[Git][xorg-team/lib/mesa][upstream-experimental] 133 commits: .pick_status.json: Update to 3b2f7ed918a5ad78c1d3756e9823a1616c1f21d7

Timo Aaltonen pushed to branch upstream-experimental at X Strike Force / lib / mesa

Commits:

f510e6a1

by Dylan Baker at 2025-10-16T11:37:29-07:00

.pick_status.json: Update to 3b2f7ed918a5ad78c1d3756e9823a1616c1f21d7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

9bb7bf9c

by Lionel Landwerlin at 2025-10-16T11:37:36-07:00

Revert "wsi: Implements scaling controls for DRI3 presentation."

This reverts commit a219308867e7cee0f3bef3f0ebc14d99c665882f.

It's failing most of the tests on Anv :

$ ./deqp-vk -n dEQP-VK.wsi.xlib.maintenance1.scaling.*

Test run totals:
  Passed:        88/2422 (3.6%)
  Failed:        576/2422 (23.8%)
  Not supported: 1758/2422 (72.6%)
  Warnings:      0/2422 (0.0%)
  Waived:        0/2422 (0.0%)

The only passing tests seem to be with this pattern :

 dEQP-VK.wsi.xlib.maintenance1.scaling.*.same_size_and_aspect

(cherry picked from commit 2baa3b8c06ab067ae78d4a924856d2d811975fec)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

fd6b9c70

by Valentine Burley at 2025-10-16T11:37:37-07:00

docs: Update LAVA caching setup

After a recent change, `piglit-traces.sh` automatically sets the caching
proxy, so update the docs to reflect this.

Also update the name of the variable from `FDO_HTTP_CACHE_URI` to
`LAVA_HTTP_CACHE_URI`.

Fixes: fa74e939bfd ("ci/piglit: automatically use LAVA proxy")

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
(cherry picked from commit 28e73a62399f5010d4c4d67f2cae2e313c05dbfb)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

84655b4b

by Lionel Landwerlin at 2025-10-16T11:37:38-07:00

anv: fix image-to-image copies of TileW images

The intermediate buffer between the 2 images is linear, its stride
should be a function of the tile's logical width.

Normally this should map to the values reported by ISL except for
TileW where for some reason it was decided to report 128 for TileW
instead of the actual 64 size (see isl_tiling_get_info() ISL_TILING_W
case)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 77fb8fb062457dad73bd763e97bf757b6cd04080)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

289c768e

by Dylan Baker at 2025-10-17T07:40:05-07:00

.pick_status.json: Update to ad421cdf2e68a1ccef80cb810c012c8469579cb6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

87113943

by Dylan Baker at 2025-10-17T07:41:23-07:00

.pick_status.json: Mark c20e2733bf8f9bb595f1bcc68ebb3d0686ef28e4 as denominated

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

45aafef6

by Xaver Hugl at 2025-10-17T07:41:25-07:00

vulkan/wsi: require extended target volume support for scRGB

It's hardly going to be useful without that

Signed-off-by: Xaver Hugl <xaver.hugl@kde.org>
Fixes: 4b663d56 ("vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland")
(cherry picked from commit 892cf427a0f62538a6943fd7500a9b23f0dd91ea)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

ca7d2daf

by Marek Olšák at 2025-10-17T07:41:27-07:00

r300: fix DXTC blits

Fixes: 9d359c6d10ad - gallium: delete pipe_surface::width and pipe_surface::height
(cherry picked from commit 733ba77bfe7fc200257eae6eac098b6577c705e3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

756618ee

by Mike Blumenkrantz at 2025-10-17T07:41:28-07:00

zink: consistently set/unset msrtss in begin_rendering

this has to always be set or unset, never persistent from previous renderpass

Fixes: 5080f2b6f55 ("zink: disable msrtss handling when blitting")
(cherry picked from commit f74cf450782509d9e386a83a3f8221a3d1bdb701)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

674e2a70

by Josh Simmons at 2025-10-17T07:41:29-07:00

radv: Fix crash in sqtt due to uninitalized value

Fixes: 772b9ce4118 ("radv: Remove qf from radv_spm/sqtt/perfcounter where applicable")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit b10c1a195266b0df668b3b5490223f648075bed1)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

42ab1c6f

by Job Noorman at 2025-10-17T07:41:30-07:00

nir: mark fneg distribution through fadd/ffma as nsz

df1876f615a ("nir: Mark negative re-distribution on fadd as imprecise")
fixed the fadd case by marking it as imprecise. This commit fixes the
ffma case for the same reason.

However, "imprecise" isn't necessary and nowadays we have "nsz" which is
more accurate here. Use that for both fadd and ffma.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 62795475e8f ("nir/algebraic: Distribute source modifiers into instructions")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit ad421cdf2e68a1ccef80cb810c012c8469579cb6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

30ba8880

by Dylan Baker at 2025-10-21T14:42:24-07:00

.pick_status.json: Update to 28fbc6addbda2ce3e264b41b6ad91a7a0d8eb788

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

c3cf272a

by Benjamin Cheng at 2025-10-21T14:42:25-07:00

radv/video: Fill maxCodedExtent caps first

Later code (i.e. max qp map extent filling) depends on this.

Fixes: ae6ea69c851 ("radv: Implement VK_KHR_video_encode_quantization_map")
Reviewed-by: David Rosca <david.rosca@amd.com>
(cherry picked from commit b1370e1935cf958b440b67b9f471499af8bc8ac8)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

bf9e1f2e

by Marek Olšák at 2025-10-21T14:42:26-07:00

winsys/radeon: fix completely broken tessellation for gfx6-7

The info was moved to radeon_info, but it was only set for the amdgpu
kernel driver. It was uninitialized for radeon.

Fixes: d82eda72a1fe3932 - ac/gpu_info: move HS info into radeon_info

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(cherry picked from commit f5b648f6d30697363d3326f408a50ae87587b1bc)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

40ff53c5

by Emma Anholt at 2025-10-21T14:42:27-07:00

wsi: Fix the flagging of dma_buf_sync_file for the amdgpu workaround.

In my regression fix, I covered one of the two paths that had stopped
setting the implicit_sync flag and thus triggered the amdgpu behavior we
don't want, but probably the less common one.

Fixes: f7cbc7b1c56c ("radv: Allocate BOs as implicit sync even if the WSI is doing implicit sync.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13942
(cherry picked from commit aa96444149fd92f80467f215985b4c39f4c00fd5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

717e8a8c

by Jose Maria Casanova Crespo at 2025-10-21T14:42:27-07:00

v3d: mark FRAG_RESULT_COLOR as output_written on SAND blits FS

With the introduction of "v3d: Add support for 16bit normalised
formats" https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35820
nir_lower_fragcolor is always called if shaders outputs_written shows
that FRAG_RESULT_COLOR is used.

But on SAND8/30 blit fragment shaders although the FRAG_RESULT_COLOR
is used, it was not marked as output_written so the lowering was not
applied.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14141
Fixes: ee48e81b26e ("v3d: Always lower frag color")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit a131530dd14b3def7c67496c2b62ccc04c70d49e)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

602b4a29

by Patrick Lerda at 2025-10-21T14:42:28-07:00

r600: fix r600_draw_rectangle refcnt imbalance

The object buf is referenced at the beginning of the
r600_draw_rectangle() function and should be freed
at the end. This issue was introduced with cbb6e0277f68.

Fixes: cbb6e0277f68 ("r600: stop using util_set_vertex_buffers")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 3b1e3a40a80bd874bc97d13846c0380313c6e7e8)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

14544ef2

by Patrick Lerda at 2025-10-21T14:42:28-07:00

r600: update nplanes support

This change fixes "piglit/bin/ext_image_dma_buf_import-export -auto".

Fixes: 02aaf360ae38 ("r600: Implement resource_get_param")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 84dc9af3d4c1a2adc6b62e3773b0ccd6dbacf77b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

13fa1460

by Timur Kristóf at 2025-10-21T14:42:29-07:00

ac/nir/ngg_mesh: Lower num_subgroups to constant

Mesh shader workgroups always have the same amount of subgroups.

When the API workgroup size is the same as the real workgroup
size, this is a small optimization (using a constant instead of
a shader arg).

When the API workgroup size is smaller than the real workgroup
size (eg. when the number of output vertices or primitves is
greater than the API workgroup size on RDNA 2), this fixes a
potential bug because num_subgroups would return the "real"
workgroup size instead of the API one.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
(cherry picked from commit d20049b430b60e1ece5bef504a3b3f694a83aa1c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

a02d8d57

by Yiwei Zhang at 2025-10-21T14:42:29-07:00

panvk: fix to advance vs driver_set properly

Should only set once outside the multidraw loop so that per draw can
patch its own own desc attribs when needed.

Fixes: a5a0dd3ccc0 ("panvk: Implement multiDrawIndirect for v10+")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
(cherry picked from commit 800c4d34306efb1e67734cefb1e75bf2b8ef2013)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

ab7bda0a

by Yiwei Zhang at 2025-10-21T14:42:29-07:00

panvk: fix to advance vs res_table properly

Fix a regression from an unfortunate typo.

Fixes: 48e8d6d207a ("panfrost, panvk: The size of resource tables needs to be a multiple of 4.")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
(cherry picked from commit 387f75f43ddbc036c2070e8386deb180282f420a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

5dcc6564

by Emma Anholt at 2025-10-21T14:42:47-07:00

nir/shrink_stores: Don't shrink stores to an invalid num_components.

Avoids a regression in the CL CTS on the next commit.

Fixes: 2dba7e60567f ("nir: split nir_opt_shrink_stores from nir_opt_shrink_vectors")
(cherry picked from commit 537cc4e0ffc1b8c3f1b6a9857749102723775a78)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

847ad886

by Mel Henning at 2025-10-21T14:42:48-07:00

nvk: Really fix maxVariableDescriptorCount w/ iub

I didn't test "nvk: Fix maxVariableDescriptorCount with iub" as
thoroughly as I should have and it regressed
dEQP-VK.api.maintenance3_check.descriptor_set because we were then
violating the requirement that maxPerSetDescriptors describes a limit
that's guaranteed to be supported (and reported as supported in
GetDescriptorSetLayoutSupport).

That commit was also based on a misreading of nvk_nir_lower_descriptors.c
where I thought that the end offset of an inline uniform block needed to
be less than the size of a UBO. That is not the case - on closer
inspection that code gracefully falls back to placing IUBs in globablmem
if necessary. So, we can afford to be less strict about our IUB sizing
and only require that IUBs follow the existing limit imposed by
maxInlineUniformBlockSize.

Fixes: ff7f785f09ce ("nvk: Fix maxVariableDescriptorCount with iub")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
(cherry picked from commit 77cd629b34f67b7035ae9c167ce1fedefe75ce32)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

f656d062

by Lionel Landwerlin at 2025-10-21T14:42:50-07:00

brw: constant fold u2u16 conversion on MCS messages

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: bddfbe7fb1 ("brw/blorp: lower MCS fetching in NIR")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit f48c9c3a3730c6beef311c2f33d06190b08de1c9)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

0d100cc0

by Lionel Landwerlin at 2025-10-21T14:42:50-07:00

brw: only consider cross lane access on non scalar VGRFs

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1bff4f93ca ("brw: Basic infrastructure to store convergent values as scalars")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 70aa028f274f5c25a4d38ba64f327557dbbb0c9e)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

dbbadebe

by Lionel Landwerlin at 2025-10-21T14:42:51-07:00

brw: fix ballot() type operations in shaders with HALT instructions

Fixes dEQP-VK.reconvergence.terminate_invocation.bit_count

LNL fossildb stats:

 Totals from 16489 (3.36% of 490184) affected shaders:
 Instrs: 3710499 -> 3710500 (+0.00%)
 Cycle count: 91601018 -> 90305642 (-1.41%); split: -1.81%, +0.40%
 Max dispatch width: 523936 -> 523952 (+0.00%); split: +0.02%, -0.01%

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 757c042e39a3281999cd65ede1ad508159ae15d4)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

e982234b

by Lionel Landwerlin at 2025-10-21T14:42:52-07:00

nir/divergence: fix handling of intel uniform block load

Those are normally uniform always, but for the purpose of fused
threads handling, we need to check their sources.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ca1533cd03 ("nir/divergence: add a new mode to cover fused threads on Intel HW")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 255d1e883d76d80e2ad5a796814ca0a9483c2ca6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

1941ada4

by Faith Ekstrand at 2025-10-21T14:42:52-07:00

panvk: Fix integer dot product properties

We already set has_[su]dot_4x8[_sat] in nir_shader_compiler_options so
we're already getting the opcodes.  We just need to advertise the
features properly.  If bifrost_compile.h is to be believed, those are
all available starting at gen 9.

Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/218
Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/219
Fixes: f7f9b3d170f5 ("panvk: Move to vk_properties")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit 38950083ae9fe5650150614687c7c46342d71d02)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

7b7cb63a

by Karol Herbst at 2025-10-21T14:42:53-07:00

nak: extract cmat load/store element offset calculation

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 05dca161437 ("nak: extract nir_intrinsic_cmat_load lowering into a function")
(cherry picked from commit f632bfc71559b6f60d9f1f4657d21b66a102bc6a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

425c49eb

by Karol Herbst at 2025-10-21T14:42:54-07:00

nak: ensure deref has a ptr_stride in cmat load/store lowering

With untyped pointer we might get a deref_cast with a 0 ptr_stride. But we
were supposed to ignore the stride information on the pointer anyway, so
let's do that properly now.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 05dca161437 ("nak: extract nir_intrinsic_cmat_load lowering into a function")
(cherry picked from commit 3bbf3f782674a25bbca01ca8dee8f58a2c33300c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

9c57c0a1

by Karol Herbst at 2025-10-21T14:42:54-07:00

nak: fix MMA latencies on Ampere

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 7a01953a396 ("nak: Add Ampere and Ada latency information")
(cherry picked from commit e7dca5a6ca3ab4f2215d48292bfa3bbb3aab6d2c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

7a30a71c

by Mel Henning at 2025-10-21T14:42:55-07:00

nvk: VK_DEPENDENCY_ASYMMETRIC_EVENT_BIT_KHR

This was missed in the original maintenance9 MR.

Fixes the flakes in test
dEQP-VK.synchronization2.op.single_queue.event.write_ssbo_compute_read_ssbo_compute.buffer_16384_maintenance9

Fixes: 7692d3c0 ("nvk: Advertise VK_KHR_maintenance9")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
(cherry picked from commit 28fbc6addbda2ce3e264b41b6ad91a7a0d8eb788)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

2a8f2ff3

by Dylan Baker at 2025-10-22T09:03:27-07:00

.pick_status.json: Update to e38491eb1850ab8b0082716b00f514f75e2a0e1a

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

e967da84

by Rhys Perry at 2025-10-22T09:03:31-07:00

amd/lower_mem_access_bit_sizes: don't create subdword UBO loads with LLVM

These are unsupported.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14127
Fixes: fbf0399517ae ("amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit 79b2fa785d51d21e56d3647ee5abb6cb78edab7a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

2b8675fd

by Rhys Perry at 2025-10-22T09:03:32-07:00

amd/lower_mem_access_bit_sizes: improve subdword/unaligned SMEM lowering

Summary of changes:
- handle unaligned 16-bit scalar loads when supported_dword=true
- increases the size of 8/16/32/64-bit buffer loads which are not dword
  aligned, which can create less SMEM loads.
- handles when "bytes" is less than "bit_size / 8"

fossil-db (gfx1201):
Totals from 26 (0.03% of 79839) affected shaders:
Instrs: 12676 -> 12710 (+0.27%); split: -0.30%, +0.57%
CodeSize: 67272 -> 67384 (+0.17%); split: -0.24%, +0.40%
Latency: 44399 -> 44375 (-0.05%); split: -0.09%, +0.04%
SClause: 352 -> 344 (-2.27%)
SALU: 3972 -> 3992 (+0.50%)
SMEM: 554 -> 528 (-4.69%)

fossil-db (navi21):
Totals from 6 (0.01% of 79825) affected shaders:
Instrs: 2192 -> 2186 (-0.27%)
CodeSize: 12188 -> 12140 (-0.39%)
Latency: 10037 -> 10033 (-0.04%); split: -0.12%, +0.08%
SMEM: 124 -> 118 (-4.84%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: fbf0399517ae ("amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit 8829fc3bd64b9f2ac62f2339fa9cf6fc0a149cba)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

c1cf6e75

by Rhys Perry at 2025-10-22T09:03:34-07:00

amd/lower_mem_access_bit_sizes: be more careful with 8/16-bit scratch load

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.3
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit e89b22280fe5f65dfdd749af0f5da892d0bb9dda)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

10475e8a

by Rhys Perry at 2025-10-22T09:03:36-07:00

amd/lower_mem_access_bit_sizes: fix shared access when bytes<bit_size/8

This can happen with (for example) 32x2 loads with
align_mul=4,align_offset=2.

This patch does bit_size=min(bit_size,bytes) to prevent num_components
from being 0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 52cd5f7e69fd ("ac/nir_lower_mem_access_bit_sizes: Split unsupported shared memory instructions")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit b18421ae3d20645aea615ff4b2ae2e6c544a7b1f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

4202ea6c

by Olivia Lee at 2025-10-22T09:03:37-07:00

panfrost: fix cl_local_size for precompiled shaders

nir_lower_compute_system_values will attempt to lower
load_workgroup_size unless workgroup_size_variable is set. For precomp
shaders, the workgroup size is set statically for each entrypoint by
nir_precompiled_build_variant. Because we call
lower_compute_system_values early, it sets the workgroup size to zero.
Temporarily setting workgroup_size_variable while we are still
processing all the entrypoints together inhibits this.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: 20970bcd965 ("panfrost: Add base of OpenCL C infrastructure")
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit a410d90fd254dd4930e72547de430a8cf5daf13b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

94ec7c68

by Faith Ekstrand at 2025-10-22T09:03:37-07:00

util: Don't advertise cache ops on x86 without SSE2

Fixes: 555881e57499 ("util/cache_ops: Add some cache flush helpers")
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
(cherry picked from commit 3739d7a90c3d2406a3297a973c3de4c3dbe83050)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

0182cde8

by Faith Ekstrand at 2025-10-22T09:03:38-07:00

util: Build util/cache_ops_x86.c with -msse2

__builtin_ia32_clflush() requires -msse2 so we need to set -msse2 at
least for building that file.  Fortunately, there are no GPUs that
actually need userspace cache flushing that can ever be bolted onto a
pre-SSE2 x86 CPUs.

Fixes: 555881e57499 ("util/cache_ops: Add some cache flush helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14134
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
(cherry picked from commit efbecd93baa35b4bbeb5f370893865568a577e6e)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

49bfddbd

by Pierre-Eric Pelloux-Prayer at 2025-10-22T09:03:39-07:00

radeonsi: propagate shader updates for merged shaders

In case of merged shaders (eg: VS+GS), a change to VS should trigger
a GS update.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13935
Fixes: b1a34ac95df ("radeonsi: change do_update_shaders boolean to a bitmask")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 90103fe61862b8cd3703dea5d906244f1bc61e4f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

be191cef

by Benjamin Cheng at 2025-10-22T09:03:39-07:00

radv/video_enc: Cleanup slice count assert

This was left over when first enabling multiple slice encoding.

Fixes: 63e952ff2cc ("radv/video: Support encoding multiple slices")
Reviewed-by: David Rosca <david.rosca@amd.com>
(cherry picked from commit b6d6c1af73b1e1cad5f84b59eaedad4faacd8dda)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>

d9812eae

by Dylan Baker at 2025-10-22T16:13:33-07:00

VERSION: bump for rc2

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>

fe3a3b08

by Dylan Baker at 2025-10-24T07:54:46-07:00

.pick_status.json: Update to fd55e874ed09a04447ebd4dae25c98df2621ef7d

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

2c1c52a8

by Valentine Burley at 2025-10-24T07:54:52-07:00

tu: Fix indexing with variable descriptor count

Based on RADV.
The Vulkan spec says:
    "If bindingCount is zero or if this structure is not included in
     the pNext chain, the VkDescriptorBindingFlags for each descriptor
     set layout binding is considered to be zero. Otherwise, the
     descriptor set layout binding at
     VkDescriptorSetLayoutCreateInfo::pBindings[i] uses the flags in
     pBindingFlags[i]."

Fixes dEQP-VK.api.maintenance3_check.* in VKCTS 1.4.4.0.

Cc: mesa-stable

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
(cherry picked from commit 17e25b4983dc333d971c7b6eed4bdae741a9bf03)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

d5f7261c

by Valentine Burley at 2025-10-24T07:54:54-07:00

tu: Fix maxVariableDescriptorCount with inline uniform blocks

It must not be larger than maxInlineUniformBlockSize.

Fixes VKCTS 1.4.4.0's
dEQP-VK.api.maintenance3_check.support_count_inline_uniform_block*.

Cc: mesa-stable

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
(cherry picked from commit fd2fa0fbc93792bd9c588c61b1ba37fe05893bba)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

1648f759

by Lionel Landwerlin at 2025-10-24T07:54:55-07:00

anv: rename structure holding 3DSTATE_WM_DEPTH_STENCIL state

Cc stable for the next commit.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit 8d05b7b72e70fe35d6ff6b5d65272ec520a707f3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

dcecd8fd

by Lionel Landwerlin at 2025-10-24T07:54:56-07:00

brw: handle GLSL/GLSL tessellation parameters

Apparently various tessellation parameters come specified from
TESS_EVAL stage in GLSL while they come from the TESS_CTRL stage in
HLSL.

We switch to store the tesselation params more like shader_info with 0
values for unspecified fields. That let's us merge it with a simple OR
with values from from tcs/tes and the resulting merge can be used for
state programming.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a91e0e0d61 ("brw: add support for separate tessellation shader compilation")
Fixes: 50fd669294 ("anv: prep work for separate tessellation shaders")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit f3df267735e47703017e640ff5b796d56ddbc36b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

bfd09d98

by Lionel Landwerlin at 2025-10-24T07:54:57-07:00

nir/lower_io: add missing levels intrinsics to get_io_index_src_number

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c7ac46a1d8 ("nir/lower_io: add get_io_index_src_number support for image intrinsics")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit aa929ea706e32f4acfe8b21eaebb2fe201afd580)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

cd253df9

by Faith Ekstrand at 2025-10-24T07:54:58-07:00

nvk: Include the chipset in the pipeline/binary cache UUID

Cc: mesa-stable
(cherry picked from commit d1793c7a594f49f8870beeef99bd3edcdb1ddb9f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

3f9f4d79

by Faith Ekstrand at 2025-10-24T07:54:59-07:00

nvk: Disable sampleLocationsSampleCounts for 1x MSAA

Suggested-by: Mel Henning <mhenning@darkrefraction.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14108
Fixes: a34edc7500c8 ("nvk: Fill out sample locations on Maxwell B+")
(cherry picked from commit aa0f404f7b7d2d0b10f5a7d8b9a98006a6b5835b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

2a0a2cc5

by Konstantin Seurer at 2025-10-24T07:54:59-07:00

aco: Fixup out_launch_size_y in the RT prolog for 1D dispatch

launch_size_y is set to ACO_RT_CONVERTED_2D_LAUNCH_SIZE for 1D
dispatches. The prolog needs to set it to 1 so that the app shader
loads the correct value.

cc: mesa-stable

(cherry picked from commit 47ffe2ecd42625405b16141868af81dc3f9006c6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

6a7effe0

by Xaver Hugl at 2025-10-24T07:55:00-07:00

vulkan/wsi: remove support for VK_COLOR_SPACE_EXTENDED_SRGB_NONLINEAR_EXT

It's not really clear whether or not it should use gamma 2.2 or the piece-wise
transfer function, or how clients would use it for wider gamut in general.
Currently no compositors I know of support ext_srgb, so this shouldn't affect
applications in practice.

Signed-off-by: Xaver Hugl <xaver.hugl@kde.org>
Fixes: 4b663d56 ("vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland")
(cherry picked from commit 14fcf145e3d95975b9d93d8c91b20331709b9d22)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

159d3974

by Lionel Landwerlin at 2025-10-24T07:55:01-07:00

anv/brw: fix output tcs vertices

brw_prog_tcs_data::instances can be divided by vertices per threads on
earlier generations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a91e0e0d61 ("brw: add support for separate tessellation shader compilation")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit e450297ea9d5b715e6e34a6a3bb7a8b3ec5f4890)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

a9653fa0

by Lionel Landwerlin at 2025-10-24T07:55:02-07:00

anv: destroy sets when destroying pool

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14169
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit 2689056c82dde882238058d183f6455750d4e340)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

65eb3aed

by Connor Abbott at 2025-10-24T07:55:02-07:00

tu: Fix RT count with remapped color attachments

The index of each RT is the remapped color attachment index, so we have
to use the remapped indices when telling the HW the number of RTs.

This fixes KHR-GLES3.framebuffer_blit.scissor_blit on ANGLE once we
enabled VK_EXT_multisampled_render_to_single_sampled, which switched
ANGLE to using dynamic rendering with
VK_KHR_dynamic_rendering_local_read.

Fixes: d50eef5b06f ("tu: Support color attachment remapping")
(cherry picked from commit 8d276e0d70151744509cbd7bb89ae8b58e8fed93)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

fb2273df

by Mauro Rossi at 2025-10-24T07:55:03-07:00

util: Fix gnu-empty-initializer error

Fixes the following building error happening with clang:

../src/util/os_file.c:291:29: error: use of GNU empty initializer extension [-Werror,-Wgnu-empty-initializer]
   struct epoll_event evt = {};
                            ^
1 error generated.

Fixes: 17e28652 ("util: mimic KCMP_FILE via epoll when KCMP is missing")
Cc: "25.3"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(cherry picked from commit 7bbbfa667036e6d495c88665bdc851623903753a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

b74000db

by Faith Ekstrand at 2025-10-24T07:55:04-07:00

nvk: Emit inactive vertex attributes

VK_KHR_maintenance9 requires that vertex attributes in shaders which map
to vertex attributes that aren't bound at the API return a consistent
value.  In order to do this, we need toemit SET_VERTEX_ATTRIBUTE_A, even
for unused attributes.  The RGBA32F format was chosen to ensure we
return (0, 0, 0, 0) from unbound attributes.

Fixes: 7692d3c0e1a2 ("nvk: Advertise VK_KHR_maintenance9")
(cherry picked from commit d39221cef30d5c54b3d7651b6d89ab85c23e0480)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

ba107091

by Faith Ekstrand at 2025-10-24T07:55:05-07:00

nvk: Look at the right pointer in GetDescriptorInfo for SSBOs

It doesn't actually matter but we shouldn't poke at the wrong union
field.

Fixes: 77db71db7dfc ("nvk: Implement GetDescriptorEXT")
(cherry picked from commit a13474939dffe2e710aa1d6a38c5c458fc7a0752)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

7f759310

by Faith Ekstrand at 2025-10-24T07:55:05-07:00

nvk: Capture/replay buffer addresses for EDB capture/replay

Fixes: 3f1c3f04be93 ("nvk: Advertise VK_EXT_descriptor_buffer")
(cherry picked from commit 998dbd43d3c3dd7f2cc0953aa8c4aeb2151964dc)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

424f37b3

by Samuel Pitoiset at 2025-10-24T07:55:06-07:00

radv: dirty dynamic descriptors when required

The user SGPRS might be different and dynamic descriptors need to be
re-emitted again

This fixes a regression with ANGLE, and VCKTS is currently missing
coverage.

Fixes: a47952d495e ("radv: upload and emit dynamic descriptors separately from push constants")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14146
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 54a6c81d3a20e6b5e6ac8b36f291ab2a8761fc95)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

606ebb04

by Faith Ekstrand at 2025-10-24T07:55:07-07:00

panvk/shader: [de]serialize desc_info.max_varying_loads

Fixes: de86641d3f4f ("panvk: Limit AD allocation to max var loads in v9+")
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit a546484ed9ed235674b5bba093def5c21f7dd151)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

2cfd3c52

by Faith Ekstrand at 2025-10-24T07:55:08-07:00

panvk/shader: Use the right copy size for deserializing dynamic UBOs/SSBOs

Fixes: 563823c9ca9e ("panvk: Implement vk_shader")
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit 64ad337036cf38c007047f4cf185ead9dfe4568d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

1c52a944

by Connor Abbott at 2025-10-24T08:07:28-07:00

tu: Don't patch GMEM for input attachments never in GMEM

This can happen if we resolve to a resolve attachment and then use that
resolve attachment as an input attachment in a later subpass. We don't
need to put it in GMEM, but it's still considered "written" because
input attachment reads need a dependency after the resolve.

MSRTSS input attachment tests effectively created such a scenario after
lowering to transient multisample attachments and inserting resolves.

Cc: mesa-stable
(cherry picked from commit d491a79027b175f2b13536b5db67b471ba58bd28)

Conflicts:
	src/freedreno/vulkan/tu_pass.cc

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

f142fdc2

by Connor Abbott at 2025-10-24T08:07:28-07:00

tu: Fix 3d load path with D24S8 on a7xx

We need to always use the FMT6_Z24S8_AS_R8G8B8A8 format for GMEM even if
UBWC is disabled, as already done for the 2d store path. Because we
use the pre-baked RB_MRT_BUF_INFO register value, this means we have to
override it.

Cc: mesa-stable
(cherry picked from commit 9417ce287c29495090ce88df3084a58542db6966)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

9728bbf7

by Connor Abbott at 2025-10-24T08:07:30-07:00

tu: Also disable stencil load for attachments not in GMEM

We were accidentally still emitting loads for D32S8 resolve attachments.

Cc: mesa-stable
(cherry picked from commit a3652af380cc1d4ec55fe3f784b7c66082fa2be1)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

498a25cf

by Olivia Lee at 2025-10-27T09:34:33-07:00

hk: fix data race when initializing poly_heap

hk_heap is called during command buffer recording, which may be
concurrent, so writing dev->heap without synchronization is a data race.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: 5bc82848163 ("hk: add Vulkan driver for Apple GPUs")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
(cherry picked from commit bca29b1c92320dea0004341a08cc76a18e3edaf3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

b7681398

by Dylan Baker at 2025-10-27T09:34:33-07:00

.pick_status.json: Update to 45a762727cf8708392b6de38616909543c799923

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

d9636807

by Dylan Baker at 2025-10-27T09:34:33-07:00

intel/compiler/brw: Add assert that we don't have a negative value

Coverity notices that `nir_get_io_index_src_number` could return -1, and
that we use it to index an array. It cannot understand that -1 only
happens for unhandled enum values, but all of these are handled. Add an
assert to help it out.

CID: 1667234
Fixes: 37a9c5411f4 ("brw: serialize messages on Gfx12.x if required")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit a5b9f428f9bbb577e70b652a11777581ece3f325)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

f02f5e21

by Mary Guillemard at 2025-10-27T09:34:33-07:00

hk: Fix maxVariableDescriptorCount with inline uniform block

Same problem as NVK on VKCTS 1.4.4.0

Fixes: 5bc828481630 ("hk: add Vulkan driver for Apple GPUs")
Signed-off-by: Mary Guillemard <mary@mary.zone>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 8447b99f61aa28d0bf233fe984b10e5a4368a1df)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

74880f89

by Mary Guillemard at 2025-10-27T09:34:33-07:00

hk: Disable 1x in sampleLocationsSampleCounts

We don't support it, everyone dropped support for that, let's not expose it.

Fixes: 5bc828481630 ("hk: add Vulkan driver for Apple GPUs")
Signed-off-by: Mary Guillemard <mary@mary.zone>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 7e636d52f17c03a909cfa348033cfe6e7c0dbcba)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

28e172e9

by Mary Guillemard at 2025-10-27T09:34:33-07:00

hk: Remove unused allocation in queue_submit

Unused and leaking memory, found with address sanitizer.

Fixes: c64a2bbff5a3 ("asahi: port to stable uAPI")
Signed-off-by: Mary Guillemard <mary@mary.zone>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 64131475a8371105a923e021299f6d8306654c53)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

04045385

by Sagar Ghuge at 2025-10-27T09:34:33-07:00

anv: Call brw_nir_lower_rt_intrinsics_pre_trace lowering pass

Call this pass before nir_lower_shader_calls().

Fixes: d39e443e ("anv: add infrastructure for common vk_pipeline")
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 006085e6769c3697c29cd5087dfabe7b5b8d046a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

5e1a88ce

by Mary Guillemard at 2025-10-27T09:34:33-07:00

hk: Make width and height per block in HIC

We were assuming that every formats used for HIC had a block widgh and
height of 1x1.

This is wrong for compressed formats like BC5, ASTC, ect.

Fixes: 5bc828481630 ("hk: add Vulkan driver for Apple GPUs")
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Eric Engestrom <eric@igalia.com>
(cherry picked from commit 887f06a966f4ac650701b9d1421dd2f67fc23ae5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

b3470359

by Mary Guillemard at 2025-10-27T09:34:33-07:00

hk: Allocate the temp tile buffer in copy_image_to_image_cpu

We may require a bigger more than 16KiB to handle the image copy.
We now always allocate a buffer to handle it properly fixing the
remaining failures on VKCTS 1.4.4.0 for HIC.

Fixes: 5bc828481630 ("hk: add Vulkan driver for Apple GPUs")
Signed-off-by: Mary Guillemard <mary@mary.zone>
(cherry picked from commit d37ba302d0055f72577a47dcc4eff5400e7ecdb1)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

5ae84740

by Taras Pisetskyi at 2025-10-27T09:34:33-07:00

drirc/anv: force_vk_vendor=-1 for Wuthering Waves

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12459

Signed-off-by: Taras Pisetskyi <taras.pisetskyi@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit dcd9b90affab27a99a6ee44ce6d0ac3f4b5990f1)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

05e5db1a

by Natalie Vock at 2025-10-27T09:34:33-07:00

nir/lower_shader_calls: Repair SSA after wrap_instrs

Wrapping jump instructions that are located inside ifs can break SSA
invariants because the else block no longer dominates the merge block.
Repair the SSA to make the validator happy again.

Cc: mesa-stable
(cherry picked from commit 50e65dac794511fb392fd9103f50c553d69a56d2)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

f1f32d55

by Job Noorman at 2025-10-27T09:34:33-07:00

ir3/ra: fix assert during file start reset

While accounting for an input register's merge set when resetting the
file start after the preamble, we implicitly assume that the allocated
register is the preferred one by asserting that the register's merge set
offset is not smaller than its physreg (to prevent an underflow).
However, inputs are not guaranteed to have their preferred register
allocated which causes the assert to get triggered.

Fix this by only taking the whole merge set into account for inputs that
actually got their preferred register allocated.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 9d4ba885bb8 ("ir3/ra: make main shader reg select independent of preamble")
(cherry picked from commit f84d85790ef0bb45488d775fc6c79b1cf1714f80)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

8010d0cd

by Mike Blumenkrantz at 2025-10-27T09:34:33-07:00

zink: disable primitiveFragmentShadingRateMeshShader feature

features are auto-enabled, but some of them cause validation errors
which are simple to work around

Fixes: 90f3c573374 ("zink: hook up VK_EXT_mesh_shader")
(cherry picked from commit a2ef369abf78ddc71725079b687c9da5d932b312)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

9ba765e3

by Sagar Ghuge at 2025-10-27T09:34:33-07:00

brw/rt: Move nir_build_vec3_mat_mult_col_major helper to header

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 3edeb1e191980f1293f12a5515843b5f97fc249c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

f63a5df3

by Sagar Ghuge at 2025-10-27T09:34:33-07:00

brw/rt: fix ray_object_(direction|origin) for closest-hit shaders

We were returning world BVH level for origin/direction, this commit
fixes by retuning correct object BVH level origin/direction.

Fixes: aaff19135644 ("brw/rt: fix ray_object_(direction|origin) for closest-hit shaders")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 89fbcc8c3413016a23720d82ffb82d47d819912c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

3e227a04

by Dylan Baker at 2025-10-28T12:53:10-07:00

.pick_status.json: Update to 32b646c5976f64152a004d4c83962ca14c46154f

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

9311f170

by Marek Olšák at 2025-10-28T12:53:15-07:00

zink: fix mesh and task shader pipeline statistics

Fixes: 9d0e73335af - zink: enable GL_EXT_mesh_shader
(cherry picked from commit 41a8c4d37ca15a17f9480d682ab444161fd67065)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

2e17fd0c

by Lionel Landwerlin at 2025-10-28T12:53:16-07:00

vulkan/render_pass: Add a missing sType

Fixes: 3a204d5cf370 ("vulkan/render_pass: Add a better helper for render pass inheritance")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
(cherry picked from commit c5740c2548a023f4e03eae6ff53b598536ed2704)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

ac492d42

by Benjamin Cheng at 2025-10-28T12:53:17-07:00

radv/video: Override H265 SPS block size parameters

VCN only supports this set of parameters.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Cc: mesa-stable
(cherry picked from commit 84b6d8e0d7789ea18867aa36fe4fa9f4eeed9475)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

8a2bf930

by Benjamin Cheng at 2025-10-28T12:53:18-07:00

radv/video: Override H265 SPS unaligned resolutions

VCN requires 64x16 alignment for HEVC. When the app requests non-aligned
resolutions, make up for it with conformance window cropping.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Cc: mesa-stable
(cherry picked from commit cef8eff74d3f05a2cf5208f42c20c46c09678785)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

3a71d947

by Job Noorman at 2025-10-28T12:53:18-07:00

spirv: don't set in_bounds for structs

The arr::in_bounds field was set unconditionally for every deref created
for a chain. For struct derefs, which don't have this field, this would
write to an unused memory location, which is probably why this never
caused issues.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: f19cbe98e32 ("nir,spirv: Preserve inbounds access information")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 0ac55b786ac357a468ca918fc848c7fe68edfc6c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38167>

315b6889

by Dylan Baker at 2025-10-30T11:35:06-07:00

VERSION: bump for rc3

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>

fd777ce6

by Dylan Baker at 2025-10-30T12:13:41-07:00

.pick_status.json: Update to 33342848451ca06deb054fad94de3cea3a9efe63

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

3ce875a2

by Alyssa Rosenzweig at 2025-10-30T12:13:52-07:00

anv: use D3D-compatible texturing for Proton

Intel & AMD Direct3D drivers modify their rounding behaviour for texturing to
match Direct3D expectations. Such behaviour is not conformant in Vulkan, and
Intel hardware lacks a reasonable way to get NVIDIA's behaviour (which uniquely
works for Vulkan & Direct3D). The second best choice is to use
Direct3D-compatible behaviour for Proton (via driconf) and our current
Vulkan-conformant behaviour everywhere else. Given the APIs diverge and there is
no Vulkan extension to control the behaviour explicitly, driconf'ing on the
engineName is the reasonable solution.

anv already has a anv_force_filter_addr_rounding driconf option to force
Direct3D behaviour for certain Direct3D titles. Here we simply apply it to all
D3D10+ titles, aligning us with the Windows driver.

Note that D3D9 does not have this behaviour. We therefore use standard Vulkan
behaviour for D3D9 to avoid breaking D3D9 titles, even though the engineName is
the same as D3D10+.

This is the same solution radv uses, they call it radv_disable_trunc_coord. We
could unify the driconf entries later.

See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38098#note_3166306
for a more detailed analysis, as well as the linked references:

   https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27337
   https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911
   https://github.com/HansKristian-Work/vkd3d-proton/pull/1884

This fixes misrendering in piles of Direct3D games run on anv via Proton,
including Assassin's Creed Valhalla.

Cc: mesa-stable
Closes: #13886
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Co-authored-by: Calder Young <cgiacun@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
(cherry picked from commit 7a719527626313d18a3d41d009d3e05c98348aa2)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

0edb1852

by Sagar Ghuge at 2025-10-30T12:13:53-07:00

vulkan/runtime: Fix typo in stack size calculation

Fixes: 69a04151db4 ("vulkan/runtime: add ray tracing pipeline support")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
(cherry picked from commit a00560f7633232c53bf90ba1ac9835ebd1d5e228)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

7e15070e

by Mike Blumenkrantz at 2025-10-30T12:13:54-07:00

zink: collapse gfx pipeline fetching and binding conditionals

this avoids taking the wrong conditional if a pipeline fetch fails

cc: mesa-stable

(cherry picked from commit 0b24fd174a8cf9543b07bdfa150d868d673ce44a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

a7a020dd

by Mike Blumenkrantz at 2025-10-30T12:13:54-07:00

zink: collapse mesh pipeline fetching and binding conditionals

this avoids taking the wrong conditional if a pipeline fetch fails

cc: mesa-stable

(cherry picked from commit 343eef990e54d974d811f7414e79a8854b8c97f9)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

6670d074

by Gert Wollny at 2025-10-30T12:13:55-07:00

r600/sfn: extract function to update group after instr insert

Fixes: 359bfc3138e ("r600/sfn: make sure that kill and update pred are not in the same group")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit a7f477b51f7b2f7861a3d1cc8efca1cc842b317e)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

a12369eb

by Gert Wollny at 2025-10-30T12:13:55-07:00

r600/sfn: move some common code into try_readport

Fixes: 359bfc3138e ("r600/sfn: make sure that kill and update pred are not in the same group")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 51e7c477d6e1994bf16e2d8dfda96966a8d0252c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

e082f6b6

by Gert Wollny at 2025-10-30T12:13:56-07:00

r600/sfn: Track whether a ALU group has a exec flag update

Fixes: 359bfc3138e ("r600/sfn: make sure that kill and update pred are not in the same group")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 0d065a2421d54ab3e95d3c2cd9fa4f3276f9fa1a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

2c67b0fa

by Gert Wollny at 2025-10-30T12:13:57-07:00

r600/sfn: make sure kill and update_exec don't happen in one group

v2: - Correctly test in multi-slot split whether the group has kill if
      we want to add a multi-slot op.
    - update group_has_predicate if an according vector op was added

Fixes: 359bfc3138e ("r600/sfn: make sure that kill and update pred are not in the same group")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 317345cc980c510b3d4600a80f87580aea5a5ac5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

093c7d9d

by Mike Blumenkrantz at 2025-10-30T12:13:57-07:00

zink: don't destroy old push layout when enabling fbfetch descriptor

this may be in use by programs, and adding tracking/refcounting just to
delete a descriptor layout isn't worth the effort

cc: mesa-stable

(cherry picked from commit 272cf1db8e7596e0eeddecc52c90629f939892d8)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

205fe1a2

by Dmitry Osipenko at 2025-10-30T12:13:58-07:00

virtio/vdrm: Fix varying offsets of struct vdrm_device members

Struct virgl_renderer_capset_drm has a varying size depending on whether
AMDGPU driver is enabled or not. This breaks offset of struct vdrm_device
members for non-AMD drivers when Mesa is built with multiple native context
drivers including the AMD driver. Place varying capsets in the end struct
vdrm_device to mitigate the issue.

Fixes: 57362807307d ("virtio/vdrm: add ENABLE_DRM_AMDGPU for c_args")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
(cherry picked from commit bd8377bb0416bd30007aa49573579e2711cc2f8e)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

770e0957

by Eric Engestrom at 2025-10-30T12:13:58-07:00

asahi/virtio: fix memleak

Fixes: c64a2bbff5a3370bca7f ("asahi: port to stable uAPI")
(cherry picked from commit fdef10916ee61e4440189b9fad5d09c6295b7a71)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

f69d1abf

by Samuel Pitoiset at 2025-10-30T12:14:00-07:00

radv: ignore dual-source blending when blending isn't enabled for MRT0

The Vulkan spec says:
    "VUID-vkCmdDraw-maxFragmentDualSrcAttachments-09239
     If blending is enabled for any attachment where either the source
     or destination blend factors for that attachment use the secondary
     color input, the maximum value of Location for any output attachment
     statically used in the Fragment Execution Model executed by this
     command must be less than maxFragmentDualSrcAttachments"

Which means it must be disabled.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14190
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit b2badb2b241b3f5637133634b6bb48ebb90e4fed)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

46f04221

by Eric Engestrom at 2025-10-30T12:14:04-07:00

util/meson: don't build libmesa_util_clflushopt unless needed

Fixes: 555881e57499bc38f098 ("util/cache_ops: Add some cache flush helpers")
(cherry picked from commit ccf33664e89bec2afb6dd1297ebfee1972d5fb3c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

9aeac1e0

by Eric Engestrom at 2025-10-30T12:14:05-07:00

util/meson: don't build libmesa_util_clflush unless needed

Fixes: efbecd93baa35b4bbeb5 ("util: Build util/cache_ops_x86.c with -msse2")
(cherry picked from commit 0fe0acd4c3896d2446ec48510928ecb46f504198)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

182877f3

by Faith Ekstrand at 2025-10-30T12:14:05-07:00

nvk: Don't re-initialize the descriptor writer if the set matches

The logic here before was wrong.  In the case where the set is the same,
it would avoid the flush but then re-initialize anyway, loosing the
dirty information and causing us not to actually flush out all the
descriptors.

Fixes: 1f0fda22f7fe ("nvk: Flush descriptor set maps")
(cherry picked from commit 2f6b3b6b91f25c3f9d3abdcb3fdfb7f47a0196d9)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

0a0d08df

by Dylan Baker at 2025-10-31T12:07:09-07:00

.pick_status.json: Update to e44a776f4751d665efc447d8fe8e6c01d25a60c5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

a46307a7

by Paul Gofman at 2025-10-31T12:07:11-07:00

driconf: add a workaround for Investigation Stories : gunsound

CC: mesa-stable
(cherry picked from commit 63aec75981c9aedf1efb98c33a99e3ceb05ec0ca)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

86313f95

by Gert Wollny at 2025-10-31T12:07:12-07:00

r600/sfn: AR loads are not dependend on the future and other code blocks

If the AR is loaded from a register changing that register in a loop was
resulting in a scheduling failure because the AR load was made dependend
on a later instruction. Fix the dependencies by only using dependencies on
older instruuctions in the same block.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14114
Fixes: d21054b4bc9 ("r600/sfn: Add pass to split addess and index register loads")

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
(cherry picked from commit 43d9765e35d936a54fb5a1846ce21b06edb1c3da)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

3ddddf78

by Tapani Pälli at 2025-10-31T12:07:12-07:00

anv: bring back some lost game drirc workarounds for subgroups

Fixes: d39e443ef88 (" anv: add infrastructure for common vk_pipeline")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit f48df6f45c80e150eff13734fb1a3df9eda86c99)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

1e885e7a

by Samuel Pitoiset at 2025-10-31T12:07:13-07:00

radv: add a workaround for illegal depth/stencil descriptors with No Man's Sky

Using descriptors with both depth and stencil aspects is illegal in
Vulkan and this hangs the GPU.

Use NULL descriptors to mitigate the issue. Note that AMDVLK also
ignores them.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13325
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit cb4e0c414093170e5edf31591d60db3f02ac857b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

12c82aaa

by Icenowy Zheng at 2025-10-31T12:07:14-07:00

gallivm: orcjit: remember Context in addition to ThreadSafeContext

The llvm::orc::ThreadSafeContext object wraps an llvm::Context and keeps
its reference.

As we are no longer able to squeeze out Context from ThreadSafeContext
in LLVM 21, do not let ThreadSafeContext create Context implicitly for
LLVM 21, instead explicitly create Context and then remember it.

This also eliminates the code creating a Context that is never disposed.

Fixes: cd129dbf8af2 ("gallivm: support LLVM 21")
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
(cherry picked from commit cc60a7a39d11251c96dafcc4c017be502c06abf5)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

629a0a4d

by David Rosca at 2025-11-03T13:17:38+01:00

radv/video: Introduce two levels of write_memory support

Print warning when using write_memory with firmwares that require
PCIe atomics support.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 8e1d74bbb466034b794cdd9e1552000c53cfc653)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

ce6c6a7a

by David Rosca at 2025-11-03T13:17:41+01:00

radv/video: Only use write_memory for encode feedback with full support

write_memory is used after encoding every frame to mark the feedback
buffer as ready. Only use it when write_memory can work without PCIe
atomics support.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 874e02003a0b6c946e2a26fae14b294918e5ac8d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

3086692b

by Dylan Baker at 2025-11-04T10:16:42-08:00

.pick_status.json: Update to 27d9e4ec2a13a957f416a234a93bf2f0c2c9c56c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

9bad1beb

by Ian Romanick at 2025-11-04T10:16:42-08:00

brw: Apply Gfx9 vgrf127 workaround in more cases

No shader-db changes on any Intel platform.

fossil-db:

Skylake
Intel(R) HD Graphics 530 (SKL GT2)
Totals:
Cycle count: 57669758527 -> 57669757913 (-0.00%); split: -0.00%, +0.00%

Totals from 10 (0.00% of 1736875) affected shaders:
Cycle count: 274949 -> 274335 (-0.22%); split: -0.36%, +0.14%

This change is likely due to subtle differences of different registers
being allocated.

In addition, fossils/google-meet-clvk/BgBlur.1f58fdf742c27594.1.foz and
fossils/google-meet-clvk/Relight.1f58fdf742c27594.1.foz stopped failing
EU validation on Gfx9 platforms.

Closes: #14171
Fixes: e7b7d572b3b ("intel/fs/ra: Re-arrange interference setup")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
(cherry picked from commit 3e6af6c5bb75e5d2823c45d4ccdd90bf2c11b6d7)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

55a37838

by Ian Romanick at 2025-11-04T10:16:42-08:00

elk: Apply vgrf127 workaround in more cases

No shader-db changes on Broadwell. Older platforms were not tested.

Fixes: e7b7d572b3b ("intel/fs/ra: Re-arrange interference setup")
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
(cherry picked from commit 2e8b89ec60f700c04347ab850d25aa6d85e2083b)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

3dab7315

by Alyssa Rosenzweig at 2025-11-04T10:16:42-08:00

asahi,ail: fix multi-plane imports

We need to handle plane offsets everywhere. I noticed this broken before but
didn't realize it was a GL driver issue. Fix is easy, wrote this on my sofa
while waking up in the morning.

Fixes gst-launch-1.0 v4l2src ! glimagesink

Note that cheese & snapshot both still hang for some reason due to
libgstpipewire, but the Mesa side should be fine now.

Closes: #14217
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Cc: mesa-stable
(cherry picked from commit aa9f93711692504bc216423cdff76a86b40c6fa3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

90b6c3a8

by Janne Grunau at 2025-11-04T10:16:42-08:00

hk: Report the correct plane count in VkDrmFormatModifierProperties2?EXT

Fixes import of planar formats like NV12 in gtk4. Allows
`gst-launch-1.0 v4l2src ! gtk4paintablesink` to use vulkan instead of
falling back to OpenGL.

Closes: #14217
Cc: mesa-stable
Signed-off-by: Janne Grunau <j@jannau.net>
(cherry picked from commit 83b97379dc2d7f8db65fd88a8773a495ca70bbd8)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

7c185409

by Marek Olšák at 2025-11-04T10:16:42-08:00

Revert ABI breakage "amd: Add user queue HQD count to hw_ip info"

This reverts commit 56d758d321fd87b883106585b564fac92aa0793a.

It broke ABI between Mesa and libdrm, causing crashes due to stack smashing.

See: https://gitlab.freedesktop.org/mesa/libdrm/-/issues/121#note_3172362

Fixes: 56d758d321fd87b883106585b564fac92aa0793a
(cherry picked from commit 5d92c92ce56c4c3b9d98936fee51129281923e1a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38268>

d527eedb