-
4369c24d
by Eric Engestrom at 2025-09-17T17:16:23+02:00
docs: add sha sum for 25.2.3
-
3a22bd0d
by Eric Engestrom at 2025-10-01T11:30:47+02:00
.pick_status.json: Update to 42a78a1aae19f855b049462d7714cd1f07ca12e4
-
0dcca970
by Eric Engestrom at 2025-10-01T11:30:47+02:00
.pick_status.json: Mark 59278c223614a3877fcbbabb8c9eb3bd4acc3836 as denominated
-
af7843a2
by Daniel Schürmann at 2025-10-01T11:30:48+02:00
aco/isel: rename emit_readfirstlane() -> emit_vector_as_uniform()
Also allow to use p_as_uniform and improve vector splitting.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36133>
(cherry picked from commit 4632ee4c376808842dc717549b090818762e743d)
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df380cfa
by Rhys Perry at 2025-10-01T11:30:48+02:00
aco: workaround load tearing for load_shared2_amd
This probably has the same issue as load_shared.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04956d54ce5b ("aco: force uniform result for LDS load with uniform address if it can be non uniform")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
(cherry picked from commit 8931672eef7f08714a565c4a598af432eb413322)
-
d1dfd5e5
by Mike Blumenkrantz at 2025-10-01T11:30:48+02:00
zink: wait on queues during screen destroy
there might somehow be operations active
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36289>
(cherry picked from commit 61633e0a2e8461250441fcbec11babf9fbe24e5e)
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02ebf5ab
by Mike Blumenkrantz at 2025-10-01T11:30:48+02:00
zink: account for kopper dt not having a swapchain when pruning batch usage
this could be pending deletion
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
(cherry picked from commit 6369dbd6be1d148ec7aa2b72885f247b5120511a)
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fb588163
by Mike Blumenkrantz at 2025-10-01T11:30:48+02:00
zink: check for zink_batch_state::ctx before using during descriptor state reset
this is a screen function, so ctx may be null
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
(cherry picked from commit e64f0414b36b04f14e4aefdc7941e31757fe04a1)
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7de1ff45
by Eric Engestrom at 2025-10-01T11:30:48+02:00
radv: make sure fp16 is enabled consistently on gfx8
Fixes `dEQP-VK.api.info.vulkan1p4_limits_validation.general`
Fixes: f0f4ae17136c9b90eb47 ("radv: Add radv_enable_float16_gfx8 drirc and enable for Indiana Jones TGC")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
(cherry picked from commit 1ee1e63bdb0dea53c17338294bb53fa76136b178)
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819a616a
by Rhys Perry at 2025-10-01T11:30:48+02:00
aco: fix SGPR 8-bit nir_op_vec with mixed constant and non-constant
For example, vec2(non_const, const)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04e3d7ad9309 ("aco: improve nir_op_vec with constant operands")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13911
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37405>
(cherry picked from commit d6ed68212c78594e634777fb68c9a02e5407b7c9)
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c35e5c29
by Danylo Piliaiev at 2025-10-01T11:30:48+02:00
freedreno/decode: Fix preamble decoding
Fixes: 46ad5a01a89 ("freedreno: Rename CP_SET_CTXSWITCH_IB to CP_SET_AMBLE")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37458>
(cherry picked from commit 0908694f027342bfb2d505514e9ecf9c2b5d2e51)
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25fa8957
by Hans-Kristian Arntzen at 2025-10-01T11:30:48+02:00
radv/sqtt: Ensure that present fence gets signalled.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 88cbe32048a ("radv: add support for RGP queue events")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37438>
(cherry picked from commit 3bc81ee6f1f3d42e4cb12e0da165d2b099b64f0a)
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02e4dfb8
by Olivia Lee at 2025-10-01T11:30:48+02:00
pan/va: fix bi_is_imm_desc_handle early return
In the bi_emit_load_attr call site, we can use the imm_index value even
if the function returns false. The bifrost path handles this correctly.
Fixes: 652e1c2e139 ("pan/bi: Rework indices for attributes on Valhall")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37464>
(cherry picked from commit 275ebde06d51704790a7b7137a1b43fb1f6360e4)
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020046ad
by Mike Blumenkrantz at 2025-10-01T11:30:48+02:00
zink: flag gfx pipeline_changed if switching from a shader object draw
this otherwise might fail to do some updates
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37466>
(cherry picked from commit 6f3d71f790462d7882213f537b6756b25a85e9f5)
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ff77f895
by Timothy Arceri at 2025-10-01T11:30:48+02:00
nir: fix uniform cloning helper again
UBOs in different stages can have the same instance name for
different UBOs so here we make sure to also check that types match
before deciding we have a match.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13254
Fixes: b47b8d16d947 ("nir: expose reusable linking helpers for cloning uniform loads")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37428>
(cherry picked from commit 870ce2275447dcf49096df35f81d974ce8e1fa5c)
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f1d85aeb
by Timur Kristóf at 2025-10-01T11:30:48+02:00
spirv: Always mark FS layer and viewport index inpus as flat
The spec requires these to be decorated as FLAT,
but some apps forgot to set that,
eg. old DXVK before d12a8e09a855
Let's unconditionally decorate these FS inputs as FLAT
in spirv_to_nir, we can do that for free and prevent those
apps from crashing RADV.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33205>
(cherry picked from commit da184ddbe4eb1dfb83ff0b097b6b5c8f97ff111f)
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1efceff1
by Mike Blumenkrantz at 2025-10-01T11:30:49+02:00
tu: don't deref end info in tu_CmdEndRendering2EXT
this can be null
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37476>
(cherry picked from commit 4b30df44622efb8a6ea3f920e22d81990d1b76c4)
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62d8a3f3
by Mike Blumenkrantz at 2025-10-01T11:30:49+02:00
mesa: don't assert when finding a renderbuffer miplevel fails
this can also be caused by winsys and api being out of sync, e.g.,
if the window resize is lagging behind the framebuffer resize
in this case, just use level 0 and assume things will be okay
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37467>
(cherry picked from commit f9dd9bc30d3a6f1edce417ab42851f34385dd163)
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376cb802
by Mike Blumenkrantz at 2025-10-01T11:30:49+02:00
zink: fix u_blitting when clears are pending
previously this only checked to see if dst was bound, but that is not
the only condition in which clears may be flushed, and triggering a clear
flush while blitting will not set image layouts, which means that a renderpass
could be illegally triggered on an UNDEFINED image (even though it wouldn't be used)
instead, do a much more thorough check to determine whether clears can actually be
stored with the expectation that they will otherwise be flushed
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37467>
(cherry picked from commit d98cf09feb7a640bfe29e4237572f2ff5b7e4239)
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1d286d2e
by Qiang Yu at 2025-10-01T11:30:49+02:00
radeonsi: fix use aco/llvm debug options
They should be moved to shader options.
Fixes: 5c92fe45a1a ("radeonsi: support more than 64 options for AMD_DEBUG")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37433>
(cherry picked from commit 996c0af482c5b6e50c987ff9c3ab8bb700715d06)
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752cc326
by Lucas Fryzek at 2025-10-01T11:30:49+02:00
anv: Update viewport/scissor state when count changes
We need to ensure that HW viewport and scissor state is updated when
just the count is updated.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37487>
(cherry picked from commit 6e29e13e78d7f0b029bded25d0a78970b999903b)
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31c2259c
by Olivia Lee at 2025-10-01T11:30:49+02:00
panvk: fix FS driver set layout when LD_VAR_BUF is disabled
We can't use shader->info.stage here because it is only initialized in
pan_shader_compile, which is called after nir_lower_descriptors. This
causes us to miss the index adjustment to make room for the varying
attributes when LD_VAR_BUF is disabled.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: 7b949dd8c40 ("panvk: Use LD_VAR_BUF[_IMM] when possible")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37471>
(cherry picked from commit 729827878a018618734685480e2da2a3e728a967)
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f54df11b
by Ian Romanick at 2025-10-01T11:30:49+02:00
brw: Increase the size of some structure fields in combine_constants
In very large shaders, first_use_ip, last_use_ip, and even (register) nr
can overflow 16 bits. Increase the size of these fields.
used_in_single_block is moved earlier in the structure to promote better
packing.
Fixes: 2dad1e3abdb ("i965/fs: Add pass to combine immediates.")
Closes: #9489
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: @joostruis
Tested-by: @Snoucher
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37482>
(cherry picked from commit b7e1ac8309843b6cc005845177080cb91d604958)
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92f65930
by Ian Romanick at 2025-10-01T11:30:49+02:00
elk: Increase the size of some structure fields in combine_constants
In very large shaders, first_use_ip, last_use_ip, and even (register) nr
can overflow 16 bits. Increase the size of these fields. Some structure
components are rearranged to promote better packing.
Fixes: 2dad1e3abdb ("i965/fs: Add pass to combine immediates.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37482>
(cherry picked from commit 3e04990c683df622fcdf915adaa255057637543b)
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877fbf74
by Calder Young at 2025-10-01T11:30:49+02:00
anv: Fix tiling for AV1 IntraBC surface on Gfx125+
Fixes: 3c7a834e ("anv: Add support for AV1 video decoding on Gfx125 and Xe2")
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37352>
(cherry picked from commit a6b11b58d982f224bdc39271c50fd964264364b2)
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4bd2fe8b
by Mario Kleiner at 2025-10-01T11:30:49+02:00
asahi: Fix lseek failure error handling in agx_bo_import().
If bo->size = lseek(); would return a failure value of bo->size ==-1,
then current error handling would return while leaving the already
allocated and cached bo for the dmabuf fd in a half initialized "zombie"
state. On a successive call to agx_bo_import() for the same fd, the
assigned bo->size == -1 would mark the bo as "already initialized",
just bumping its reference count, and then returning a dysfunctional
bo to the caller, leasing to followup failures elsewhere.
Use goto error; instead, where "error:" handling will zero-out the bo,
marking it as effectively uninitialized, and hopefully causing proper
initialization on a successive call to agx_bo_import().
Fixes: df725d4f642a ("asahi: remove agx_bo::dev")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37538>
(cherry picked from commit 3c01205e32b14cfca36f8396d34150b152f46218)
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a555c018
by Mario Kleiner at 2025-10-01T11:30:49+02:00
asahi: Set PIPE_BIND_SCANOUT in agx_resource_from_handle().
Commit 534a04d557f3 optimized agx_resource_from_handle() to lazily
defer assignment of a kms-ro renderonly_scanout object to an imported
resource until its kms winsys handle is actually queried by a caller
via agx_resource_get_handle(), to avoid unnecessary import into the
DCP display controller. Only resources with bind flag PIPE_BIND_SCANOUT
will get a renderonly_scanout object assigned during such queries.
Problem: This prevents Mesa GBM's gbm_bo_import() function from properly
importing dmabufs for direct scanout use by some Wayland compositors,
e.g., GNOME mutter.
gbm_bo_import() of dmabuf fd's (GBM_BO_IMPORT_FD / GBM_BO_IMPORT_FD_MODIFIER),
even with GBM_BO_USE_SCANOUT flag, will not mark an imported bo with the
PIPE_BIND_SCANOUT bind flag before internally assigning its KMS winsys
handle via screen->resource_get_handle() -> agx_resource_get_handle(),
causing silent failure of that query. Therefore gbm_bo_import() seems
to return a successfully created gbm_bo with all proper properties,
but gbm_bo_get_handle() and gbm_bo_get_handle_for_plane() will return
invalid handles. These invalid handles cause drmAddFbXXX ioctl calls to
fail, and therefore failure of direct scanout of wl_buffers.
Setting PIPE_BIND_SCANOUT for a resource in agx_resource_from_handle()
may retain the optimization and makes gbm_bo_get_handle[_for_plane]()
work. This fixes direct scanout of fullscreen wl_surface / wl_buffers
under at least GNOME mutter 48.
Fixes: 534a04d557f3 ("asahi: Flip kmsro around to allocate on the GPU")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37538>
(cherry picked from commit fc44e708d71ea97f21aaa1e9274e4a89c032dd92)
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4533272f
by Mel Henning at 2025-10-01T11:30:49+02:00
nak: Don't copy-prop adds that flush to zero
Adding zero has the effect of flushing to zero when ftz is set.
This fixes a regression in
dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp32.input_args.reflect_denorm_flush_to_zero
An add.ftz changes one of its arguments to negative rather than positive
zero starting in 8d19ffef0a9 ("nir: Add more matches for `fmulz`") on
that test, which was then triggering copy-prop which brought this
issue to light.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13961
Fixes: 29bfdcd7 ("nak: Add an ftz bit to a bunch of float ops")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37537>
(cherry picked from commit ce1d0ae10842bf33dfaf0a82fd04048d7a95199c)
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23495cf4
by Faith Ekstrand at 2025-10-01T11:30:49+02:00
vulkan/queue: Move shared binary semaphores to temps
If a client creates a semaphore, exports it, and then re-imports it back
into the device, this can trick our semaphore reset logic. When this
happens, we end up with two different vk_sync structs that have the same
underlying payload so if one is used as the signal and one is used as
the wait of the same submit, we'll end up resetting it because we think
they're different, causing us to lose the signal.
We already have the ability to handle this for the threaded case by
moving the semaphore payload into a new vk_sync which we then destroy
after we're done submitting to the driver. Use this path for shared
semaphores in the immediate case so we can just wait and signal without
worrying about the reset.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13805
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37149>
(cherry picked from commit 0f7e0f79ad1754d64cef08da0a511c8447bb8d44)
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65c71922
by Karol Herbst at 2025-10-01T11:30:49+02:00
Revert "ci: Update CrosVM and Virglrenderer"
This reverts commit ab5605aab3241c87b3828abcda861efa58d20ae8.
We require 1.78 on 25.2 and we should CI against 1.78 on 25.2.
If something in CI requires a newer version, this should be handled
differently. If we require a newer rustc version because of a dependency
we should properly bump the rustc version requirement.
But please no random bumps like this because we don't want to cause random
build failures due to changes in rustc.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37198>
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b4cbb513
by Dave Airlie at 2025-10-01T11:30:49+02:00
gallivm: handle u8/u16 const loads properly on big-endian.
Turns out just putting the u32 in doesn't work on big endian, so
put the proper u8/u16 values in.
Got a report that since the loop limiter got removed, a gtk4 blur
shader was looping forever on s390x. Turns out it was using a 16-bit
loop variable (because why wouldn't you), and the loop counter was
just staying at 0 all the time.
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37593>
(cherry picked from commit e28cfb2bada2398a9ddcadd03fac060d5654a15e)
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cf43bd3d
by Tapani Pälli at 2025-10-01T11:30:50+02:00
blorp: add missing pipecontrol after 3DSTATE_WM_HZ_OP for Xe2+
Backport-to: 25.2
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37547>
(cherry picked from commit c8f47d7681a5e8a5e346215150e3e333ce4d5ef5)
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b6735876
by Hyunjun Ko at 2025-10-01T11:30:50+02:00
vulkan/video: fix misuse of CLAMP in h265 slice parsing.
Fixes: 79981063552 ("vulkan/video: Fix wrong parsing for H265 decoding")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37412>
(cherry picked from commit 84802cf32523eee2937ddd939e7a5ffad717ae8e)
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98265249
by Georg Lehmann at 2025-10-01T11:30:50+02:00
aco/lower_branches: update branch hints after changing jump targets
Fixes: 13ad3db43f9 ("aco/lower_branches: implement try_remove_simple_block() in lower_branches()")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37552>
(cherry picked from commit 8343e4546707f9839aa247e0cd664eb743fca4f7)
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e99bd7db
by José Roberto de Souza at 2025-10-01T11:30:50+02:00
intel/brw: Use ASR over SHR for SHADER_OPCODE_ISUB_SAT
src[1]/src0 is signed and Xe2+ SHR don't support operations over signed
data types so lets switch this over ASR that supports signed data
types.
Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37557>
(cherry picked from commit 141a225ca136e7a7e6368e5999c793428c363978)
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d134b44b
by Mel Henning at 2025-10-01T11:30:50+02:00
nak: Fix divergence test for redux availability
nak's divergence differs slightly from nir's divergence. Fix the test to
match what the backend will use, since we need to allocate a ureg.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13964
Fixes: 295373f29f ("nak: Implement nir_intrinsic_reduce with REDUX")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37585>
(cherry picked from commit 094804131ea57c250c1d54c776ea26ab7b2f127b)
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eddc5117
by Jordan Justen at 2025-10-01T11:30:50+02:00
anv: Use image view base-layer in can_fast_clear_color_att()
We currently only support fast clearing the first layer of an image.
Attachments use VkImageView which can specify a base-layer of the view
for an image attachment.
Fixes: 44351d67f8f ("anv: Change params of anv_can_fast_clear_color_view")
Ref: https://projects.blender.org/blender/blender/issues/141181
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37562>
(cherry picked from commit be61c12f3e61d1b6e3c76a46f3e8851d95e15a09)
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ac47f526
by Faith Ekstrand at 2025-10-01T11:30:50+02:00
spirv: Add support for OpBitcast in OpSpecConstantOp
This is required for OpenCL but not Vulkan. This fixes a bunch of
OpenCL CTS fails using the SPIR-V back-end in LLVM as opposed to
SPIRV-LLVM-Translator.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37555>
(cherry picked from commit 8ef811b02a022719dfff3fded07b6a2e6ec592f7)
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3482550e
by Timur Kristóf at 2025-10-01T11:30:50+02:00
ac/nir/ngg: Fix scalarized mesh primitive indices
Take the write_mask into account when storing primitive indices,
otherwise they will end up being stored in the wrong place.
Fixes: 8e24d3426d93 ("ac/nir/ngg: Refactor MS primitive indices for scalarized IO.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37610>
(cherry picked from commit d3579190d6176f2665364c79085ac4a4ed00f7d5)
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482d1c32
by Christoph Neuhauser at 2025-10-01T11:30:50+02:00
egl: Fix invalid device UUID returned by EGL_EXT_device_persistent_id
MR !36998 / commit 72f2565fc99ea80b7f7ddc4392ef2313edf96692 introduced
an issue where QueryDeviceInfo is not called in eglQueryDeviceBinaryEXT,
which causes the queried UUID to always be zero.
This commit fixes the issue by adding a call to QueryDeviceInfo.
Also, it refactors the inconsistent function names passed to _eglError.
Signed-off-by: Christoph Neuhauser <christoph.neuhauser@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37616>
(cherry picked from commit 5e5bc7a1c728693b97d45b13c3a5eabc6313e9db)
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0955a160
by Bas Nieuwenhuizen at 2025-10-01T11:30:50+02:00
device-select: Fix error check.
Fixes: 355b96413d6 ("egl/wayland: Move bind_wayland_display to legacy build option")
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13931
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37622>
(cherry picked from commit 00b8b571c60575c330d5a4fa8580ebb0eac82123)
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b6636130
by Ian Romanick at 2025-10-01T11:30:50+02:00
brw/nir: nir_intrinsic_load_reloc_const_intel may not be scalar [v3]
If the (NIR) destination is a register (i.e., not an SSA value), the
destination of the BRW instruction will not be is_scalar. This occurs in
some shaders in Final Fantasy XVI (and
finalfantasytype0_1.rdc.2826e29da3722a83.1.foz).
If the destination is not is_scalar, revert most of this code to the
state previous to f3593df877f. This means
- Allocate a SIMD1 register and UNDEF it.
- Emit a SIMD1 MOV_RELOC_IMM to that register.
- Emit an additional MOV to expand the SIMD1 result.
Closes: #12520
Fixes: f3593df877f ("brw/nir: Treat load_reloc_const_intel as convergent")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37384>
(cherry picked from commit 23bd356b425c885bf48e5349c0b7ee1f74b6ca4b)
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a0dc73e2
by Nanley Chery at 2025-10-01T11:30:50+02:00
anv: Disable CCS if image bound to wrong heap on Xe2+
Avoids HIZ + CCS flushes and helps debug.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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483cb339
by Nanley Chery at 2025-10-01T11:30:50+02:00
anv: Disable fast-clears on linear surfaces
Bspec 57340 does not have a fast-clear rectangle for linear surfaces.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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3885d175
by Nanley Chery at 2025-10-01T11:30:50+02:00
iris: Disable fast-clears on linear surfaces
Bspec 57340 does not have a fast-clear rectangle for linear surfaces.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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d75c5803
by Nanley Chery at 2025-10-01T11:30:50+02:00
iris: Add PIPE_BIND_SCANOUT when exporting textures
I don't see anything preventing images from being used for display via
EGL_MESA_image_dma_buf_export. When CCS is enabled on linear surfaces in
a future patch, this will prevent exported DRM_FORMAT_MOD_LINEAR images
from being compressed.
On BMG, this fixes the mesa demo, dmabufshare:
https://gitlab.freedesktop.org/mesa/demos/-/blob/main/src/egl/opengl/dmabufshare.c
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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8802a63e
by Nanley Chery at 2025-10-01T11:30:50+02:00
iris: Fix image reallocation for sharing
On XeKMD, BOs need to be created with a vm_id of zero in order to get
prime handles. That only occurs if the image was created with
PIPE_BIND_SHARED/BO_ALLOC_SHARED. Ensure that shareable images have this
flag in iris_flush_resource().
Fixes the dmabufshare demo on BMG with INTEL_DEBUG=noccs and mesa hacked
to disable suballocation.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13511
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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f005cd7d
by Nanley Chery at 2025-10-01T11:30:50+02:00
intel/isl: Only set CMF on renderable views on Xe2+
The compression format is only used during rendering.
This prevents drivers from hitting an unreachable when we start enabling
CCS on linear surfaces which may have non-renderable and non-pow2 formats.
For now, continue to use the surface format instead of the view format
to look up the CMF. This strategy should return the optimal CMF for
compressed surfaces that undergo redescription during copies.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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cb6b3768
by Nanley Chery at 2025-10-01T11:30:51+02:00
intel: Enable CCS_E on linear surfaces on Xe2+
Allow CCS for non-display linear surfaces in isl_surf_supports_ccs().
We're going to rely more on the helper to determine CCS-enabling for Xe2
on iris.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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03e147b1
by Nanley Chery at 2025-10-01T11:30:51+02:00
iris: Drop iris_resource_image_is_pat_compressible
The functionality is provided by isl_surf_supports_ccs().
Also, move the protected content restriction to
iris_resource_configure_aux(). I'm not aware of any reason protected
content wouldn't support CCS. However, to keep this series simple,
enabling that combination is left for another time.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
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7d60cd0f
by Jianxun Zhang at 2025-10-01T11:30:51+02:00
iris: Disable compression on sharing without modifier
For an image created either without a modifier to share or as the
destination image to get rid of compression by re-allocation, it
should have compression disabled.
Close: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13729
(Fix firefox misrendering when gfx.wayland.hdr option is true)
Backport-to: 25.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
(cherry picked from commit 5aa4dc7f77ca9f93d5fb3d2f98bf13dee76e2c84)
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aae59f1f
by Ella Stanforth at 2025-10-01T11:30:51+02:00
v3d/compiler: Lower load_output after logic operations
Fixes: 42154029fcd ("v3d/compiler: Implement software blend lowering")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35820>
(cherry picked from commit 9263e1838bb824fd2d9d30a3225bfd062eb91a8a)
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f0d08a5c
by Kenneth Graunke at 2025-10-01T11:30:51+02:00
nir: Add load_simd_width_intel to divergence analysis
For some reason we missed adding this. This prevents some asserts
from triggering when I call divergence analysis at certain points
in an upcoming patch.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36750>
(cherry picked from commit 25cb6dfbf7c859152ea8aebd0f4b778e27a863f4)
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84739d85
by Kenneth Graunke at 2025-10-01T11:30:51+02:00
intel/nir: Make ffma peephole optimization preserve fp_fast_math flags
float_controls2 may have marked these as needing to preserve NaN or
other values. If so, our newly contracted ffma needs to as well.
Fixes dEQP-VK.spirv_assembly.instruction.compute.float_controls2.*.input_args.mat_det_testedWithout_NotNan*
when nir_opt_algebraic is run after this pass.
Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36750>
(cherry picked from commit 1b0808adf3d95c64081e393f021f624f72e86d88)
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7614fa79
by Eric Engestrom at 2025-10-01T12:32:50+02:00
docs: add release notes for 25.2.4
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ab462ae6
by Eric Engestrom at 2025-10-01T12:32:50+02:00
VERSION: bump for 25.2.4