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[Git][xorg-team/lib/mesa][upstream-unstable] 89 commits: docs: add sha sum for 25.0.2



Title: GitLab

Timo Aaltonen pushed to branch upstream-unstable at X Strike Force / lib / mesa

Commits:

  • a801a4aa
    by Eric Engestrom at 2025-03-20T15:00:31+01:00
    docs: add sha sum for 25.0.2
    
  • 43d5f3ca
    by Eric Engestrom at 2025-03-29T20:45:01+01:00
    .pick_status.json: Update to 85983e060ccca163ff5c4aad51c7082b7ae8c4a0
    
  • bcaae899
    by Eric Engestrom at 2025-03-29T20:45:01+01:00
    ci/piglit: drop usage of s3cp for a simple download
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120>
    (cherry picked from commit 213550d2e03c531751068ca8b20b6122e8db17de)
    
  • 2ed27e06
    by Eric Engestrom at 2025-03-29T20:45:02+01:00
    ci: always abort if the curl download fails
    
    Reported-by: @Valentine
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120>
    (cherry picked from commit d4258477937cd497f73b87adb386c9a9f05e9345)
    
  • 666e00cf
    by Eric Engestrom at 2025-03-29T20:45:02+01:00
    ci: replace broken s3cp command with a simple curl call
    
    The current `s3cp` implementation does not work anymore after the
    migration, and instead of fixing it and propagating the fix down to us,
    it's simpler to directly use `curl`.
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120>
    (cherry picked from commit 7178425ccf1016e31ce3ba59d1f606d1afd8c51a)
    
  • 58e28017
    by Valentine Burley at 2025-03-29T20:45:02+01:00
    ci: Add missing kvm runner tags
    
    A recent change now requires the kvm runner tag to be explicitly listed
    for jobs that need to run on runners with KVM capability.
    This ensures the jobs are scheduled on compatible runners.
    
    Cc: mesa-stable
    
    Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120>
    (cherry picked from commit a36379d97390b5275a746214b1ac46236d3a4daf)
    
  • 6b31b441
    by Eric Engestrom at 2025-03-29T20:45:02+01:00
    ci: run shader-db & zink-lvp on kvm runners
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34120>
    (cherry picked from commit 6cd7b65ac0e0464768ffd30190a644c399b72edf)
    
  • a4231424
    by Eric Engestrom at 2025-03-29T20:45:02+01:00
    pick-ui: fix parsing of multiple `backport-to:` lines
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34117>
    (cherry picked from commit e7b2eda39db915c8516ac13a3ac9765e73b15455)
    
  • caf97cb6
    by Eric Engestrom at 2025-03-29T20:45:02+01:00
    .pick_status.json: Update to e3433489f81a75c278ff70cc5700cd028447bf76
    
  • 0c6e6477
    by Daniel Stone at 2025-03-29T20:45:02+01:00
    ci: Re-enable trace jobs with updated Piglit
    
    mesa/piglit!996 fixed up Piglit to allow us to do trace downloads again,
    so we can now bring these jobs back. The fdno trace jobs hosted at
    Google are still disabled whilst we try to fix their nginx.
    
    Signed-off-by: Daniel Stone <daniels@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34245>
    (cherry picked from commit f6f085f50a293d18e41758bae7972dae41e9c6ff)
    
  • 69d6923c
    by Eric Engestrom at 2025-04-02T11:04:10+02:00
    [25.0 only] update ci expectations
    
    These changes happened with no mesa code change, only infrastructure
    changes, which is really weird, but to be able to move on, let's simply
    document the "new normal".
    
  • e159e000
    by Daniel Schürmann at 2025-04-02T11:04:10+02:00
    aco: don't assume that demote doesn't cause an empty exec mask
    
    Totals from 188 (0.24% of 79377) affected shaders: (Navi31)
    Instrs: 209239 -> 209473 (+0.11%); split: -0.01%, +0.12%
    CodeSize: 1101124 -> 1101744 (+0.06%); split: -0.02%, +0.07%
    Latency: 1672182 -> 1672748 (+0.03%); split: -0.11%, +0.14%
    InvThroughput: 237276 -> 237546 (+0.11%); split: -0.00%, +0.12%
    SClause: 5694 -> 5690 (-0.07%); split: -0.28%, +0.21%
    Copies: 21685 -> 21682 (-0.01%); split: -0.12%, +0.10%
    Branches: 5740 -> 5863 (+2.14%)
    PreSGPRs: 7004 -> 7034 (+0.43%)
    VALU: 123595 -> 123641 (+0.04%); split: -0.00%, +0.04%
    SALU: 28418 -> 28411 (-0.02%); split: -0.09%, +0.06%
    
    Fixes: f35e229faedb5e19da49846eed119d82228c5d5a ('aco: skip code if exec is empty')
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33619>
    (cherry picked from commit 69dcd5be3a94d8c301ebf54f7e043f419841a231)
    
  • b9e649b3
    by Eric Engestrom at 2025-04-02T11:04:10+02:00
    .pick_status.json: Update to b60d816d6ee35cc1bfa2d2f6aed59104a09ec11d
    
  • 5db78fe0
    by Jordan Justen at 2025-04-02T11:04:10+02:00
    intel/dev: Add BMG PCI IDs (0xe210, 0xe215, 0xe216)
    
    Backport-to: 24.3
    Backport-to: 25.0
    Ref: https://patchwork.freedesktop.org/patch/msgid/20250128162015.3288675-1-shekhar.chauhan@intel.com
    Ref: bspec 68090
    Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33335>
    (cherry picked from commit 0e648a238e23199969e57e1d9336755b5c74d87f)
    
  • e3003829
    by Tomeu Vizoso at 2025-04-02T11:04:10+02:00
    egl/surfaceless: Only choose drivers that expose the graphics capability
    
    This is to prevent applications to try to render to devices that have no
    3D hardware (eg. NPUs).
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30096>
    (cherry picked from commit cfad6fb037f74753f17bcac0067330254c45dfaa)
    
  • b075d80f
    by Lucas Stach at 2025-04-02T11:04:10+02:00
    kmsro: look for graphics capable screen as renderonly device
    
    Exposing a rendernode from a supported driver is not a sufficient
    matching criteria to qualify as the render part of a renderonly
    device, as the rendernode might only expose compute or 2D accel
    capabilities.
    
    Look for a screen that actually supports gallium graphics operations
    to qualify as a renderonly screen.
    
    v2 (Tomeu): Have pipe-loader return a list of FDs for kmsro to choose
                based on capabilities.
    
    Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30096>
    (cherry picked from commit 7e76c676322d7772849ccc29b186062fb724ed7d)
    
  • c0bc957c
    by Tomeu Vizoso at 2025-04-02T11:04:10+02:00
    kopper: Explicitly choose zink
    
    If we pass zink=false to pipe_loader_drm_probe_fd, it could happen that
    a Gallium driver that had been already discarded because of not
    supporting the graphics CAP will be chosen.
    
    To avoid that, explicitly ask pipe_loader_drm_probe_fd to choose the
    zink Gallium driver.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30096>
    (cherry picked from commit 854bc2ee05f90e426f318352682144050e402d4b)
    
  • 2684f371
    by Eric R. Smith at 2025-04-02T11:04:10+02:00
    panfrost: consider xfb shader when calculating thread local storage size
    
    Register spilling can cause us to require thread local storage (tls).
    However, we were not adjusting the tls stack size space to account for
    the tls needed for the extra xfb shader when transform feedback is
    needed. We noticed this when testing register allocation in the
    OpenGL CTS (for testing we had forced spilling where none happened
    before).
    
    Cc: mesa-stable
    Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33935>
    (cherry picked from commit 2ee3bef252237d8c94b873e3378e0bedd69cf59a)
    
  • 59c34850
    by Yiwei Zhang at 2025-04-02T11:04:10+02:00
    docs: demote VK_KHR_shader_relaxed_extended_instruction
    
    It's not part of core 1.3.
    
    Fixes: 8b272c8d8c4 ("docs: update feature matrix for VK_KHR_shader_relaxed_extended_instruction")
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34104>
    (cherry picked from commit d2a7c1c45247c5efde09b0004a1455a42baff94c)
    
  • f8f43523
    by Yiwei Zhang at 2025-04-02T11:04:10+02:00
    venus: fix unexpected ring alive status expire upon owner thread switch
    
    If the last owner thread has just unset the alive status and released
    the watchdog, the new owner thread could have acquired to abort
    unexpectedly if the ownership transfer occurs right before the next
    owner's warn order. So we must set watchdog alive for new owner so that
    it can properly check ring alive status in the next warn order.
    
    Cc: mesa-stable
    Acked-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34135>
    (cherry picked from commit 8b2703fe0838419f081b5fc0c9dc66ab91c4efff)
    
  • 54d82949
    by Yiwei Zhang at 2025-04-02T11:04:10+02:00
    venus: fix ahb usage caching
    
    Test: dEQP-VK.api.external.memory.android_hardware_buffer.*
    
    Fixes: fde5cebec53 ("venus: fix image format cache miss with AHB usage query")
    Acked-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34135>
    (cherry picked from commit ea6dc035d893b973c5dc7dd097e26e1d5ddf13e7)
    
  • c432dfe7
    by Yiwei Zhang at 2025-04-02T11:04:10+02:00
    venus: fix maint4 multi-planar memory requirements
    
    Fixes: ce1bbd241eb ("venus: extend image cache to vkGetDeviceImageMemoryRequirements")
    Acked-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34135>
    (cherry picked from commit adcb967c5c2306b01f3ddee04eb41210a5d6f03e)
    
  • 0a6dcd91
    by Yiwei Zhang at 2025-04-02T11:04:10+02:00
    panvk/csf: rework cache flush reduction
    
    Per Vulkan spec 7.9. Host Write Ordering Guarantees, queue submission
    commands automatically perform a domain operation from host to device
    for all writes performed before the command executes. That is to say,
    host updates to the mappings can occur after the end of the command
    recording and must be flushed implicitly at submission boundary.
    
    Before this change, necessary cache flushes could be missed once the
    app starts reusing pre-recorded command buffers. e.g. a simple buffer
    copy cmd while the app only updates the source buffer mapping in
    different submissions. This changes backs out most of the current
    version of cache flush reduction while still assigning LATEST_FLUSH_ID
    to at least the final batch itself. This aligns with panfrost_batch
    submit behavior on the gallium side.
    
    Test: dEQP-VK.synchronization*.timeline_semaphore.* pass w/o flakiness
          via venus-on-panvk
    
    Fixes: 28e4d224972 ("panvk/csf: Pass a non-zero flush-id to benefit from cache flush reduction")
    Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34093>
    (cherry picked from commit 98a5acf352451e10046e9c5be3a2f0f1430ea6e9)
    
  • 66b5ae35
    by Yiwei Zhang at 2025-04-02T11:04:10+02:00
    panvk: fix memory requirement query for aliased disjoint image
    
    The spec allows to create aliased disjoint image for a specific plane of
    a multi-planar image, and the format can be R8. When querying memory
    requirement of such image, VkImagePlaneMemoryRequirementsInfo is not
    required to be chained although it has the disjoint bit.
    
    This change fixes to look for aspect info from plane memory info only
    when that's chained. The implementation can be passive here as the spec
    VU has sufficient guarantees for the validity around. See below VU for
    details:
    - VUID-VkImageMemoryRequirementsInfo2-image-01589
    - VUID-VkImageMemoryRequirementsInfo2-image-01590
    - VUID-VkImageMemoryRequirementsInfo2-image-02279
    - VUID-VkImageMemoryRequirementsInfo2-image-02280
    
    Meanwhile, the existing disjoint check for size info is kept as is for
    the special handling of VK_FORMAT_D32_SFLOAT_S8_UINT.
    
    Test: dEQP-VK.ycbcr.plane_view.memory_alias.* pass with venus-on-panvk
    
    Fixes: 412c2863315 ("panvk: Enable multiplane images and image views")
    Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34134>
    (cherry picked from commit 5dcb9f918ddc6517bb1face005ad4d0f0aed17cb)
    
  • 756b10a8
    by Caio Oliveira at 2025-04-02T11:04:10+02:00
    brw: Fix decoding of 3-src destination stride in EU validation
    
    Fixes: f1036da3454 ("intel/brw: Add vstride/width/hstride to brw_hw_decoded_inst")
    Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
    Reviewed-by: Rohan Garg <rohan.garg@intel.com>
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33664>
    (cherry picked from commit 676b874ca9763a7a72b008932434423c213bc463)
    
  • ce22e438
    by Timothy Arceri at 2025-04-02T11:04:10+02:00
    mesa: fix reuse of deleted buffer object
    
    Deleting a buffer object will only cause it to be unbound from the
    current context. To avoid reusing something that it still bound in
    another context we need to check the DeletePending flag first.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12810
    Fixes: 842c91300fd0 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 0f0834275df223a5eb72289148e693043597e455)
    
  • 0c5a31f5
    by Timothy Arceri at 2025-04-02T11:04:10+02:00
    mesa: fix reuse of deleted texture object
    
    Deleting a texture object will only cause it to be unbound from the
    current context. To avoid reusing something that it still bound in
    another context we need to check the DeletePending flag first.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c91300fd0 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12710
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12722
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12830
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 9b85142e40468196dcf9d6d4260a6cef86d4243f)
    
  • d44e9736
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    mesa: fix potential race condition in with TexObjects
    
    The calls look up a texture object and create it if it doesn't
    already exist. However they weren't locking the hash between looking
    up the name and adding it to the hash so it could be possible
    another thread also generated the same name.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c9130 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 95e87f6a6ab85fea054c5f5d69bfc77938adc0f5)
    
  • 4a158b97
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    mesa: fix reuse of deleted sampler object
    
    Deleting a sampler object will only cause it to be unbound from the
    current context. To avoid reusing something that it still bound in
    another context we need to check the DeletePending flag first.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c9130 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 9bb696588db0dd568599cbebb43c3eac788f863e)
    
  • 835a3553
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    mesa: fix potential race conditions in with FrameBuffers
    
    The calls look up a framebuffer and create it if it doesn't
    already exist. However they weren't locking the hash between looking
    up the name and adding it to the hash so it could be possible
    another thread also generated the same name.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c91300fd0 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit c4ee84f3b631d32497d98507a0b043b2b634de8b)
    
  • f150c501
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    mesa: fix potential race condition in with RenderBuffers
    
    The calls look up a renderbuffer and create it if it doesn't
    already exist. However they weren't locking the hash between looking
    up the name and adding it to the hash so it could be possible
    another thread also generated the same name.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c91300fd0 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 0e61d31e9d9072482db64973d8a9154a7f4e6e45)
    
  • 04df661b
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    mesa: fix potential race condition in with ATIShaders
    
    The call looks up an ATIShader and creates it if it doesn't
    already exist. However we weren't locking the hash between looking
    up the name and adding it to the hash so it could be possible
    another thread also generated the same name.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c91300fd0 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 4c1e4d7b496fbe7a2e196b167e7aba9a5bc9d265)
    
  • 20e09c30
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    mesa: fix potential race condition in with Programs
    
    The call looks up a Program and creates it if it doesn't
    already exist. However we weren't locking the hash between looking
    up the name and adding it to the hash so it could be possible
    another thread also generated the same name.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
    Fixes: 842c91300fd0 ("mesa: enable GL name reuse by default for all drivers except virgl")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
    (cherry picked from commit 786b8b2d3490f315f5f779d55264d90052eb470d)
    
  • de5de2ec
    by Timothy Arceri at 2025-04-02T11:04:11+02:00
    nir: fix uniform cloning helper
    
    glsl allows for ubos to have the same name but different bindings.
    
    Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
    Fixes: b47b8d16d947 ("nir: expose reusable linking helpers for cloning uniform loads")
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12852
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34138>
    (cherry picked from commit 2b2132d2acd1fc312de41813888b802aeda3a00a)
    
  • cabc8c60
    by Job Noorman at 2025-04-02T11:04:11+02:00
    ir3/legalize: take wrmask into account for delay updates
    
    When updating delays, we'd update all dst regs based on reg_elems.
    However, when wrmask has gaps, this would update delays for regs that
    aren't actually written. Fix this by skipping regs for which the
    corresponding wrmask bit is zero.
    
    Note that this wasn't just a performance issue but could result in
    illegal code because the delay is reset to zero for tex/sfu
    instructions. For example, the following (post-legalization) code was
    observed in the wild:
    
    (rpt1)add.f r1.w, (r)r2.w, (r)c3.z
    sam.base0 (f32)(w)r2.x, r3.y, s#0, t#1
    rcp r2.x, r2.x
    
    Here, the add would result in a required delay for r2.x which would then
    be cleared by the sam (even though it doesn't write to it), resulting in
    insufficient delay before the rcp.
    
    Signed-off-by: Job Noorman <jnoorman@igalia.com>
    Fixes: 61b2bd861f9 ("ir3: Rewrite nop insertion")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34107>
    (cherry picked from commit 84dbd34332fe63169bb48ff7741032d4857c43b5)
    
  • 7e55a046
    by Samuel Pitoiset at 2025-04-02T11:04:11+02:00
    radv: fix creating pipeline binary from the traversal shader
    
    rt_stage_info is NULL.
    
    Fixes: 88026124585 ("radv: advertise VK_KHR_pipeline_binary")
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34141>
    (cherry picked from commit 29b3d9f0f4311d876f7a9ae48f6906ee51dffeca)
    
  • c89250cd
    by Lionel Landwerlin at 2025-04-02T11:04:11+02:00
    anv: fix end of pipe timestamp query writes
    
    Currently trying to use PIPE_CONTROL on blitter/video engines.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Cc: mesa-stable
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12833
    Acked-by: Hyunjun Ko <zzoon@igalia.com>
    Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34095>
    (cherry picked from commit 6b6a4cb1e2d705889644e68c3ffe7d7f8f4256cb)
    
  • fad1d950
    by Lionel Landwerlin at 2025-04-02T11:04:11+02:00
    anv: disable replication when we don't have both VS/FS stages
    
    Enabling this with shaders compiled separately through pipeline
    libraries fails because we currently only enable it for VS and the
    associated FS stage ends up with a non compatible VUE map.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Cc: mesa-stable
    Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34173>
    (cherry picked from commit 25a695552a96f53fbd224bc2d0630c1658fe7d9e)
    
  • b3991dd8
    by Rhys Perry at 2025-04-02T11:04:11+02:00
    aco/ra: fix free register counting when moving variables
    
    info.bounds might be smaller than the bounds available for the moved
    variables.
    
    Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
    Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
    Fixes: 626aa7b64817 ("aco: workaround GFX9 hardware bug for D16 image instructions")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34158>
    (cherry picked from commit 80fef30531358000dcc9bf0a4f34410dd45f304f)
    
  • 7f32247d
    by Samuel Pitoiset at 2025-04-02T11:04:11+02:00
    radv: fix bpe for the stencil aspect of depth/stencil copies on transfer queue
    
    Using the bpe of depth+stencil when copying the stencil aspect only
    doesn't work.
    
    Cc: mesa-stable
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34143>
    (cherry picked from commit 7b15e85b956f26e48cffba513ea210b92adcc612)
    
  • 6ad9455f
    by Samuel Pitoiset at 2025-04-02T11:04:11+02:00
    radv: fix compresed depth/stencil copies on transfer queue
    
    HTILE is always pipe aligned.
    
    Cc: mesa-stable
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34143>
    (cherry picked from commit 114fbdc5349744fb68952296c838246599a95cac)
    
  • 167bcee3
    by Hyunjun Ko at 2025-04-02T11:04:11+02:00
    vulkan/video: Do byte-alignment when building a h264 slice header
    
    Fixes: ff8de6190 ("vulkan/video: adds a bitstream writer of h264 slice header")
    Closes: mesa/mesa#12835
    
    Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
    Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34094>
    (cherry picked from commit c22a635938c4df93bde6d0b6d4726f4a99c7dbd8)
    
  • 88c7326a
    by Samuel Pitoiset at 2025-04-02T11:04:11+02:00
    radv/meta: fix color<->depth/stencil image copies
    
    The color format needs to be compatible with depth or stencil. Also
    the depth/stencil format was incorrect when it's the source.
    
    Fixes dEQP-VK.api.ds_color_copy.*
    and VKD3D_TEST_FILTER=test_copy_texture.
    
    Fixes: d4ff011b12d ("radv: advertise VK_KHR_maintenance8")
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34142>
    (cherry picked from commit 2c3b9312ccec1df7a8f71033a402ccb48958d193)
    
  • 9acee7d4
    by Paulo Zanoni at 2025-04-02T11:04:11+02:00
    drirc/anv: DiggingGame.exe needs force_vk_vendor=-1
    
    Otherwise, it fails with a message:
    
      "Assertion failed: IsValidIndex(Index)
       [File:D:\\build\\++UE5\\Sync\\Engine\\Source\\Runtime\\Core\\Public\\Containers\\UnrealString.h]
       [Line: 218] \nString index out of bounds: Index 0 from a string with
       a length of 0"
    
    Thanks to the ProtonDB community for having figured this out and
    documented it for us.
    
    Cc: mesa-stable
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12695
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34103>
    (cherry picked from commit e72ad49622f971c18f71c6c6a4ae4be449c218bc)
    
  • 5ecc1fb1
    by Lionel Landwerlin at 2025-04-02T11:04:11+02:00
    brw: always write the VUE header
    
    In 35df3925ca ("brw: ensure VUE header writes in HS/DS/GS stages") I
    misread the PRMs and thought that the VF would initialize the header.
    
    What actually happens is that the VF does not write valid values in
    there and the PRMs explicitly say that the VS shader should overwrite
    whatever is in there.
    
    We could avoid writing the header in some cases when no HW is going to
    read back the header. For example with rendering disables through
    3DSTATE_STREAMOUT::RenderingDisable. But those cases are dynamic and
    the compiler is not able to tell. So just always write the header.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: 35df3925ca ("brw: ensure VUE header writes in HS/DS/GS stages")
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12880
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34211>
    (cherry picked from commit 4db4bd1d044c37fb5bb8a64075a696a52f3d4465)
    
  • ba58320a
    by Lionel Landwerlin at 2025-04-02T11:04:12+02:00
    anv: limit implict write with drirc
    
    9f32e1a489 meant to amend 1e80a426c2.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: 9f32e1a489 ("anv/drirc: Add option to control implicit sync on external BOs")
    Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
    Reviewed-by: Matt Turner <mattst88@gmail.com>
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12629
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33587>
    (cherry picked from commit a88c9ea192c3588b99f8d35a292d84d12779d100)
    
  • ed757785
    by irql-notlessorequal at 2025-04-02T11:04:12+02:00
    hasvk: Fix non-functioning version override.
    
    https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27717 accidentally removed the instance check for the drirc option "hasvk_report_vk_1_3_version", rendering it useless.
    
    Re-add the check and expose Vulkan 1.3 if the user asks.
    
    Fixes: 2d575034f23 ("hasvk: switch to use runtime physical device properties infrastructure")
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34232>
    (cherry picked from commit c0c562cf6e590764e7edb1b82f2604cf79d433a5)
    
  • 1fa4455b
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nak: Insert the annotation in the right spot in assign_regs
    
    Fixes: efc4ac0d27ee ("nak/sm50: sprinkle OpAnnotate in optimization passes")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34201>
    (cherry picked from commit 98677294b9aea472d7e73d3a00261440a063307c)
    
  • 829c728e
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nak: Always copy sources when handling vec/pack/mov ops
    
    It's possible that the source is uniform but the destination is not.  In
    this case, we need to insert a copy or else we might accidentally
    propagate a uniform into some place we don't expect it.
    
    This fixes a bunch of fp64 KHR-Single-GL46.subgroups.arithmetic.* tests.
    
    Fixes: d09d3f52468a ("nak/from_nir: Emit uniform instructions when !divergent")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34201>
    (cherry picked from commit 1d1d79bbaa385f180acddbe69fb8190d69873d20)
    
  • 4aad059d
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nak: Fix a SM check for OpPCnt
    
    This doens't really fix anything as we don't have any nir_loops on
    Volta+ but the code was wrong so we should fix it.
    
    Fixes: 9bbc6920640b ("nak/nir: Rework CRS handling")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34201>
    (cherry picked from commit af9d65e8b8a6522702770b380e3e3b333587f170)
    
  • 558a7d92
    by Robert Mader at 2025-04-02T11:04:12+02:00
    llvmpipe: Take offset into account when importing dmabufs
    
    Which is necessary for many common YCbCr formats.
    
    Fixes: d74ea2c117f (llvmpipe: Implement dmabuf handling)
    Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Signed-off-by: Robert Mader <robert.mader@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34240>
    (cherry picked from commit 05e7ac6551d53ce848360941acfb9e74b4253a79)
    
  • c84a792c
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nvk: Free owned_gart_mem correctly
    
    Fixes: fbe171638ebb ("nvk: add gart forced cmd pool side buffer.")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
    (cherry picked from commit 90b2137ac50289eb18d4ba9eab056d31a48be88a)
    
  • c0de23e9
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nvk: Fix a Volta check
    
    Fixes: e162c2e78e86 ("nvk: Use VM_BIND for contiguous heaps instead of copying")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
    (cherry picked from commit 79294fb95aa6945e810e3b34ec28e14a601e8c0c)
    
  • 3e475be1
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nouveau/mme/fermi: Don't allow STATE and EMIT on the same op
    
    Fixes: 162269f04981 ("nouveau/mme: Add Fermi builder")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
    (cherry picked from commit 3354c24169bf2b5616108e1f466148a1e046eef6)
    
  • f2fa2ea4
    by Faith Ekstrand at 2025-04-02T11:04:12+02:00
    nvk: Use the right sample mask for 8x/4pass on Maxwell A
    
    Fixes: 48898c47bf37 ("nvk: Rework setup of sample masks")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
    (cherry picked from commit cbf87e82e8d70094984d02664c23b32739ef1229)
    
  • 40babe1e
    by Connor Abbott at 2025-04-02T11:04:12+02:00
    tu: Fix GMEM offset for multisample layered separate stencil
    
    Fixes a bug uncovered by CTS when enabling GMEM with layered rendering.
    
    Fixes: def56b531c8 ("tu: Support GMEM with layered rendering and multiview")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34082>
    (cherry picked from commit 6cadc1baea75136d720fc82b72f04eb6b3786d1e)
    
  • 0df2cf3a
    by Connor Abbott at 2025-04-02T11:04:12+02:00
    tu: Fix size of frag_size_ir3 and frag_offset_ir3 driver params
    
    They are an array, so we have to reserve extra space for extra views.
    This bug was being masked by the bug fixed in the next commit.
    
    Fixes: 76e417ca593 ("turnip,ir3/a750: Implement consts loading via preamble")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33991>
    (cherry picked from commit 122f2c422a5bba76c16b85502e669da04afd5463)
    
  • e9b6cf70
    by Connor Abbott at 2025-04-02T11:04:12+02:00
    tu: Fix reported FDM fragment size with multiview
    
    We were never setting has_multiview. It's not actually necessary anyway,
    since we can just do the optimization we were trying to do whenever
    num_views is 1 instead.
    
    This doesn't affect the actual fragment size, which was already correct,
    only gl_FragSizeEXT.
    
    Fixes: 6f2be52487b ("tu, ir3: Handle FDM shader builtins")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33991>
    (cherry picked from commit 8864ee7b0f430c909435f30336301fe919be631f)
    
  • e09a2e80
    by David Rosca at 2025-04-02T11:04:12+02:00
    radeonsi/vce: Support old VCE firmware
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12866
    Fixes: 104f9c66545 ("radeonsi/vce: Remove support for FW 50 and older")
    Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34152>
    (cherry picked from commit a2b4617c00ea5c7dd86b95d2294e02ab843c898b)
    
  • 09da8e12
    by Robert Mader at 2025-04-02T11:04:12+02:00
    llvmpipe: Free dummy_dmabuf on shutdown
    
    In order to stop ASAN from complaining.
    
    Fixes: d21aa86b547 ("llvmpipe: Implement EGL_ANDROID_native_fence_sync")
    Signed-off-by: Robert Mader <robert.mader@collabora.com>
    Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34258>
    (cherry picked from commit 2034c901ccdcc1bb02d150911615ba09e242ca33)
    
  • d56be9ad
    by David Rosca at 2025-04-02T11:04:12+02:00
    gallium/vl: Fix rotation with scaling for compute shaders
    
    Cc: mesa-stable
    Acked-by: Ruijing Dong <ruijing.dong@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34140>
    (cherry picked from commit c8a2f0b2485976dfe134869e089d314d14d09293)
    
  • b6f9ccf0
    by David Rosca at 2025-04-02T11:04:12+02:00
    gallium/vl: Fix mirror with rotation for compute shaders
    
    The mirror needs to be reversed because the rotation is applied
    before the mirroring.
    
    VAAPI docs:
      Mirroring of an image can be performed either along the
      horizontal or vertical axis. It is assumed that the rotation
      operation is always performed before the mirroring operation.
    
    Cc: mesa-stable
    Acked-by: Ruijing Dong <ruijing.dong@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34140>
    (cherry picked from commit 962c33cbcacdee9e4d45adcad81b8090fffc8a22)
    
  • e790a1ca
    by David Rosca at 2025-04-02T11:04:12+02:00
    frontends/va: Don't ignore rotation and mirror for conversions to RGB
    
    Cc: mesa-stable
    Acked-by: Ruijing Dong <ruijing.dong@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34140>
    (cherry picked from commit 51292976feb2d737dc97a46685ce7223dd64f51e)
    
  • 0c3b74d5
    by Natalie Vock at 2025-04-02T11:04:13+02:00
    radv/rt: Flush CP writes from the common BVH framework with INV_L2 on GFX12
    
    a1b05991 ("radv/rt: Flush L2 after writing internal node offset on GFX12")
    did this for radv-internal CP writes - we also need to do this for PLOC
    sync data initialization which is done in the common framework.
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34178>
    (cherry picked from commit c1e1d86bd1c4d00b5ea797377a6fb96c305b6093)
    
  • 9fb56e27
    by Natalie Vock at 2025-04-02T11:04:13+02:00
    vulkan/bvh: Move first PLOC task_count fetch inside PHASE
    
    Otherwise, the memory fetch is not protected by the global sync and
    memory barriers and there is a chance to read a stale (or just wrong)
    task count.
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34178>
    (cherry picked from commit 8b0271050a4f42f35cfdbc50a0d88e47ba9290e1)
    
  • 79f960cb
    by Faith Ekstrand at 2025-04-02T11:04:13+02:00
    vulkan/wsi: Signal buffer memory object when blitting
    
    When we're using the PRIME path and using vkCmdCopyImageToBuffer to copy
    to a linear image, the buffer memory is what's shared with the window
    system.  For legacy drivers that depend on memory signaling via
    wsi_memory_signal_submit_info, we need to tell the driver to signal the
    buffer memory, not the image memory or else the window system may wait
    on a driver-internal buffer and not wait for the copy to complete.
    
    Cc: mesa-stable
    Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34218>
    (cherry picked from commit cf23ffcbae9d3a420a633509440fbe0483b7efb2)
    
  • 9dd82a2e
    by Faith Ekstrand at 2025-04-02T11:04:13+02:00
    nvk: Use max_image_dimension for maxFramebufferWidth/Height
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34281>
    (cherry picked from commit 65d06d91cabff4f69c7047a810290c3b5e5e3e1a)
    
  • 7d321272
    by Faith Ekstrand at 2025-04-02T11:04:13+02:00
    nvk: Disable 32k images on Pascal A
    
    While we're here, add a comment about why we have this restriction in
    the first place since NVK and the proprietary driver are different here.
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34281>
    (cherry picked from commit 59b01dc764a1ed2f5231176290d2da75bcef2354)
    
  • 1c85e781
    by Trigger Huang at 2025-04-02T11:04:13+02:00
    radeonsi: Fix perfcounter start event in si_pc_emit_start
    
    The original typo caused performance counters to send STOP events
    instead of START, leading to incorrect profiling data.
    
    Fixes: 1a1138817c3 ("radeonsi: add a new PM4 helper radeon_event_write")
    
    Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34236>
    (cherry picked from commit f03b385d4b8d90950ccb997f8712bf86dee618d5)
    
  • ffa6fd4b
    by Samuel Pitoiset at 2025-04-02T11:04:13+02:00
    radv: do not trigger FCE or FMASK decompress on compute queue
    
    A pipeline barrier which contains an image layout transition like
    COLOR_ATTACHMENT_OPTIMAL -> TRANSFER_DST_OPTIMAL on compute queue
    would just hang. Such a barrier is useless in practice but it's legal.
    
    Prevent GPU hangs by skipping FCE or FMASK_DECOMPRESS when it's not
    on the graphics queue.
    
    Fixes dEQP-VK.synchronization2.layout_transition.compute_transition*.
    
    Cc: mesa-stable
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34231>
    (cherry picked from commit 086f529bbe8654bc5cf16dff46a6b4d6dbc196d7)
    
  • ae02c9a2
    by Pierre-Eric Pelloux-Prayer at 2025-04-02T11:04:13+02:00
    ac/nir: fix nir_metadata value of ac_nir_lower_image_opcodes
    
    This pass can insert new blocks so 'nir_metadata_control_flow' is not
    preserved.
    
    Fixes: eaf98b14220 ("ac/nir: implement image opcode emulation for CDNA, enable it in radeonsi")
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34241>
    (cherry picked from commit 785df1b980b6b173baece6b991caca2e2db9b2ab)
    
  • c8f9b803
    by Pierre-Eric Pelloux-Prayer at 2025-04-02T11:04:13+02:00
    radeonsi: use composed swizzle in cdna_emu_make_image_descriptor
    
    Otherwise the state swizzle is ignored.
    
    Fixes: 139bc6b8136 ("radeonsi: use common build buffer descriptor helpers")
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34241>
    (cherry picked from commit 7e2c3be4544f6327b34a305cb6725567a30cbad9)
    
  • cd871544
    by Dave Airlie at 2025-04-02T11:04:13+02:00
    gallivm: check for avx512vbmi and tell LLVM the correct answer.
    
    There are some CPUs out there which don't have vbmi and do have
    other avx512 and mesa crashes on those with illegal instructions.
    
    This was reported to Red Hat support.
    
    Cc: mesa-stable
    Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34282>
    (cherry picked from commit 5d6d167a7c2f492710b666c963cfa306e3d82aae)
    
  • 98530340
    by Jordan Justen at 2025-04-02T11:04:13+02:00
    intel/dev: Add BMG 0xe211 PCI ID
    
    Backport-to: 25.0
    Ref: bspec 68090
    Ref: https://patchwork.freedesktop.org/series/146769/
    Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
    Reviewed-by: Rohan Garg <rohan.garg@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34249>
    (cherry picked from commit d3ec467031780136412366a2a36a46d4c4d8cfdc)
    
  • 42b6bd48
    by Rebecca Mckeever at 2025-04-02T11:04:13+02:00
    panvk: Remove lower_tg4_broadcom_swizzle from panvk_preprocess_nir()
    
    We are already applying the .bagr swizzle in bifrost_preprocess_nir(), so
    remove lower_tg4_broadcom_swizzle from nir_lower_tex_options in
    panvk_preprocess_nir to avoid applying the swizzle twice.
    
    Fixes: 4050697a8f4 ("panvk: So more nir_lower_tex before descriptor lowering")
    
    Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
    Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34033>
    (cherry picked from commit f450807b68e1415d1154b4fe0be2af31b6c1fb11)
    
  • 82304cad
    by Robert Mader at 2025-04-02T11:04:13+02:00
    gallivm: Re-add check for passmgr before disposing it
    
    In can be NULL, but on LLVM >= 15 lp_passmgr_dispose() is
    a no-op.
    
    Fixes: 47cd0eee261 (gallivm: create a pass manager wrapper.)
    
    Signed-off-by: Robert Mader <robert.mader@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34312>
    (cherry picked from commit c0ec35bb423e4c443ba8e47e3c7f7239e5a5b208)
    
  • 29cf4608
    by Erik Faye-Lund at 2025-04-02T11:04:13+02:00
    panfrost: avoid accidental aliasing
    
    We already have a variable call "alignment" here, and aliasing it
    breaks things. Whoops, let's rename the variable to page_size to
    avoid this.
    
    Fixes: 22985caf3ff ("panfrost: sanity-check alignment")
    Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
    Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34156>
    (cherry picked from commit 1471279203a2675bca066229a46fe6ab87567b68)
    
  • d34e17a9
    by Taras Pisetskyi at 2025-04-02T11:04:13+02:00
    anv,driconf: Add sampler coordinate precision workaround for EVE Online
    
    Signed-off-by: Taras Pisetskyi <taras.pisetskyi@globallogic.com>
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12920
    
    Cc: mesa-stable
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34316>
    (cherry picked from commit 04962975fdea0e23957efc7480eadc28801ccf1c)
    
  • e4f5908a
    by Erik Faye-Lund at 2025-04-02T11:04:13+02:00
    panvk: check for texture-compression support
    
    We currently just assume that textureCompressionETC2 and
    textureCompressionASTC_LDR are always supported. And while that's true
    for all the G52s, G610s abd G310s we've seen out in the wild, it's not
    guaranteed to be true. An SoC vendor might disable support for one of
    these formats.
    
    So let's check properly, just for good measure.
    
    Fixes: d970fe2e9d6 ("panfrost: Add a Vulkan driver for Midgard/Bifrost GPUs")
    Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34206>
    (cherry picked from commit e4786cf971539f05a72318e1d121e9818d71e14e)
    
  • 2344060c
    by Erik Faye-Lund at 2025-04-02T11:04:13+02:00
    mesa/main: fix regression in extension-checking
    
    This condition accidentally got inverted when cleaning up code, whoops.
    
    Fixes: 3251f321b86 ("mesa: some cleanups for texparam extension checks")
    Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34248>
    (cherry picked from commit eb82d65a20a222a835282e7c0330d845480f519a)
    
  • d020c25b
    by Eric Engestrom at 2025-04-02T13:56:30+02:00
    .pick_status.json: Update to 0d2ebca39fd2a68bfb64dc2196e442e25dc90334
    
  • f94216bb
    by Dave Airlie at 2025-04-02T14:18:26+02:00
    nak: add reads after setting writes
    
    Otherwise we schedule this sort of thing wrong,
     r0    = iadd3 r0 c[0x0][0x0] rZ
     r0    = shf.l.w.i32 r0 rZ 0x2
     r0 p0 = iadd3 r0 c[0x1][0x0] rZ
    
    since raw latencies are more important than waw, but we go do a
    waw for the first two instructions instead of a raw which is correct.
    
    Fixes: 2d4e4450999d ("nak/calc_instr_deps: Rewrite calc_delays() again")
    Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33573>
    (cherry picked from commit 7a55a9afcce85b589b66e5636ef33e4bf696c953)
    
  • abb47924
    by Samuel Pitoiset at 2025-04-02T14:18:29+02:00
    ac/surface: fix selecting preferred alignments for HiZ/HiS on GFX12
    
    VK_MESA_image_alignment_control is used by vkd3d-proton to set
    optimal alignments for images. Though, the preferred alignment was
    only applied to the surface (or the stencil aspect) but not to the HiZ
    surface due to the NULL check.
    
    This caused rendering issues because swizzle modes didn't match.
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12831
    Fixes: 079f55d405e ("radv: advertise VK_MESA_image_alignment_control on GFX12")
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34322>
    (cherry picked from commit fac44c0ca0c70bc6f1fc125a5f6422406a6ffa76)
    
  • 27ecb47a
    by Ian Romanick at 2025-04-02T14:22:09+02:00
    brw/nir: Lower fsign again after last call to brw_nir_optimize
    
    No shader-db or fossil-db changes on any Intel platform.
    
    Fixes: 13332c23 ("intel/brw: Unconditionally run optimizations after nir_opt_uniform_subgroup")
    Closes: #12888
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34251>
    (cherry picked from commit e210b79ce3932f7fb1387d68a4cad495b77746f4)
    
  • ccc86bd6
    by Samuel Pitoiset at 2025-04-02T14:24:08+02:00
    Revert "radv: program SAMPLE_MASK_TRACKER_WATERMARK optimally for GFX11 APUs"
    
    This reverts commit 96e9c3fe77a315869a567dcdd5b1a2549a51925b.
    
    This actually causes random GPU hangs like on Phoenix.
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12461
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12426
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12692
    Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34306>
    (cherry picked from commit 64e6e043b3ca2d428b92bd08a6b42cc1d69c155b)
    
  • 93a4a2ec
    by Samuel Pitoiset at 2025-04-02T14:24:58+02:00
    Revert "radeonsi/gfx11: program SAMPLE_MASK_TRACKER_WATERMARK optimally for APUs"
    
    This reverts commit 6ce3a958523dd0be97d9fb9e29af9336440b1213.
    
    This likely also causes random GPU hangs.
    
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34306>
    (cherry picked from commit 5784a36fd1efeeb880014151270a8d787859c276)
    
  • b5927362
    by David Rosca at 2025-04-02T14:27:04+02:00
    radv: Add radv_format_description to remap 10/12bit formats to 16bit
    
    Remapping was missing for format description which made these formats
    effectively unsupported as zero format features were reported.
    
    Fixes: 0098f8ef35a ("radv: Remap 10 and 12 bit formats to 16 bit formats")
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34274>
    (cherry picked from commit 597f13b24421f4308ac9d513d9774f2b8673c120)
    
  • 8eab11c9
    by Eric Engestrom at 2025-04-02T18:35:11+02:00
    docs: add release notes for 25.0.3
    
  • c3afa2a7
    by Eric Engestrom at 2025-04-02T18:35:11+02:00
    VERSION: bump for 25.0.3
    

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