-
6be16b08
by Eric Engestrom at 2024-10-03T17:50:23+02:00
docs: add sha sum for 24.2.4
-
4aaf1e1d
by Fabio Pedretti at 2024-10-03T22:21:37+03:00
lower librust-syn-dev dependency version
mesa requires 2.0.15:
src/compiler/rust/meson.build
src/etnaviv/isa/meson.build
subprojects/packagefiles/syn/meson.build
set it to 2.0.48 which is the version in ubuntu noble, where it build
perfectly.
-
1df31a9b
by Eric Engestrom at 2024-10-07T14:55:40+02:00
.pick_status.json: Update to 1cbc316999af23b2dbe5f2fc0c057a9a26ae68b7
-
bd7af2d8
by Mike Blumenkrantz at 2024-10-07T17:16:15+02:00
zink: fix external_only reporting for dmabuf formats
this is based on format features
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31467>
(cherry picked from commit f3c206d61e24baa04467d5b8508230ac8da15431)
-
7c099248
by Mike Blumenkrantz at 2024-10-07T17:16:16+02:00
zink: block srgb with winsys imports
these are already a set format
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31467>
(cherry picked from commit f7b5faa1a276a29b1de9a87a645320703bc3d841)
-
543831aa
by Samuel Pitoiset at 2024-10-07T17:16:18+02:00
radv: do not expose NV DGC extensions on GFX6-7
These extensions were experimental and only exposed with radv_dgc=true
for vkd3d-proton. Only two games require DGC (Starfield and Halo
Infinite) and both also require sparse support which GFX6-7 can't
support.
GFX6-7 support is also mostly broken because IB2 can't be used when
indirect draw packets are used and RADV uses that to preprocess IBO.
Also with the EXT, indirect draws are more common and can't be
supported.
Everything could work with a bunch of time and workarounds but I don't
think it's worth the effort given there is no real use.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31491>
(cherry picked from commit e4f67f2106768eeb34ea40ac73a298e19fe5969f)
-
2155cd54
by Lucas Stach at 2024-10-07T17:16:19+02:00
etnaviv: re-emit uniforms on sampler view changes when txs is used
The shader uniforms used for emulating TXS depend on the current
sampler view state and thus need to be re-emitted when this
states changes.
Fixes: 88f399b65157 ("etnaviv: nir: support intrinsic used for txs lowering")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31495>
(cherry picked from commit c12697abe0cb6aac45aeac3ebb9e55f64cfc9f37)
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df0aa4eb
by Carlos Santa at 2024-10-07T17:16:21+02:00
intel/hang_replay: fix the typo in the ioctl call
What we really want to pass is DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
vs DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
Fixes: a9f1151de27 ("intel/hang_replay: use hw image param")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11959
Signed-off-by: Carlos Santa <carlos.santa@intel.corp-partner.google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31494>
(cherry picked from commit 700141da43d9ec13d5deffedb14c3c4a9266f8d9)
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d4809473
by Carlos Santa at 2024-10-07T17:16:53+02:00
intel/hang_replay: remove EXEC_OBJECT_WRITE
This flag causes the following failure:
total_vma: 0x0000000071c9d000
fail to set context hw img: Invalid argument
Fixes: bab52763f45 ("intel/hang_replay: fix batch address")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11959
Signed-off-by: Carlos Santa <carlos.santa@intel.corp-partner.google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31494>
(cherry picked from commit 39e3015c3609408d7f0c698fc750b2f040049446)
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90b269cd
by Eric Engestrom at 2024-10-08T12:39:27+02:00
Revert "mesa: fix sample count handling for MSRTT"
This reverts commit b36d9d9a31f475e375db228c74fb4e317edd72fa.
This commit is causing issues [1] and is not worth backporting, so let's
just revert it.
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31485#note_2599128
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40709811
by Eric Engestrom at 2024-10-08T13:12:37+02:00
.pick_status.json: Mark 894b37e06099c60f371e9b181e3f84cfc29c49bb as denominated
-
7a450a43
by Eric Engestrom at 2024-10-08T13:12:37+02:00
.pick_status.json: Update to 78b614b333b01ce0dfb9e4d9353a02a03fdcc154
-
cd69a8f0
by Tapani Pälli at 2024-10-08T13:12:43+02:00
intel/genxml: introduce L3 Fabric Flush for gfx12
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 8cb08830e6bfee6940ed1a3933f7fa626792b293)
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ef5abfd5
by Tapani Pälli at 2024-10-08T16:54:23+02:00
intel/ds: add L3 fabric flush support
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 03f762f90c54c09e58cc736e0ac7c684ac367a45)
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8f16e243
by Tapani Pälli at 2024-10-08T16:54:24+02:00
anv: add plumbing/support for L3 fabric flush
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit e3814dee1ac0f90771b921a4f6f5aed10f06e8d4)
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28691fb5
by Tapani Pälli at 2024-10-08T16:54:24+02:00
iris: add plumbing/support for L3 fabric flush
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 11774075a354dda934aaedcfb34bd88956806d41)
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21781fb3
by Tapani Pälli at 2024-10-08T16:54:24+02:00
iris: add depth, DC and L3 fabric flush for aux map invalidation
These should be included according to table in Bspec 43904.
Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 3e29ea69ce683b23dd8708f13dd8b98433a3c59c)
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8d3fc29b
by Tapani Pälli at 2024-10-08T16:54:24+02:00
anv: add depth, DC and L3 fabric flush for aux map invalidation
These should be included according to table in Bspec 43904.
Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
(cherry picked from commit 78b614b333b01ce0dfb9e4d9353a02a03fdcc154)
-
2a17eb83
by Eric Engestrom at 2024-10-08T23:58:23+02:00
.pick_status.json: Update to 336f80137d26230bd124f475bd4382a0c727004f
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4fdd0860
by Samuel Pitoiset at 2024-10-08T23:58:25+02:00
radv: fix conditional rendering with DGC preprocessing on compute
Preprocess now must use the same conditional rendering state as the
execute, so the DGC prepare shader must reset the number of sequences
to generate an empty cmdbuf for compute.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31563>
(cherry picked from commit 336f80137d26230bd124f475bd4382a0c727004f)
-
19d421ab
by Lionel Landwerlin at 2024-10-11T23:00:58-04:00
.pick_status.json: Update to c8c354d9c3a2e79230723f1c8b0571b20d034fee
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ba13c306
by Christian Gmeiner at 2024-10-11T23:01:00-04:00
etnaviv: Improve split sampler check
Check if the block size is bigger then 64. We want to block
e.g. one of the following formats:
- R32G32B32A32_FLOAT
- R32G32B32A32_SINT
- R32G32B32A32_ZINT
Unbreaks e.g. dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb16i
Fixes: e481c1269c3 ("etnaviv: disable 64bpp render/sampler formats")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27111>
(cherry picked from commit 04521c14b0d90f54228809d240630e35033f39a4)
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c644f737
by Maíra Canal at 2024-10-11T23:01:03-04:00
v3d: Don't use performance counters names array with an older kernel
Starting with Linux v6.11+, performance counter information is no
longer duplicated in both the kernel and userspace. Instead, an IOCTL
retrieves this information, allowing userspace to maintain a local
array for reuse, thus avoiding redundant kernel queries.
However, support for older kernels without these new IOCTLs remains.
To distinguish between versions, we check `devinfo->max_perfcnt` -
which is non-zero on Linux v6.11+ and zero on older kernels.
Currently, applications using performance queries on platforms with
older kernels encounter a SEGFAULT, as we don't validate
`devinfo->max_perfcnt` before accessing the userspace array for
performance counter information.
This commit makes sure that, if `devinfo->max_perfcnt` is zero,
`screen->perfcnt_names` will be NULL. This way, we can check if
`screen->perfcnt_names` is different than NULL before attempting to use
the userspace array.
Fixes: 017dde0d1ca ("v3d: Use DRM_IOCTL_V3D_GET_COUNTER to get perfcnt information")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31552>
(cherry picked from commit 47a78614eaece530244a23ec630e57b24654db46)
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497afad8
by Lionel Landwerlin at 2024-10-11T23:01:56-04:00
isl: remove duplicated copy for tileX/TileY
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
(cherry picked from commit 52263413f47e9190d9f53c9ef336c3ab46070598)
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ce61b23c
by Tapani Pälli at 2024-10-11T23:02:20-04:00
drirc/anv: force_vk_vendor=-1 for Silent Hill 2
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11992
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31573>
(cherry picked from commit f77ffd6b7c870a3355b8920fe2aa4da0e2721b4b)
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36e2c671
by David Rosca at 2024-10-11T23:03:14-04:00
radeonsi/vcn: Fix out of bounds write when invalidating QP map regions
Fixes coverity issue 1559460 Out-of-bounds write
Fixes: 9c07a2e10d6 ("radeonsi/vcn: ROI feature implementation")
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
(cherry picked from commit 10a73564889a81329bf5b79744a8bc3a8c4bdeed)
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14967005
by David Rosca at 2024-10-11T23:03:15-04:00
radeonsi/vcn: Fix out of bounds read in H264 decode
When all 16 references are used, this would read pic->ref[16].
Same for HEVC, but HEVC only uses 15 reference frames so it would
never happen there yet is still reported by coverity.
Fixes coverity issues 1497283 and 1465569 Out-of-bounds read
Cc: mesa-stable
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
(cherry picked from commit 20d5020ad718743af593f80755117153d0288a4a)
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e6d729fa
by Jose Maria Casanova Crespo at 2024-10-11T23:03:18-04:00
v3d: initialize job local key with the 8 color buffer available in v7.1+
Fixes: 9e90d955087 ("v3d,v3dv: support up to 8 render targets in v7.1+")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31582>
(cherry picked from commit 687ed3fcaa831376a9a3a9860400959eb4633569)
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a1689bce
by Satadru Pramanik at 2024-10-11T23:03:19-04:00
Update lp_bld_misc.cpp to support llvm-19+.
Fixes #11896.
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31533>
(cherry picked from commit fa9cd89a85b904615ebc11da609445b5b751e68d)
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ce52e7b1
by Bas Nieuwenhuizen at 2024-10-11T23:03:21-04:00
radv: Disable EXT BDA capture and replay.
Spec allows calling VkBufferGetDeviceAddressInfo without binding to memory:
VUID-VkBufferDeviceAddressInfo-buffer-02600
If buffer is non-sparse and was not created with the VK_BUFFER_CREATE_DEVICE_ADDRESS_CAPTURE_REPLAY_BIT flag, then it must be bound completely and contiguously to a single VkDeviceMemory object
Which we can only do by making it sparse unconditionally, which feels very wrong to me for a capture & replay extension as that significantly impacts execution.
Current theory is that this was only intended for the EXT and not the core functionality. As such, let's disable capture using the EXT.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31140>
(cherry picked from commit c8c354d9c3a2e79230723f1c8b0571b20d034fee)
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710d343d
by Eric Engestrom at 2024-10-14T21:52:49+02:00
.pick_status.json: Update to e8e8c17a0c893a74bff58c2abbc0ee8c451db933
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d487e0bd
by Pavel Ondračka at 2024-10-14T21:52:50+02:00
r300: remove gl_ClipVertex early
There is no HW support, but in some cases the shaders mostly work even
if we ignore it, and so far we have just done so. However since the
driver didn't know to what output position in the PVS we should
redirect it, it ended in the first slot. Importantly, if the
CLIP_VERTEX output would be written after position (which actually
belongs in the first slot) it would overwrite it and things blow up.
So just remove it early, and also improve the warning a bit, including
the part that we could use draw module to actually emulate the feature.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11856
Fixes: 5dcef1e7b87498f1f115f2167a007fb724987b97
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31547>
(cherry picked from commit cc14d402393a5fbedeec6ac7d4f936e6b9050d7e)
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14ee858c
by Rob Clark at 2024-10-14T21:52:51+02:00
freedreno: Balance out u_blitter cb0 save/restore
Fixes: 5de33f3d3e15 ("freedreno: Implement stencil blit fallback")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31569>
(cherry picked from commit c7b126f6273eb4e60f3d36822593e90ad529251a)
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97aba55d
by Samuel Pitoiset at 2024-10-14T21:52:53+02:00
radv: fix returning non-zero captured address without binding
The Vulkan spec says:
"If the buffer was created with a non-zero value of
VkBufferOpaqueCaptureAddressCreateInfo::opaqueCaptureAddress or
VkBufferDeviceAddressCreateInfoEXT::deviceAddress, the return
value will be the same address that was returned at capture time."
My interpretation is that you can get the buffer device address before
binding if you passed a non-zero address during buffer creation. The
returned BDA would be similar if a memory object is bound to the
buffer later.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31145>
(cherry picked from commit 03b4477c8feb4b0b235c9558b73495bb4c815fa8)
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e3cd0dcb
by David Heidelberg at 2024-10-14T21:52:57+02:00
amd: Pass addrlib cpp args to the tests
The declaration and definition used by tests otherwise differs from
addrlib.
Found by LTO -Werror=lto-type-mismatch.
Fixes: 1d69c0419b39 ("amd/addrlib: prevent defining regparm differently")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31613>
(cherry picked from commit d14d3c5bdda9947c9bfb16d30c0e95798362af02)
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4359694c
by Samuel Pitoiset at 2024-10-14T21:52:59+02:00
radv: use app names instead of exec name for shader based drirc workarounds
Otherwise, they aren't applied if shaders are pre-compiled using
builders because the executable name would be fossilize-replay.
Using pApplicationName is the correct way to do because it's replayed
by Fossilize correctly.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31621>
(cherry picked from commit 56813236f47a8d2f8d7fe3dfb3909797176f6e82)
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3c5dc257
by Eric Engestrom at 2024-10-15T18:26:03+02:00
.pick_status.json: Update to 6d6d5b869c5a4afd7fb30c7a5b1def8fcc14d255
-
65bc5a81
by Tapani Pälli at 2024-10-16T15:21:11+02:00
mesa: fix DXT1 support with EXT_texture_compression_dxt1
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11987
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31540>
(cherry picked from commit a3c03b6a96ff3c914ca8dcc675005cf986203d03)
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70e3231f
by Jordan Justen at 2024-10-16T15:21:11+02:00
intel/dev: Add 0xb640 ARL PCI id
Backport-to: 24.2
Ref: https://gitlab.freedesktop.org/drm/kernel/-/commit/35667a0330612bb25a689e4d3a687d47cede1d7a
Ref: bspec 55420
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31618>
(cherry picked from commit 0530d4d59d7727fcefab1bff870b9923ea9f2098)
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7ebbb0c5
by David Heidelberg at 2024-10-16T15:21:11+02:00
osmesa: Fix OSMesaGetDepthBuffer() test without depth
Correct copy-paste typo of depth_cpp instead of depth and use nullptr
instead of NULL, as GTest suggest in documentation:
When comparing a pointer to NULL, use EXPECT_EQ(ptr, nullptr) instead of EXPECT_EQ(ptr, NULL).
Fixes: ef9362acb81b ("gallium/osmesa: Return cleanly for OSMesaGetDepthBuffer() with no depth.")
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31606>
(cherry picked from commit 321012b95d61cf1c081079376ffab7f159a6368b)
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3cd62ed4
by Alessandro Astone at 2024-10-16T15:21:11+02:00
panvk: Add missing headers to android platform
Fixes: 2de95773b9c ("panvk: Kill panvk_private.h")
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31610>
(cherry picked from commit 2c79e012593178075eac31dfa907ea64bf448b1c)
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fec4dadd
by Timothy Arceri at 2024-10-16T15:21:11+02:00
nir/glsl: set cast mode for image during function inlining
Fixes: d681cf96fbf9 ("nir/glsl: set deref cast mode during function inlining")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11980
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31554>
(cherry picked from commit 46facf903778dfb2ae530cbb2cf4d1f660d467dd)
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224fe5ad
by Marek Olšák at 2024-10-16T15:21:11+02:00
nir/opt_vectorize_io: fix stack buffer overflow with 16-bit output stores
uncovered by unrelated work
Fixes: 2514999c9c5d4b64b0 - nir: add nir_opt_vectorize_io, vectorizing lowered IO
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31644>
(cherry picked from commit 64c4d29e65853d0c31a5c2adcd749077b39bc446)
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97fcf876
by Faith Ekstrand at 2024-10-16T15:21:11+02:00
nvk: Advertise 64-bit atomics on buffer views
We also add an nvk_format_supports_atomics() helper. This helper lives
in NVK for now because it's not just about the format and hardware but
also about whether or not we have compiler support in NAK.
Fixes: 1d10de539c2e ("nvk: Implement VK_EXT_shader_image_atomic_int64")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31633>
(cherry picked from commit c2684968de46a1c1a0ab80a9104c48b742c687c2)
-
e3d72952
by Eric Engestrom at 2024-10-16T15:21:11+02:00
.pick_status.json: Update to 7b09fc98fb60becde7435b2303f7dd329937f6cb
-
da09a3e9
by Marek Olšák at 2024-10-16T15:21:11+02:00
gallium/u_threaded: fix crash in tc_create_image_handle due to resource == NULL
Fixes: 3df9d8ed807a6693d5fc8 - gallium/u_threaded: implement pipelined partial buffer uploads using CPU storage
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12020
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31651>
(cherry picked from commit 88f057eb531180c37f0d2c2d5bbbdc6e0a261816)
-
8ada91f6
by Marek Olšák at 2024-10-16T15:21:11+02:00
radeonsi: set the valid buffer range for bindless image buffers
This was missing.
Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31651>
(cherry picked from commit 2272db2ac66561e4389d4101596480234378e00d)
-
bde3e18d
by Timothy Arceri at 2024-10-16T15:21:11+02:00
nir/glsl: set deref cast mode for blocks during function inlining
More cast fixes this time for UBO and SSBO. Which were missing testing
previously.
Fixes: d681cf96fbf9 ("nir/glsl: set deref cast mode during function inlining")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11587
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31668>
(cherry picked from commit aa7c59e02cfffa70cac83b2c126fbb5bd313ff6c)
-
5b50c4e9
by Danylo Piliaiev at 2024-10-16T15:21:11+02:00
nir/opt_16b_tex_image: Sign extension should matter for texel buffer txf
Texel buffer could be arbitrary large, so the assumption being made in
the following comment is wrong:
"Zero-extension (u16) and sign-extension (i16) have
the same behavior here - txf returns 0 if bit 15 is set
because it's out of bounds and the higher bits don't matter."
Sign extension should matter for GLSL_SAMPLER_DIM_BUF.
This fixes the case of doing texelFetch with u16 offset:
uniform itextureBuffer s1;
uint16_t offset = some_ssbo.offset;
value = texelFetch(s1, offset).x;
If the offset is higher than s16 optimization incorrectly
left it as 16b.
In spirv the above glsl is translated into:
%22 = OpLoad %ushort %21
%23 = OpUConvert %uint %22
%24 = OpBitcast %int %23
%26 = OpImageFetch %v4int %16 %24
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31664>
(cherry picked from commit 7b09fc98fb60becde7435b2303f7dd329937f6cb)
-
9ea82480
by Eric Engestrom at 2024-10-16T15:21:11+02:00
.pick_status.json: Mark c747c1e1f4f48b543a8ed8f7f7db32e5393d41a0 as denominated
-
f1d66fdb
by Kenneth Graunke at 2024-10-16T15:21:11+02:00
intel/brw: Delete Gfx7-8 code from emit_barrier()
Those are supported by elk, not brw.
Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
(cherry picked from commit a9d948878894660f97dd6d63618ced35400aec77)
-
6fde580e
by Kenneth Graunke at 2024-10-16T15:21:11+02:00
intel/brw: Make a ubld temporary in emit_barrier()
Saves typing .exec_all() in a lot of places.
Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
(cherry picked from commit 7c9eb8b289bb6fe891cae78377e94589299afeb4)
-
1f2d6b6a
by Kenneth Graunke at 2024-10-16T15:21:11+02:00
intel/brw: Fix register and builder size in emit_barrier() for Xe2
We were manually allocating 1 REG_SIZE for the barrier payload, which is
only half a register on Xe2. This should eventually get allocated to a
whole register anyway, but it's awkward in the meantime. Also, we were
zero-initializing the header using group(8, 0) which only initialized
half the register. The rest of the fields are Reserved MBZ, so they're
likely unused and unread anyway - but it's better to zero-initialize
them so we don't get random undefined, miserable-to-debug behavior.
Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
(cherry picked from commit dea61b739913fe85981cd3ef3ec563087c15b8da)
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8562a40d
by Kenneth Graunke at 2024-10-16T15:21:11+02:00
intel/brw: Delete more Gfx8 code from brw_fs_combine_constants
These platforms are supported by elk, not brw.
Backport-to: 24.2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
(cherry picked from commit d9e502265034848b7908afa9a974cc0d618e1197)
-
52d70cb7
by Kenneth Graunke at 2024-10-16T15:21:11+02:00
intel/brw: Use whole 512-bit registers in constant combining on Xe2
Xe2 increased the register size from 256-bits to 512-bits. So we can
store 32 16-bit values in a register, rather than 16 values. Prior to
this patch, we hadn't updated the pass, so the second half of each of
our registers was unused.
Backport-to: 24.2
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31499>
(cherry picked from commit 4cb67cb07ae53dd47b261ce6a236899bf1cf7ea6)
-
a24d356a
by Paulo Zanoni at 2024-10-16T15:21:11+02:00
anv/trtt: set every entry to NULL when we create an L2 table
When we create sparse resources the first thing we do is a NULL bind
on them, as the Vulkan spec mandates certain behavior even for unbound
sparse resources. We do this with the minimal effort possible: if we
can get away with marking an L2 pointer as NULL in the L3 table, we
just do it and return, instead of going all the way to creating L1
tables and marking all the final entries as NULL.
The strategy we were using had a bug that could lead to previously
created NULL entries not being marked as NULL anymore. Let's give an
example:
(before proceeding, keep in mind that a NULL entry in the L3 and L2
tables has bit 1 set, it does *not* have the value 0)
- Create a 64mb buffer that uses an entire L1 table (needs to be
properly aligned), which triggers a NULL bind.
- Our algorithm will just set the L3 entry (pointing to the L2
table) as NULL.
- Create a 64kb buffer that uses the same L2 table (but a different
L1 table).
- The NULL bind triggered won't do anything as the L2 table is
already NULL.
- Bind the first buffer to actual memory. This will end up creating
the L2 table and the L1 table. The only entry we will set in the L2
table will be the one pointing to the L1 table. All the other
values will be 0 (so they won't have neither the NULL or Invalid
bits set: access to them will lead to page faults).
- Try to use the second buffer, which is still unbound. It was
relying on the fact that its L2 table pointer was NULL, but now
it's not anymore, so the page walker will fetch the L1 entries in
the L2 table and they will all be zero instead of having the NULL
bit set.
The fix is pretty simple: whenever we create a new L2 table, set every
entry to NULL (except the one we're about to set to non-NULL). This
preserves behavior for every other NULL resource relying on the L3
entry being set to NULL.
We don't need to do this for the L1 table because its entries are
different and instead of having bits to signal NULL entries we have
a special TR-TT register that we can set that gets compared to check
if an entry is NULL, and we conveniently program it to 0: see
ANV_TRTT_L1_NULL_TILE_VAL.
I am not aware of any real workloads that are triggering this
behavior, I found this issue while investigating something else,
running a custom sparse program in our pre-silicon environment, and it
told us about the page faults.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30953>
(cherry picked from commit 4c366ef67bd9e45618bb16826fc2f60e2f949892)
-
d53e1c07
by Paulo Zanoni at 2024-10-16T15:21:11+02:00
anv/trtt: fix error handling when adding binds
We're missing a check for 'result' in the middle of a loop and we have
an unnecessary check for 'result' after the loop.
Fixes: 7da5b1caef21 ("anv: move trtt submissions over to the anv_async_submit")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30953>
(cherry picked from commit aea9ac47d23d842bc1b10241c36fd8db7653113d)
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c13e5dca
by Eric Engestrom at 2024-10-16T18:57:51+02:00
docs: add release notes for 24.2.5
-
3b9fcb7e
by Eric Engestrom at 2024-10-16T18:57:54+02:00
VERSION: bump for 24.2.5
-
e2fa6b6e
by Eric Engestrom at 2024-10-16T19:25:55+02:00
docs: add sha sum for 24.2.5
-
7e718ab5
by Eric Engestrom at 2024-10-22T12:40:38+02:00
.pick_status.json: Update to 0bffe8ec053f2a43795515b0f9c64cf98b5bd8b7
-
7569a01b
by Christian Gmeiner at 2024-10-22T12:40:47+02:00
etnaviv: nir: Enforce stricter swizzle for virtual scalar x register
This change enforces stricter swizzle behavior for the virtual scalar x
register, addressing a regression encountered in piglit's
spec@glsl-1.10@execution@derivatives@glsl-derivs-abs-sign test.
The regression occurred after switching to derivative intrinsics.
CC: mesa-stable
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31034>
(cherry picked from commit 5a15b36a64c690725224eb9524e3376595a07b39)
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421848fb
by Lionel Landwerlin at 2024-10-22T12:40:49+02:00
anv: use stage mask to deduce cs/pb-stall requirements
When flushing the render target cache for future operations, we need a
stall at pixel scoreboard. We likely didn't see any issue until now
because a change in render target added the pb-stall.
When using a 2 compute shaders with the following pattern :
vkCmdDispatch()
vkCmdPipelineBarrier() ImageBarrier with (src|dst)AccessMask=0 & identical layout
vkCmdDispatch()
we should ensure that the first dispatch is completed before executing
the second one, otherwise they can race to on resource accesses. This
fixes failures in some new CTS tests.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31676>
(cherry picked from commit ea2bbe327106cfe5b6cb24c9bed5f41b0ac41f02)
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dd9c41be
by Anil Hiranniah at 2024-10-22T12:40:50+02:00
panfrost: Fix a memory leak in the CSF backend
The geometry BO should be released in csf_cleanup_context().
Fixes: 447075eeeef8 ("panfrost: Add support for the CSF job frontend")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31705>
(cherry picked from commit 3d066e5ef188cd1f49f5b27627ae9e63a9151011)
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6b58431e
by Zan Dobersek at 2024-10-22T12:40:51+02:00
zink: fix bo_export caching
When creating and caching the bo_export object for a given zink_bo, the
screen file descriptor was used. Since no buffer object's file descriptor
would match that, bo_export objects were continuously added to the exports
list and no bo_export was effectively picked from the cache. Using the
buffer object's file descriptor avoids that.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: b0fe621459c ("zink: add back kms handling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31715>
(cherry picked from commit b44480e86a13c2f268174380d65ed6ac10374fb8)
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c4939761
by Eric Engestrom at 2024-10-22T15:59:43+02:00
.pick_status.json: Mark 1dc125338e19325b0926840303731ec00af83125 as denominated
-
a0c91060
by Iván Briano at 2024-10-22T15:59:44+02:00
hasvk: fix non matching image/view format attachment resolve
Port of 5a7e58a4301 ("anv: fix non matching image/view format attachment resolve")
to hasvk.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31696>
(cherry picked from commit 8423998d6942164c576fa219bd5f93d2fabf8baf)
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62d11bb2
by Lionel Landwerlin at 2024-10-22T15:59:46+02:00
elk: Don't apply discard_if condition opt if it can change results
Replicates the change from 57344052b6 ("intel/brw: Don't apply
discard_if condition opt if it can change results")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0ba9497e66 ("intel/fs: Improve discard_if code generation")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31604>
(cherry picked from commit 608d521086c651dc7061c961c0614457dd5e6299)
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70432dfc
by Paulo Zanoni at 2024-10-22T15:59:47+02:00
anv/trtt: fix the creation of sparse buffers of size 2^32 on 32bit systems
When the VkBuffer is of size 2^32 (which matches maxBufferSize), we
have vm_bind->size set to 2^32, which is fine because it fits in an
uint64_t. What is not fine is the 'i' variable being size_t, because
on 32bit systems it will loop forever since it will always be smaller
than 2^32.
Credits to Iván for not only reporting it, but also coming up with the
solution at the same time as I did, then testing it.
Cc: mesa-stable
Reported-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31698>
(cherry picked from commit da396a49a08d62b8d9a04971635bd6d12241b7f7)
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3dc3ec93
by Lionel Landwerlin at 2024-10-22T15:59:48+02:00
isl: fix range_B_tile end_tile_B value
Quoting the documentation :
"The returned range is a half-open interval where all of the
addresses within the subimage are < end_tile_B."
This is obviously not true with images smaller than a logical tile.
Currently the code return 1.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
(cherry picked from commit bcc820950d277513454f033706d194b4a61b9d23)
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eb40b926
by Pavel Ondračka at 2024-10-22T15:59:48+02:00
nir/nir_group_loads: reduce chance of max_distance check overflow
Helps for the case when max_distance is set to ~0, where the pass would now
only create groups of two loads together due to overflow. Found while
experimenting with this pass on r300, however the only driver currently
affected is i915.
With i915 this change gains around 20 shaders in my small shader-db
(most notably some GLMark2, Unigine Tropics, Tesseract, Amnesia) at
the expense of increased register pressure in few other cases.
I'm assuming this is a good deal for such old HW, and this seems like what
was intended when the pass was introduced to i915, but anyway this
could be tweaked further driver side with a more optimized max_distance
value. Only shader-db tested.
Relevant i915 shader-db stats (lpt):
total tex_indirect in shared programs: 1529 -> 1493 (-2.35%)
tex_indirect in affected programs: 96 -> 60 (-37.50%)
helped: 29
HURT: 2
total temps in shared programs: 3015 -> 3200 (6.14%)
temps in affected programs: 465 -> 650 (39.78%)
helped: 1
HURT: 91
GAINED: 20
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: GKraats <vd.kraats@hccnet.nl>
Fixes: 33b4eb149ea7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31529>
(cherry picked from commit 33c8dc4f1839b350cc763074d269064ea9ac4365)
-
4abcd9d9
by Pierre-Eric Pelloux-Prayer at 2024-10-22T15:59:49+02:00
radeonsi/gfx12: fill missing dcc tiling info
Display DCC support has been enabled in 0bb83a4060a but this TODO
was forgotten.
Now that the kernel is fixed, we can set the related fields.
Fixes: 0bb83a4060a ("ac/surface: finish display DCC for gfx12")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31683>
(cherry picked from commit bb085966458cf2684d1ce1f9d270ea498da003e7)
-
8e3c3652
by Pierre-Eric Pelloux-Prayer at 2024-10-22T15:59:50+02:00
radeonsi: fix radeon_canonicalize_bo_flags domain handling
ffs(VRAM, GTT) returns the GTT bit as it's the smaller.
Simplify the code by explicitely selecting VRAM when both
domains are active, otherwise assert that only 1 bit is set.
Fixes: 593f72aa212 ("winsys/amdgpu-radeon: rework how we describe heaps")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31683>
(cherry picked from commit 19fa5561bea5b1031a0f7dab42bb5cac35d616ae)
-
b5a6e63c
by Pierre-Eric Pelloux-Prayer at 2024-10-22T15:59:51+02:00
ac/surface: fix determination of gfx12_enable_dcc
For surfaces without a modifier, the surf_size check wasn't
necessary, but it was also invalid since surf_size is set later
(in gfx12_compute_miptree).
Since it's not required anyway, drop this check.
Fixes: 060d5dacfd1 ("ac: add gfx12 DCC shared code")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31683>
(cherry picked from commit 5607c7ee4906dad8483c2c6668fceee255ac6ea2)
-
e688ecb6
by Mike Blumenkrantz at 2024-10-22T15:59:51+02:00
va: fail context create if driver does not support video
not all drivers support this, and forcing them to implement stubs
is not how gallium works
cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31736>
(cherry picked from commit fd0b20e8e857a888deddcc33b54cc5415daaf70e)
-
ea84fd96
by Mike Blumenkrantz at 2024-10-22T15:59:52+02:00
vdpau: fail context create if driver does not support video
not all drivers support this, and forcing them to implement stubs
is not how gallium works
cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31736>
(cherry picked from commit b4e18fb188cb30bc506b2e426e6e17c75ca3ec8b)
-
bd1821fe
by Georg Lehmann at 2024-10-22T15:59:54+02:00
aco: fix 64bit extract_i8/extract_i16
The old code only sign extended to 32bit, with a zero hi half.
Fixes: 1f2518ef9fc ("aco: implement nir_op_extract/nir_op_insert")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31734>
(cherry picked from commit 10951bb11ab982941b5c80765e7be266eae20bd4)
-
ef95d2b1
by Rhys Perry at 2024-10-22T15:59:54+02:00
radv: fix output statistic for fragment shaders
This is a per-component bit mask (0xf for each output).
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 0e0c2574d1d3 ("radv: Add shader stats for inputs and outputs.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31593>
(cherry picked from commit 9784165de58d1af50c7ed84637d683cb63a0fdda)
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6a866679
by Karol Herbst at 2024-10-22T15:59:55+02:00
radeonsi: move si_compute::global_buffers to si_context
si_set_global_binding is a context function, but it touches the bound
compute program. As radeonsi also advertizes PIPE_CAP_SHAREABLE_SHADERS
this function is supposed to be safe when the same compute state object is
bound to multiple contexts at once.
In order to fix this data race global_buffers is moved to si_context so it
becomes context private data instead.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31672>
(cherry picked from commit 179859763736c8270956f4d6fcc95491f4532128)
-
e9884d16
by Eric Engestrom at 2024-10-23T12:58:07+02:00
.pick_status.json: Update to d5581b112452398e3e56ae0e9ab8f585b6374020
-
2f2b79a4
by David Rosca at 2024-10-23T12:58:10+02:00
frontends/va: Fix parsing leb128 when using more than 4 bytes
Bit shift would go over 32 bits. Also add assert for maximum
value as allowed by spec.
Fixes coverity issue 1469252 Bad bit shift operation
Fixes: 5edbecb8569 ("frontends/va: adding va av1 encoding functions")
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31622>
(cherry picked from commit 2cb3c2e8d5e306bd64a303c3254dd80b9c49248f)
-
fcfb957a
by Chia-I Wu at 2024-10-23T12:58:12+02:00
panvk: fix descriptor set layout hash
Save the hash to layout->vk.blake3, rather than the unused layout->hash.
Fixes: 73518dc169f ("panvk: Add Valhall DescriptorSetLayout implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31773>
(cherry picked from commit c23f7a2562bbcc8b5dd7d3912b6f10bd60c875a8)
-
1a3141ac
by Tapani Pälli at 2024-10-23T12:58:13+02:00
iris: implement VF_STATISTICS emit for Wa_16012775297
Emit dummy VF_STATISTICS state before each VF state.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31759>
(cherry picked from commit 9465d6e3d7cb2925c63f2e6ed057de87f0699352)
-
40ca28af
by Tapani Pälli at 2024-10-23T12:58:13+02:00
anv: implement VF_STATISTICS emit for Wa_16012775297
Emit dummy VF_STATISTICS state before each VF state.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31759>
(cherry picked from commit dddd7655531557dcd1f46058561c6213ee5377a6)
-
cb1b63cb
by Rohan Garg at 2024-10-23T12:58:14+02:00
anv: Xe2+ doesn't need the special flush for sparse
Fixes: 4aa3b2d ('anv: LNL+ doesn't need the special flush for sparse')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31737>
(cherry picked from commit 2a34b492d8025c83cd0772d6c761ff2d24dabde9)
-
2533e38a
by Eric Engestrom at 2024-10-28T15:49:29+01:00
.pick_status.json: Update to 6775524c69c660a4585e3e5ed85f4d7b9129054f
-
5aac8d24
by Daniel Schürmann at 2024-10-28T15:49:34+01:00
aco/spill: fix faulty assertions
By unintentionally using integer division for score(), these
assertions were likely to be raised by accident.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31769>
(cherry picked from commit 30d85b23efeab77a308c63e2872beaf25be3f867)
-
bce34bc4
by Matt Coster at 2024-10-28T15:49:38+01:00
pvr: Fix ds subtile alignment NULL pointer dereference
pvr_cmd_buffer_end_sub_cmd() sets the current sub-command to NULL. This was
causing list_move_to(), which is called immediately after this, to access a NULL
pointer. Fix this by storing the current sub command before calling
pve_cmd_buffer_end_sub_cmd() so that this can be used instead when modifying the
list.
Fixes: d1b17a5edcd ("pvr: Implement ZLS subtile alignment")
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 6ba3c5263d979209af3b6f2bf4546b158362b0fe)
-
2e0bc63f
by Matt Coster at 2024-10-28T15:49:38+01:00
pvr: Fix reordering of sub-cmds when performing ds subtile alignment
The use of list_move_to() meant that the first transfer sub-command wasn't being
correctly placed before the target graphics sub-command.
Fixes: d1b17a5edcd ("pvr: Implement ZLS subtile alignment")
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit fbca3d64add37da9711200350dad51cb68ae22c4)
-
14e183bc
by Frank Binns at 2024-10-28T15:49:39+01:00
pvr: fix image size calculation when mipLevels is 1
When calculating the size of an image, the driver was always factoring in space
for a full mip chain. However, this isn't necessary when mipLevels is 1 and this
resulted in applications needing to allocate more memory for these images than
is strictly necessary. Fix this by calculating the size of additional mip levels
(those greater than mipLevels) when more than 1 mip level has been requested.
Fixes: 2a3aa6da503 ("pvr: Fix cubemap layer stride")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 5ef9c552b2e72e727b6c4b4994e727ffa9c72bbd)
-
f51aef81
by Luigi Santivetti at 2024-10-28T15:49:40+01:00
pvr: fix calculation for textures z position fractional part
The fractional part of the z position will only be used with linear or bi-linear
filtering. Otherwise it is safe to discard the original fractional value and
reset it to 0.5.
Fixes: 480bdff4b52 ("pvr: Add support to process transfer and blit cmds")
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 1b67637fa09a969161b7e8a7ab10ff14bbfe5bad)
-
5284b3fc
by Iliyan Dinev at 2024-10-28T15:49:40+01:00
pvr: fix mipmap alignment for non-32bpp textures
There is no alignment necessary between mip levels.
Fixes test cases:
dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_fastest
dEQP-GLES2.functional.texture.mipmap.2d.generate.a8_non_square_nicest
dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_fastest
dEQP-GLES2.functional.texture.mipmap.2d.generate.l8_non_square_nicest
dEQP-GLES3.functional.texture.mipmap.2d.generate.a8_non_square_fastest
dEQP-GLES3.functional.texture.mipmap.2d.generate.a8_non_square_nicest
dEQP-GLES3.functional.texture.mipmap.2d.generate.l8_non_square_fastest
dEQP-GLES3.functional.texture.mipmap.2d.generate.l8_non_square_nicest
Fixes: 8991e646411 ("pvr: Add a Vulkan driver for Imagination Technologies...")
Signed-off-by: Iliyan Dinev <iliyan.dinev@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 1d0f23752c04ab3ca3e33a452e9ff581620c96a4)
-
09f096c8
by Luigi Santivetti at 2024-10-28T15:49:41+01:00
pvr: really free memory in subpass render init
Fixes: 10b6a0d567e ("pvr: Add support for generating render pass hw setup data.")
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 9651d73671817ca742398367b90fdb4dd9342020)
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0c158e67
by Frank Binns at 2024-10-28T15:49:42+01:00
pvr: ensure stencil clear value fits TA_STATE_ISPA.sref field
If the stencil clear value was larger than the maximum supported by the hardware
(255) then it would end up corrupting other fields in TA_STATE_ISPA. The Vulkan
1.0.266 spec says for VkClearDepthStencilValue:
"stencil is the clear value for the stencil aspect of the depth/stencil
attachment. It is a 32-bit integer value which is converted to the
attachment’s format by taking the appropriate number of LSBs."
As such, mask the clear value when packing TA_STATE_ISPA.
Fixes a number of GLES tests, including:
dEQP-GLES2.functional.depth_stencil_clear.*stencil_scissored*
dEQP-GLES2.functional.fragment_ops.stencil.*
dEQP-GLES3.functional.depth_stencil_clear.*stencil_scissored*
dEQP-GLES3.functional.fragment_ops.stencil.*
Fixes: 821c6b93423 ("pvr: Implement depth/stencil/depth+stencil attachment...")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31679>
(cherry picked from commit 1612255de678bc24d4886a734596ebf13ebd62b6)
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308c6b90
by Sviatoslav Peleshko at 2024-10-28T15:58:59+01:00
intel/brw/gfx9: Implement WaClearArfDependenciesBeforeEot
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11928
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31746>
(cherry picked from commit 2a4efe21c5e6dba353fc67c9ea58a52a913bb970)
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fc21133c
by Samuel Pitoiset at 2024-10-28T15:59:12+01:00
radv: fix initializing the HTILE buffer on transfer queue
When only of the depth/stencil aspects is used, RADV dispatches a
compute shader to initialize the HTILE buffer. But dispatching on SDMA
just hangs and the only way to initialize the HTILE buffer is to clear
both aspects using a memory fill operation.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31803>
(cherry picked from commit be81c8b8db16b82a0166cabfb72550000bf56b29)
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e25c4095
by Jordan Justen at 2024-10-28T15:59:13+01:00
intel/dev: Rework DEVINFO_HWCONFIG; add DEVINFO_HWCONFIG_KV macro
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit b4df9658f52180c5d115cc8cfce99b84dca83d7f)
-
f878028d
by Jordan Justen at 2024-10-28T15:59:14+01:00
intel/dev: Simplify DEVINFO_HWCONFIG_KV by adding should_apply_hwconfig_item()
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit a71702d34220f9ddb9b3b502247814d80591db3a)
-
3da8b46e
by Jordan Justen at 2024-10-28T15:59:15+01:00
intel/dev: Allow specifying a version when to always use hwconfig
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit 7b86da0ccdb5e56d8907a69c20d1492609c0aea3)
-
34aff5d2
by Jordan Justen at 2024-10-28T15:59:16+01:00
intel/dev: Use hwconfig for urb min/max entry values
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
(cherry picked from commit a4c5bfd34ca82a51a0e8fff529fb1d11af82b81f)
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4d166e1e
by Danylo Piliaiev at 2024-10-28T15:59:22+01:00
util/vma: Fix util_vma_heap_get_max_free_continuous_size calculation
It was based on misunderstanding of how holes are sorted, they are
sorted by address and not by size.
Fixes: df3ba95a2498447b037d0d8efbdf605be25ff8ff
("util/vma: Add function to get max continuous free size")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31722>
(cherry picked from commit 3209a97c5c391aee3bbd3aab25853d9c4a5daff9)
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09167a3e
by Adam Jackson at 2024-10-28T16:01:33+01:00
glx: Fix the GLX_EXT_swap_control_tear drawable attributes
GLX_SWAP_INTERVAL_EXT is always positive, GLX_LATE_SWAPS_TEAR_EXT is how
you tell whether the drawable is set to do it. This aligns us with the
spec and NVIDIA's GLX.
Closes: mesa/mesa#10193
Fixes: 5e9e4573835 glx/dri3: Implement GLX_EXT_swap_control_tear
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31655>
(cherry picked from commit 858eb189529ba904cea663168d64440338a16138)
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c282a404
by Yao Zi at 2024-10-28T16:01:33+01:00
panvk: Link with --build-id explicitly
panvk provides driver UUID generated from build id of the dynamic
library, but ld_args_build_id isn't used during linking. This leads to
broken drivers when building mesa with a toolchain defaults to
--no-build-id. Let's specify the flag explicitly.
Fixes: 8ea2931ed1f ("panvk: Generate proper device and driver UUIDs")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31654>
(cherry picked from commit 5ffc5ba8ef958b03a67b152f3a60e92fa1ff4480)
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62930741
by Valentine Burley at 2024-10-28T16:08:21+01:00
freedreno/devices: Unify magic_regs for A740 and A32
The only difference was RB_UNKNOWN_8E01 being set to 0x0 or 0x00000000.
Their raw_magic_regs however are different.
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31328>
(cherry picked from commit dde6acceb5470755a4b1607a29c5e503b974ec1f)
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655cdbd6
by Connor Abbott at 2024-10-28T16:08:21+01:00
ir3: Increase compute const size on a7xx
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30995>
(cherry picked from commit 5879eaac185ed1c167fd01aff9b91c7cbe43ab0a)
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d48aac9e
by Connor Abbott at 2024-10-28T16:08:48+01:00
freedreno: Add compute constlen quirk for X1-85
This GPU seems to have half the compute constlen of other a7xx GPUs,
because there are sporadic hangs in dEQP-VK.robustness.robustness2.* and
other tests unless we limit the constlen. This does *not* happen on
SM8550-HDK, so it does seem to be specific to the GPU in x1e laptops.
Fixes: b0d22461b94 ("freedreno: Enable the X1-85")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
(cherry picked from commit 3c8190e8b221a7996c6c79534e1c20929cf8d9ef)
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e94468c7
by Connor Abbott at 2024-10-28T16:13:43+01:00
tu: Don't invalidate CS state for 3D blits
We don't dirty the CS state, so if a 3D blit comes between binding a
compute pipeline and executing a dispatch then we won't re-emit the
pipeline and invalidating CS state causes immediates emitted via
CP_LOAD_STATE to disappear. Fixes
dEQP-VK.binding_model.descriptor_buffer.ycbcr_sampler.compute_comp.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
(cherry picked from commit 048afdd438902cb9f2b3477b15e3a40550e9465f)
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b7f428a3
by Georg Lehmann at 2024-10-28T16:13:44+01:00
radv: don't use v_mqsad_u32_u8 on gfx7
According to tests on hawaii, v_mqsad_u32_u8 always uses saturating accumulation
while v_msad_u8 truncates. GFX8+ can control this with the VOP3 clamp bit,
on older hardware that's not supported.
We want truncation for the NIR opcode.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12062
Fixes: c3c138b10f4 ("radv: optimize msad_4x8 to mqsad_4x8")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31809>
(cherry picked from commit 54fa55a3f779fd0b8f373b8d033ccfec1bf97df2)
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08378004
by Patrick Lerda at 2024-10-28T16:13:45+01:00
r600: fix spec ext_packed_depth_stencil getteximage
This very test was working until the commit 4da147a02b54
("mesa: remove fallback for GL_DEPTH_STENCIL"). Indeed this
commit lets the driver handles this path and this was
failing on evergreen r600.
The test was processed through r600_blit() which loads the
fragment shader util_make_fs_blit_zs(). This fragment shader
loads two textures the stencil and depth. The texture depth
was processed properly but the other texture was generating
incorrect values. This issue, which seems to be related to
the hardware configuration, disappears when the underlying
surface is allocated using a width multiple of 32.
This change was tested on cayman and palm with the normal test:
"piglit/bin/ext_packed_depth_stencil-getteximage -auto -fb" and
the test was modified to test all the relevant width and height
values. The gpu rv770 was not affected by this issue. Here is
the result:
spec/ext_packed_depth_stencil/getteximage: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31757>
(cherry picked from commit d19e2597cedf39439f7aa5dc3676509f96ab6c3b)
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1701837c
by Samuel Pitoiset at 2024-10-28T16:13:45+01:00
radv: fix emitting NGG culling state for ESO
It's possible to enable NGG culling with ESO if shaders are linked, or
if the VS doesn't need a prolog or if TES is used. This wasn't
supposed to be enabled but I think it worked just by luck because the
user SGPR value was probably zero and NGGC was disabled at draw time.
Found by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31829>
(cherry picked from commit 62efebfd7019bb5762ec5a9905281eaee3464e0c)
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5ad70039
by Rhys Perry at 2024-10-28T16:13:46+01:00
nir: fix shfr constant folding with zero src2
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 08903bbe89ae ("nir: add mqsad_4x8, shfr and nir_opt_mqsad")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31808>
(cherry picked from commit b2abd3bdba6af766967878398f25beb06a541b9e)
-
e3116409
by Rhys Perry at 2024-10-28T16:13:47+01:00
nir/algebraic: fix shfr optimization with zero src2
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 08903bbe89ae ("nir: add mqsad_4x8, shfr and nir_opt_mqsad")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31808>
(cherry picked from commit 8efc765a3d62a404f57fe4b0083e8ed2d3c5ecb7)
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10e69d78
by Jocelyn Falempe at 2024-10-28T16:13:48+01:00
loader: Fix typo in __DRI_IMAGE_FORMAT_XBGR16161616 definition
The X and A format are inverted by mistake.
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
(cherry picked from commit c6d7ab7c1f838b761b99376a56b09d793e1be63f)
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325ee594
by Jocelyn Falempe at 2024-10-28T16:16:02+01:00
gbm/dri: Use PIPE_FORMAT_* instead of using __DRI_IMAGE_*
__DRI_IMAGE formats are not well defined for big endian.
This patch has no functionnal change and prepare the work to better support
big endian.
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
(cherry picked from commit 3814dee11a141e8b74e61f0eb657d55c4bc0f909)
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a6f53410
by Jocelyn Falempe at 2024-10-28T16:16:33+01:00
gbm/dri: Fix color format for big endian.
Using wayland on s390x has all the colors wrong.
Mesa reports using GBM_FORMAT_XRGB8888 but inside the buffer, the
colors are in GBM_FORMAT_BGRX8888 order.
This patch fixes it for common formats, and also introduced BGRX8888
which is the default on big endian.
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31707>
(cherry picked from commit b24d4f0c8697d53ac035472590bcc2fd16c010ce)
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ed61c273
by Rob Clark at 2024-10-28T16:17:54+01:00
freedreno/ir3: Create UBO variables for driver-UBOs
Some nir passes, like lower_amul, expect to have varibles declared for
things that are accessed via load_ubo().
Fixes: 76e417ca5938 ("turnip,ir3/a750: Implement consts loading via preamble")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31611>
(cherry picked from commit e548f90edbc9bc59eb0b52a3b2345450943ccef2)
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c2cf1cc5
by Rob Clark at 2024-10-28T16:17:55+01:00
nir/lower_amul: Fix ASAN error
We shouldn't assume the bindings are sparse when we allocate an array
indexed on the binding. See, for example:
dEQP-GLES31.functional.program_interface_query.buffer_variable.random.55
Fixes: 2e833b16bca6 ("nir/lower_amul: Use num_ubos/ssbos instead of recomputing it.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31611>
(cherry picked from commit 7f63fa34da9847a6891207cf309bdaf76878bfc6)
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e7dc5d64
by Michel Dänzer at 2024-10-28T16:17:56+01:00
util/mesa-db: Make mesa_db_lock robust against signals
flock may be interrupted by a signal, in which case it returns with
EINTR error. In this case we need to retry until it returns success
or another error.
Fixes: 32211788d053 ("util/disk_cache: Add new mesa-db cache type")
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 13c44abaacb045d9b5ade829ea2842739ec67b08)
-
823397fe
by Dmitry Osipenko at 2024-10-28T16:17:57+01:00
util/mesa-db: Fix missing O_CLOEXEC
Use O_CLOEXEC flag for opened cache DB files to not leak cache FDs when
process forks.
Fixes: 32211788d053 ("util/disk_cache: Add new mesa-db cache type")
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 6a2f5cb5568131b3d7aa41dce76c1c95b9403d4c)
-
64bc227b
by Dmitry Osipenko at 2024-10-28T16:17:57+01:00
util/mesa-db-multipart: Open one cache part at a time
Open one cache DB part at a time for a multi-part cache to reduce number
of FDs used by the cache. Previously multi-part DB cache instance was
consuming 100 FDs, now it's 2 and cache files are opened when cache
is read or written instead of opening them at the init time.
Fixes: fd9f7b748e2e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 2a9378a0f97c9eddaba4dba32a24be699916f482)
-
1421945e
by Dmitry Osipenko at 2024-10-28T16:20:06+01:00
util/mesa-db: Open DB files during access time
Open DB files when DB is accessed and close them afterwards to reduce
number of FDs used by multi-part DB cache.
Fixes: fd9f7b748e2e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 7b40d32187bbdd0cd8da75d4c626ea87dd14b4fb)
-
ffbb9de5
by Dmitry Osipenko at 2024-10-28T16:20:07+01:00
util/mesa-db: Fix crash on compacting empty DB
Fix mesa_db_compact() segfaulting if compacted DB is empty. This crash
happens on writing cache entry that is bigger than DB's size limit and
when DB is empty, which can be triggered by setting DB size to a small
value.
Fixes: 32211788d053 ("util/disk_cache: Add new mesa-db cache type")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
(cherry picked from commit 5ec424c6bed98a69bf3e56d24af0393225077f44)
-
f0cb1eb4
by Ian Romanick at 2024-10-28T16:20:08+01:00
brw/copy: Don't remove instructions w/ conditional modifier
Fixes: 9e750f00c3b ("intel/brw: Make opt_copy_propagation_defs clean up its own trash")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
(cherry picked from commit 8329c04521884145bf15ec2cb4c85471fc8cdf61)
-
742e2ddb
by Rob Clark at 2024-10-28T16:20:09+01:00
freedreno/ir3: Do not propagate away a widening move
A narrowing move from const is just emulated CONSTANT_DEMOTION_ENABLE so
we can permit it. But not the inverse.
Cc: mesa-stable
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
(cherry picked from commit 63a5803433093df3965427d73b39d87a73cab365)
-
c99c1ba2
by Job Noorman at 2024-10-28T16:20:10+01:00
ir3: fix physical edges of predicated branches
The algorithm for adding extra physical edges works by finding edges
that jump over reconvergence points. Since predicated branches don't
introduce reconvergence points, we wouldn't add a physical edge from the
true block to the false block. However, this physical edge is still
needed as control flow does fall though here. This patch fixes this by
manually adding the physical edge so that we don't need to insert a
reconvergence point for it.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 39088571f08 ("ir3: add support for predication")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31733>
(cherry picked from commit 19c560da04d938d84b1fa5f2de2110aa2084d6c9)
-
6a593de6
by Samuel Pitoiset at 2024-10-28T16:20:11+01:00
radv: fix considering NGG culling for depth-only rendering
When the FS is unknown, this can happen with fast-link GPL or unlinked
ESO, rely on the number of VS/TES outputs which should be a good
approximation of the number of PS inputs.
This fixes a (huge?) performance regression from May 2023 because
for depth-only rendering, the FS is NULL and NGG culling wasn't
considered at all.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31830>
(cherry picked from commit 8e4d1965bd6514461c41ab4a7348345da1febbf1)
-
03aadd15
by Daniel Schürmann at 2024-10-28T16:20:12+01:00
aco: Respect addressible SGPR limit in VS prologs
On Tonga, the effective SGPR limit is 96, including VCC.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31859>
(cherry picked from commit 10958d04d5767d733ab7ef20fcc261c8a7c92b59)
-
056e7c79
by Eric Engestrom at 2024-10-30T17:20:10+01:00
.pick_status.json: Update to c245609b641ad914a931ad2b3fd930ed8d065e07
-
859bf9a4
by YaoBing Xiao at 2024-10-30T18:56:40+01:00
vulkan/x11: use xcb_connection_has_error to check for failue
xcb_connectxx() always returns a non-NULL pointer to a
xcb_connection_t, even on failure.
cc: mesa-stable
Signed-off-by: YaoBing Xiao <xiaoyaobing@uniontech.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31812>
(cherry picked from commit b63dfcc1722b2da4d360f8cbcce32530b90303be)
-
4da95485
by Lu Yao at 2024-10-30T18:56:40+01:00
ac/radeonsi: compute htile for tile mode RADEON_SURF_MODE_1D on GFX6-8
Computing 'htile_size/meta_size' is allowed for RADEON_SURF_MODE_1D when
RADEON_SURF_TC_COMPATIBLE_HTILE isn't set.
Lacking of computing causes performance degradation in some scenarios.
Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE")
Signed-off-by: Lu Yao <yaolu@kylinos.cn>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31617>
(cherry picked from commit 0442a6c29259f5e40208db33fe79833d1dff289a)
-
274f4296
by Samuel Pitoiset at 2024-10-30T18:56:40+01:00
radv: fix wrong index in radv_skip_graphics_pipeline_compile()
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12089
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31901>
(cherry picked from commit fc0545e6a70c6ca310ef9f2327fb649f0d495f4a)
-
2e61c87e
by Alyssa Rosenzweig at 2024-10-30T18:56:40+01:00
asahi: fix no16 flag
regressed when shuffling code for hk.
Fixes: 3cb8c1de819 ("asahi: get debug in common")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31908>
(cherry picked from commit 773dd89fded1341fc89b8fae8dbf093e2e453827)
-
68bf689e
by Eric Engestrom at 2024-10-30T19:12:25+01:00
docs: add release notes for 24.2.6
-
c6b35802
by Eric Engestrom at 2024-10-30T19:12:27+01:00
VERSION: bump for 24.2.6
-
f07479eb
by Eric Engestrom at 2024-10-30T19:32:46+01:00
docs: add sha sum for 24.2.6
-
e33b7009
by Eric Engestrom at 2024-11-02T11:26:20+01:00
.pick_status.json: Update to ab1479ae6a845d2c7beeb0fed6e2153cc2b16c5e
-
f583d6f7
by Connor Abbott at 2024-11-02T18:17:15+01:00
ir3: Fix detection of nontrivial continues
We may still need to insert a continue block even if there is only one
backedge, in a situation like:
for (...) {
if (...) continue;
foo();
break;
}
We want foo() to be executed before reconverging. This is important for
the BVH encoding kernel, which launches an invocation for each node in
the tree and does a preorder traversal:
while (true) {
if (!ready[node]) continue;
encode();
for (child node)
ready[child] = true;
break;
}
For the first few nodes, which will be in the same wave, we need
encode() for the root node to be called first, then its children spin
until ready, then the children call encode(), and so on. This can only
work if the children that aren't ready yet are parked while the parent
executes encode(), which requires the continue block.
This is also required because divergence analysis will assume that
uniform values written before the continue are still uniform after it,
which isn't the case now and causes an RA validation failure with Godot.
Fixes: 0fa93fb6626 ("ir3: Fix convergence behavior for loops with continues")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31905>
(cherry picked from commit d3533716f95d77e35103562b8edee864ffc16a18)
-
9d0da876
by Timur Kristóf at 2024-11-02T18:17:16+01:00
radv: Flush L2 cache for non-L2-coherent images in EndCommandBuffer.
This fixes a CTS hang on Hawaii.
We previously only did a CB/DB flush,
but that doesn't include a L2 cache flush.
Also fix the comment that said this is for GFX9+.
Fixes: 7c62f6fa01d7c0d9d7eabec1c545950af20d0c92
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31906>
(cherry picked from commit 96b95c84279e3bb8c0dcebfb0e811bf2b8633fc6)
-
d480ca55
by Rob Clark at 2024-11-02T18:17:17+01:00
util/primconvert: Avoid OoB with improbable draws
Detect when the temporary index buffer cannot be generated due to too
large primitive count, and simply drop the draw on the floor.
Fixes a webgl reachable asan/crash.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12092
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31914>
(cherry picked from commit 98ff271c5a3643a1cbbaf070896cf6a22a45c2c8)
-
6531617c
by Lionel Landwerlin at 2024-11-02T18:17:18+01:00
anv: avoid L3 fabric flush in pipeline barriers
This bit is not needed for barriers and appears to trigger a
performance regression. So leave it for just for AUX-TT
flushing/invalidation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e3814dee1a ("anv: add plumbing/support for L3 fabric flush")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12090
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31915>
(cherry picked from commit cb224370b6fcda7f73be99d94c98096569b2e2ba)
-
904c9d64
by Paulo Zanoni at 2024-11-02T18:17:19+01:00
brw: add a NOP in between WHILE instructions on LNL
This is a workaround that is still in progress, see HSD 22020521218.
If we don't have these NOPs we may see rendering corruption or even
GPU hangs.
While we still don't fully understand the issue from the hardware
point of view, let's have this workaround so we can pass CTS and move
things forward. If we need to change this later, we can. Besides, the
impact is minimal. Shaderdb/fossilize report no changes for this
patch.
On our Blackops trace, the lack of this patch causes corruption in fog
rendering (rectangles where fog was supposed to be shown don't show
the fog).
On dEQP-VK.graphicsfuzz.cov-array-copies-loops-with-limiters, without
this patch we get a GPU hang.
Backport-to: 24.2
Testcase: dEQP-VK.graphicsfuzz.cov-array-copies-loops-with-limiters
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11813
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31331>
(cherry picked from commit 5ca883505e29870c7ae8929049397b9ef85666e9)
-
85cfa40d
by David Rosca at 2024-11-02T18:17:21+01:00
radeonsi/vcn: Enable VCN4 AV1 encode WA
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31889>
(cherry picked from commit c9ade8c3b53fe1ae9467d19b43bc605ea4fba6de)
-
092a85a7
by Samuel Pitoiset at 2024-11-02T18:17:21+01:00
radv: add missing L2 non-coherent image case for mipmaps with DCC/HTILE on GFX11
According to PAL, an image with DCC/HTILE and mipmaps isn't coherent
with L2 when the mip level is in the metadata mip-tail region.
This fix isn't super optimal because the driver should rely on the
subresource range to determine if the mip level is in the mip-tail,
but it's easier to backport. Upcoming commits will optimize that.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11939
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31920>
(cherry picked from commit b23cc8c1d39c419b025870159083f444eca7c465)
-
2db348fd
by Mike Blumenkrantz at 2024-11-02T18:17:22+01:00
zink: stop leaking precompiled generated tcs
this may have been created during precompile when using shader objects
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27705>
(cherry picked from commit 01608a4067b9919ebef77e65a75e1b7a56dc75c3)
-
782225e1
by Patrick Lerda at 2024-11-02T18:17:23+01:00
r600: fix sfn_nir_legalize_image_load_store cubearray behavior
This change fixes the calculation of the number of cubemap
images which requires a 6x multiplier.
This commit is inspired from nir_lower_robust_access and fixes
at least the following tests on cayman:
spec/arb_shader_image_load_store/layer/imagecubearray/layered binding test: fail pass
spec/arb_shader_image_load_store/max-size/imagecubearray max size test/8x8x2046x1: fail pass
Fixes: 27f515777741 ("r600/sfn: Add lowering pass to legalize image access")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31626>
(cherry picked from commit 5c63d7a916d2396eca25c0796431ba631ad3a2e8)
-
575259eb
by Rob Clark at 2024-11-02T18:41:25+01:00
freedreno: Fix tile-per-pipe debug overrides
Fixes: 0f3c12c0ab05 ("freedreno: add env var to override tiles-per-pipe")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31857>
(cherry picked from commit 42446052d40a3f9ae8780cb45c88a500b79a0636)
-
e143fabe
by Rob Clark at 2024-11-02T20:28:35+01:00
freedreno/a6xx: Stop exposing MSAA image load/store harder
Fixes KHR-GL46.multi_bind.dispatch_bind_image_textures which decides
max_image_samples==1 means that MSAA image load/store is supported.
Switch the condition to > 0, which matches what zink does.
Fixes: e277b1318253 ("freedreno: Stop exposing MSAA image load/store on desktop GL.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31857>
(cherry picked from commit f8e7c0e2a2f0e65837abc513f4d1ce30f67a9449)
-
11fbef63
by Timo Aaltonen at 2024-11-05T09:47:39+02:00
Merge branch 'upstream-unstable' into debian-unstable
-
3282dbf3
by Timo Aaltonen at 2024-11-05T09:48:06+02:00
version bump
-
9e6d6ec7
by Timo Aaltonen at 2024-11-05T09:49:17+02:00
fix-armhf-build.diff: Dropped, upstream.
-
3eb0c40b
by Timo Aaltonen at 2024-11-05T10:10:35+02:00
releasing package mesa version 24.2.6-1
-
19d06c73
by Eric Engestrom at 2024-11-07T18:37:51+01:00
.pick_status.json: Update to fe50011ddb35077c0d4cc2b31d56f8dd1376d5a2
-
34ed9f05
by Lucas Fryzek at 2024-11-07T18:38:00+01:00
lp: Only close udmabuf handle if its valid
Also change ifdef's from just `HAVE_LIBDRM` to check for both LIBDRM
and for UDMABUF HEADER. preventing unbalanced guards preventing part of
the code from being included if you just have LIBDRM or just have the
udmabuf headers.
Fixes: 4cfaf10c ("llvmpipe: Only use udmabuf with libdrm")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31877>
(cherry picked from commit 159fb9691d792594b91e0fbc4c7823e1a191620d)
-
c19d4af9
by Marek Olšák at 2024-11-07T18:38:01+01:00
radeonsi/gfx11: fix Z corruption for Blender
The corruption only happens with non-TC-compatible HTILE, so always use
TC-compatible HTILE.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11891
Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31910>
(cherry picked from commit 047532b1e1df6bb3e0c6ca6b81fbfbf3fd9d502c)
-
ee5ae8c7
by Marek Olšák at 2024-11-07T18:38:02+01:00
radeonsi/gfx12: fix AMD_DEBUG=nodcc not working
surface->modifier is always 0 here. We should use the parameter instead.
Fixes: 3d05d86d88e (radeonsi/gfx12: add DCC)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31910>
(cherry picked from commit 5d09374ffef4956b9504f4573b127fbbede8420c)
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4962a83c
by itycodes at 2024-11-07T18:38:03+01:00
intel: Fix a typo in intel_device_info.c:has_get_tiling
The structs are of equal size and both ioctls were added at the same
time, so the functionality is equivalent, but it's nonetheless the
incorrect type being passed.
Signed-off-by: tranquillitycodes@proton.me
Fixes: 762e601f776e7d692f49c328e526e6e2c3b14345
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31974>
(cherry picked from commit 10c92cbd394b0299de8384f42abcd3072c7a3908)
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d8e49ead
by Samuel Pitoiset at 2024-11-07T18:38:04+01:00
radv: cleanup tools related resources when destroying logical device
This was missing.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31986>
(cherry picked from commit 64774f9c19a1fe0a4c1ec7a455f3d8be0de8ebc6)
-
6b3af035
by Lionel Landwerlin at 2024-11-07T18:38:06+01:00
vulkan/runtime: fix allocation failure handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 93d0c66b27 ("vulkan/pipeline_cache: Add helpers for storing NIR in the cache")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31982>
(cherry picked from commit 2cadab5dcf3bdff4e52395eac6d04daba7ccdda0)
-
fbb3dbdf
by Lionel Landwerlin at 2024-11-07T18:38:07+01:00
anv: fix even set/reset on blitter engine
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31928>
(cherry picked from commit b3f487bd0deeda113290b558443dbd25a245def4)
-
fe115789
by Lionel Landwerlin at 2024-11-07T18:38:14+01:00
anv: add texture cache inval after binding pool update
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31928>
(cherry picked from commit f9e76e8ca67d2f1d16d0df6d8576eed2c075f96f)
-
bb0502e5
by Rhys Perry at 2024-11-07T18:38:29+01:00
aco: don't byte align global VMEM loads if it might be unsafe
Using the byte align path can be unsafe even when 12 byte loads are
supported.
fossil-db (navi21):
Totals from 185 (0.23% of 79395) affected shaders:
Instrs: 391501 -> 391575 (+0.02%); split: -0.03%, +0.05%
CodeSize: 2147336 -> 2147672 (+0.02%); split: -0.03%, +0.05%
Latency: 3762613 -> 3860941 (+2.61%); split: -0.01%, +2.62%
InvThroughput: 871429 -> 888013 (+1.90%); split: -0.08%, +1.98%
VClause: 9712 -> 10210 (+5.13%)
Copies: 53775 -> 53010 (-1.42%); split: -1.46%, +0.04%
VALU: 254009 -> 252146 (-0.73%)
SALU: 56698 -> 56699 (+0.00%); split: -0.00%, +0.00%
VMEM: 18503 -> 19601 (+5.93%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 391bf3ea30ec ("aco: don't expand smem/mubuf global loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31807>
(cherry picked from commit b318fe47e9ce315f9dd58ae65334ef6a0727e71f)
-
d73b751b
by Christian Gmeiner at 2024-11-07T18:38:32+01:00
etnaviv: Fix incorrect pipe_nn creation
When etna_screen_create(..) is called with gpu != NULL and npu == NULL,
screen->pipe_nn is incorrectly set up. This leads to an unintended
stream configuration for compute-only contexts, as determined by
pipe = (compute_only && screen->pipe_nn) ? screen->pipe_nn : screen->pipe;
To address this, extend the gpu != npu condition by adding a check for
npu != NULL to ensure pipe_nn is only initialized when both gpu and npu
are provided.
Fixes: a4653587cc4 ("etnaviv: Add a separate NPU pipe")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32025>
(cherry picked from commit f4e8849d79de2cdc6c91f877cb223ed375d6a50c)
-
a47d11b7
by Benjamin Herrenschmidt at 2024-11-07T18:38:35+01:00
dril: Fixup order of pixel formats in drilConfigs
Having the RGB* formats before the BGR* formats in the table causes
problems where under some circumstances, some applications end up
with the wrong colors.
The repro case for me is: Xvnc + mutter + chromium
There was an existing comment in dri_fill_in_modes() which explained
the problem. This was lost when dril_target.c was created.
Fixes: ec7afd2c24c ("dril: rework config creation")
Fixes: 3de62b2f9a6 ("gallium/dril: Compatibility stub for the legacy DRI loader interface")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31950>
(cherry picked from commit e1098310da6b9fa7e66dc3fe382ae08d88fd1352)
-
7e011814
by Eric Engestrom at 2024-11-07T18:38:37+01:00
meson: add dependencies needed by wsi_common_x11.c even on non-drm platforms
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11907
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32012>
(cherry picked from commit 06cca41889eedb8c1c2beef2d2c924907910ecfb)
-
afe62e96
by Eric Engestrom at 2024-11-11T11:12:52+01:00
.pick_status.json: Update to 4d09cd7fa590cbd52d8772d5a251fab8b0874ab7
-
3a7a0455
by Karol Herbst at 2024-11-11T11:12:55+01:00
nv/codegen: Do not use a zero immediate for tex instructions
They aren't always legal for tex instructions, specifically for TXQ when
an actual source is needed.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11999
Fixes: 85a31fa1fc9 ("nv50/ir/nir: fix txq emission on MS textures")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32043>
(cherry picked from commit 47a1565c3d0599c8748e6c97c46b9e18655d3201)
-
d7db9b47
by Karol Herbst at 2024-11-11T11:12:56+01:00
nvc0: return NULL instead of asserting in nvc0_resource_from_user_memory
Fixes: 212f1ab40ea ("nvc0: support PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY")
Acked-by: David Heidelberg <david@ixit.cz>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27783>
(cherry picked from commit 277925471e47916fb88b39edc5d66d3cb5ddb8b9)
-
a5c46206
by Ian Romanick at 2024-11-11T11:12:57+01:00
brw/copy: Don't copy propagate through smaller entry dest size
Copy propagation would incorrectly occur in this code
mov(16) v4+2.0:UW, u0<0>:UW NoMask
...
mov(8) v6+2.0:UD, v4+2.0:UD NoMask group0
to create
mov(16) v4+2.0:UW, u0<0>:UW NoMask
...
mov(8) v6+2.0:UD, u0<0>:UD NoMask group0
This has different behavior. I think I just made a mistake when I
changed this condition in e3f502e0074.
It seems like this condition could be relaxed to cover cases like (note
the change of destination stride)
mov(16) v4+2.0<2>:UW, u0<0>:UW NoMask
...
mov(8) v6+2.0:UD, v4+2.0:UD NoMask group0
I'm not sure it's worth it.
No shader-db or fossil-db changes on any Intel platform. Even the code
for the test case mentioned in the original commit did not change.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: e3f502e0074 ("intel/fs: Allow copy propagation between MOVs of mixed sizes")
Closes: #12116
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32041>
(cherry picked from commit 80a5d158ae7d675e2cc62c78970a84abc1c85cfe)
-
5b2b92a5
by Ian Romanick at 2024-11-11T11:12:58+01:00
brw/cse: Don't eliminate instructions that write flags
With other changes in my tree, I observed this code from
dEQP-VK.subgroups.vote.compute.subgroupallequal_float have the second
cmp.z removed.
undef(8) %69:UD
cmp.z.f0.0(8) %69:F, %37:F, %57+0.0<0>:F
mov(1) v58+0.0:D, 0d NoMask group0
(+f0.0) mov(1) v58+0.0:D, -1d NoMask group0
cmp.nz.f0.0(8) null:D, v58+0.0<0>:D, 0d
...
undef(8) %72:UD
cmp.z.f0.0(8) %72:F, %37:F, %57+0.0<0>:F
mov(1) v63+0.0:D, 0d NoMask group0
(+f0.0) mov(1) v63+0.0:D, -1d NoMask group0
This was also fixed by running dead-code elimination before CSE. That
seems more like avoiding the problem than fixing it, though.
I believe this affects shader-db results because leaving the second
CMP in the shader can give more opportunities for cmod propagation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: 234c45c929e ("intel/brw: Write a new global CSE pass that works on defs")
shader-db:
All Intel platforms had similar results. (Lunar Lake shown)
total cycles in shared programs: 922097690 -> 922260862 (0.02%)
cycles in affected programs: 3178926 -> 3342098 (5.13%)
helped: 130
HURT: 88
helped stats (abs) min: 2 max: 2194 x̄: 296.71 x̃: 16
helped stats (rel) min: <.01% max: 16.56% x̄: 1.86% x̃: 0.18%
HURT stats (abs) min: 4 max: 11992 x̄: 2292.55 x̃: 47
HURT stats (rel) min: 0.04% max: 57.32% x̄: 11.82% x̃: 0.61%
95% mean confidence interval for cycles value: 320.36 1176.63
95% mean confidence interval for cycles %-change: 1.59% 5.73%
Cycles are HURT.
LOST: 2
GAINED: 1
fossil-db:
Lunar Lake, Meteor Lake, Tiger Lake had similar results. (Lunar Lake shown)
Totals:
Instrs: 142022960 -> 142022928 (-0.00%); split: -0.00%, +0.00%
Cycle count: 21995242782 -> 21995384040 (+0.00%); split: -0.00%, +0.00%
Max live registers: 48013385 -> 48013343 (-0.00%)
Totals from 507 (0.09% of 551441) affected shaders:
Instrs: 886191 -> 886159 (-0.00%); split: -0.01%, +0.01%
Cycle count: 69302492 -> 69443750 (+0.20%); split: -0.66%, +0.86%
Max live registers: 94413 -> 94371 (-0.04%)
DG2
Totals:
Instrs: 152856370 -> 152856093 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17237159885 -> 17236804052 (-0.00%); split: -0.00%, +0.00%
Fill count: 150673 -> 150631 (-0.03%)
Max live registers: 31871520 -> 31871476 (-0.00%)
Totals from 506 (0.08% of 633197) affected shaders:
Instrs: 831795 -> 831518 (-0.03%); split: -0.04%, +0.01%
Cycle count: 55578509 -> 55222676 (-0.64%); split: -1.38%, +0.74%
Fill count: 2779 -> 2737 (-1.51%)
Max live registers: 51383 -> 51339 (-0.09%)
Ice Lake and Skylake had similar results. (Ice Lake shown)
Totals:
Instrs: 152017826 -> 152017793 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15180773451 -> 15180761166 (-0.00%); split: -0.00%, +0.00%
Fill count: 106610 -> 106614 (+0.00%)
Max live registers: 32195006 -> 32194966 (-0.00%)
Totals from 411 (0.06% of 637268) affected shaders:
Instrs: 705935 -> 705902 (-0.00%); split: -0.01%, +0.01%
Cycle count: 47830019 -> 47817734 (-0.03%); split: -0.05%, +0.02%
Fill count: 2865 -> 2869 (+0.14%)
Max live registers: 42883 -> 42843 (-0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32041>
(cherry picked from commit 9aba731d0354d456a8aab53e3a1ceef94a0d7f99)
-
07cea4ca
by Eric Engestrom at 2024-11-11T11:13:21+01:00
.pick_status.json: Mark 5cd054ebe5512aeac80e08528d8363335d0aeeb8 as denominated
-
63f2ab67
by Eric Engestrom at 2024-11-13T12:38:50+01:00
.pick_status.json: Update to b32d0d4b4588bf207a9b85b03f2f1c7bb9e72d57
-
aa81c109
by Matt Turner at 2024-11-13T12:38:53+01:00
anv: Align anv_descriptor_pool::host_mem
Otherwise anv_descriptor_set is accessed through an unaligned pointer,
which is undefined behavior in C.
```
anv_descriptor_set.c:1620:17: runtime error: member access within misaligned address 0x61900002c2b5
for type 'struct anv_descriptor_set', which requires 8 byte alignment 0x61900002c2b5
```
Fixes: 2570a58bcdf ("anv: Implement descriptor pools")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32070>
(cherry picked from commit a2c4a34303cd70e1df3e822bec53312b96e94293)
-
c4ca3d53
by Job Noorman at 2024-11-13T12:38:53+01:00
ir3/ra: prevent moving source intervals for shared collects
Non-trivial collects (i.e., ones that will introduce moves because the
sources don't line-up with the destination) may cause source intervals
to get implicitly moved when they are inserted as children of the
destination interval. Since we don't support moving intervals in shared
RA, this may cause illegal register allocations. Prevent this by
creating a new top-level interval for the destination so that the source
intervals will be left alone.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fa22b0901af ("ir3/ra: Add specialized shared register RA/spilling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31978>
(cherry picked from commit b36a7ce0f1988dd93ec31059cd6ab0ccec32ee91)
-
ed2af400
by Karmjit Mahil at 2024-11-13T12:38:53+01:00
tu: Fix push_set host memory leak on command buffer reset
Addresses:
```
Direct leak of 192 byte(s) in 1 object(s) allocated from:
#0 0x7fbe5e4230 in __interceptor_realloc
../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:164
#1 0x7fbd008bf4 in vk_default_realloc
../src/vulkan/util/vk_alloc.c:37
#2 0x7fbbabb2fc in vk_realloc ../src/vulkan/util/vk_alloc.h:70
#3 0x7fbbaead38 in tu_push_descriptor_set_update_layout
../src/freedreno/vulkan/tu_cmd_buffer.cc:3173
#4 0x7fbbaeb0b4 in tu_push_descriptor_set
../src/freedreno/vulkan/tu_cmd_buffer.cc:3203
#5 0x7fbbaeb500 in tu_CmdPushDescriptorSet2KHR(VkCommandBuffer_T*,
VkPushDescriptorSetInfoKHR const*)
../src/freedreno/vulkan/tu_cmd_buffer.cc:3235
#6 0x7fbbe35c80 in vk_common_CmdPushDescriptorSetKHR
../src/vulkan/runtime/vk_command_buffer.c:300
```
seen in:
dEQP-VK.binding_model.shader_access.secondary_cmd_buf.bind.with_push.sampler_mutable.tess_eval.multiple_discontiguous_descriptors.1d_array
Fixes: 03294e1dd1c ("turnip: Keep a host copy of push descriptor sets.")
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32057>
(cherry picked from commit 53c2d5e426d8a5b919ea3c64bad9e46b354b2fc9)
-
969b7ba5
by Karmjit Mahil at 2024-11-13T12:38:53+01:00
tu: Fix potential alloc of 0 size
We can end up calling vk_multialloc_alloc with 0 size when
`attachment_count` is 0 and `clearValueCount` is 0.
Addressed:
```
Direct leak of 1 byte(s) in 1 object(s) allocated from:
#0 0x7faf033ee0 in __interceptor_malloc
../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:145
#1 0x7fada5cc10 in vk_default_alloc ../src/vulkan/util/vk_alloc.c:26
#2 0x7fac50b270 in vk_alloc ../src/vulkan/util/vk_alloc.h:48
#3 0x7fac555040 in vk_multialloc_alloc
../src/vulkan/util/vk_alloc.h:234
#4 0x7fac555040 in void
tu_CmdBeginRenderPass2<(chip)7>(VkCommandBuffer_T*,
VkRenderPassBeginInfo const*, VkSubpassBeginInfo const*)
../src/freedreno/vulkan/tu_cmd_buffer.cc:4634
#5 0x7fac900760 in vk_common_CmdBeginRenderPass
../src/vulkan/runtime/vk_render_pass.c:261
```
seen in:
dEQP-VK.robustness.robustness2.bind.notemplate.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.len_252.samples_1.1d.frag
Fixes: 4cfd021e3f7 ("turnip: Save the renderpass's clear values in the cmdbuf state.")
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32057>
(cherry picked from commit c923eff742b83cc475d02ad57c538754db991c06)
-
11843f8a
by Karmjit Mahil at 2024-11-13T12:38:53+01:00
nir: Fix `no_lower_set` leak on early return
Addresses:
```
Indirect leak of 256 byte(s) in 2 object(s) allocated from:
#0 0x7faaf53ee0 in __interceptor_malloc
../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:145
#1 0x7fa8cfe900 in ralloc_size ../src/util/ralloc.c:118
#2 0x7fa8cfeb20 in rzalloc_size ../src/util/ralloc.c:152
#3 0x7fa8cff004 in rzalloc_array_size ../src/util/ralloc.c:232
#4 0x7fa8d06a84 in _mesa_set_init ../src/util/set.c:133
#5 0x7fa8d06bcc in _mesa_set_create ../src/util/set.c:152
#6 0x7fa8d0939c in _mesa_pointer_set_create ../src/util/set.c:613
#7 0x7fa95e5790 in nir_lower_mediump_vars
../src/compiler/nir/nir_lower_mediump.c:574
#8 0x7fa862c1c8 in tu_spirv_to_nir(tu_device*, void*, unsigned long,
VkPipelineShaderStageCreateInfo const*, tu_shader_key const*,
pipe_shader_type) ../src/freedreno/vulkan/tu_shader.cc:116
#9 0x7fa8646f24 in tu_compile_shaders(tu_device*, unsigned long,
VkPipelineShaderStageCreateInfo const**, nir_shader**,
tu_shader_key const*, tu_pipeline_layout*, unsigned char const*,
tu_shader**, char**, void*, nir_shader**, VkPipelineCreationFeedback*)
../src/freedreno/vulkan/tu_shader.cc:2741
#10 0x7fa85a16a4 in tu_pipeline_builder_compile_shaders
../src/freedreno/vulkan/tu_pipeline.cc:1887
#11 0x7fa85eb844 in tu_pipeline_builder_build<(chip)7>
../src/freedreno/vulkan/tu_pipeline.cc:3923
#12 0x7fa85e6bd8 in tu_graphics_pipeline_create<(chip)7>
../src/freedreno/vulkan/tu_pipeline.cc:4203
#13 0x7fa85c2588 in VkResult
tu_CreateGraphicsPipelines<(chip)7>(VkDevice_T*,
VkPipelineCache_T*, unsigned int, VkGraphicsPipelineCreateInfo const*,
VkAllocationCallbacks const*, VkPipeline_T**)
../src/freedreno/vulkan/tu_pipeline.cc:4234
```
seen in:
dEQP-VK.binding_model.mutable_descriptor.single.switches.uniform_texel_buffer_storage_image.update_write.no_source.no_source.pool_expand_types.pre_update.no_array.vert
Fixes: 7e986e5f045 ("nir/lower_mediump_vars: Don't lower mediump shared vars with atomic access.")
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32057>
(cherry picked from commit 2a7df331af65216e0229fe6481c1eca70221b225)
-
138bced8
by Jose Maria Casanova Crespo at 2024-11-13T12:38:53+01:00
v3d: Enable Early-Z with discards when depth updates are disabled
The Early-Z optimization is disabled when there is a discard
instruction in the shader used in the draw call.
But if discard is the only reason to disable Early-Z, and at
draw call time the updates in the draw call are disabled we
can enable Early-Z using a shader variant.
If there are occlussion queries active we also need to disable
Early-z optimization.
So this patch enables Early-Z in this scenario.
The performance improvement is significant when running gfxbench
benchmark showing an average improvement of 11.15%
fps_avg helped: gl_gfxbench_aztec_high.trace: 3.13 -> 3.73 (19.13%)
fps_avg helped: gl_gfxbench_aztec.trace: 4.82 -> 5.68 (17.88%)
fps_avg helped: gl_gfxbench_manhattan31.trace: 5.10 -> 6.00 (17.59%)
fps_avg helped: gl_gfxbench_manhattan.trace: 7.24 -> 8.36 (15.52%)
fps_avg helped: gl_gfxbench_trex.trace: 19.25 -> 20.17 ( 4.81%)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32028>
(cherry picked from commit 5b951bcdd7faf1cbfc189a953c33334378ada3df)
-
fa0b36b9
by M Henning at 2024-11-13T12:38:53+01:00
nvk/cmd_buffer: Pass count to set_root_array
Previously, we were passing the end index which was incorrect.
Also, improve the macros so that they can take an _expression_ for
the count.
Fixes: b2d85ca36f95 ("nvk: Use helper macros for accessing root descriptors")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32086>
(cherry picked from commit 64f17c1391860ca2d0898dd5076514c22b1cbdfa)
-
d3cbd92d
by M Henning at 2024-11-13T12:38:53+01:00
nvk: Fix invalidation of NVK_CBUF_TYPE_DYNAMIC_UBO
Because dyn_start and dyn_end are indices into
nvk_root_descriptor_table->dynamic_buffers, we would need to offset
cbuf->dynamic_idx by
nvk_root_descriptor_table->set_dynamic_buffer_start[cbuf->desc_set]
in order to do those comparisons correctly.
We could do that, but it's simpler and no less precise to sinply
re-use the same comparison that we do in the other cases here.
This fixes a rendering artifact in Baldur's Gate 3 (Vulkan), which
regressed with the commit listed below.
Fixes: 091a945b57 ("nvk: Be much more conservative about rebinding cbufs")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32086>
(cherry picked from commit dc12c78235bb5334dd9c2d3c91ffc4c7990e1c2b)
-
c2c3d6ab
by Tomeu Vizoso at 2024-11-13T12:38:53+01:00
etnaviv/ml: Fix includes
etnaviv_ml.h uses dynarray, but the u_inlines.h header is needed by
some of the files that include it.
Fixes: d6473ce28ee0 ("etnaviv: Use NN cores to accelerate convolutions")
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
(cherry picked from commit 70bff0c971aa41d9eacf813a771a73918b0146aa)
-
cc372f41
by Lionel Landwerlin at 2024-11-13T12:38:54+01:00
anv: update shader descriptor resource limits
Some limits got stuck to the old binding table limits. Those don't
apply anymore since EXT_descriptor_indexing was implemented.
Fixes: 6e230d7607 ("anv: Implement VK_EXT_descriptor_indexing")
Fixes: 96c33fb027 ("anv: enable direct descriptors on platforms with extended bindless offset")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31999>
(cherry picked from commit d6acb56f11edfdccfcc477ded897feb25383a31a)
-
2f6f1088
by Eric Engestrom at 2024-11-13T12:41:03+01:00
ci: raise priority of release manager pipelines
KernelCI jobs have priority 44 and are very long-running jobs (and
there might be an issue with the KernelCI that makes it create hundreds
of jobs, @sergi is looking into that).
While bumping to 45+ would be enough to allow Mesa release staging
pipelines to run despite the KernelCI, during the CI meeting with @sergi
and @mupuf it was determined that the Mesa releases are an important
enough operation to warrant being a higher priority than user forks
pipelines, so priority 70 was picked (still under the 75 of Marge
pipelines).
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32093>
(cherry picked from commit 50f9bec3ce4424afb508be81ef0fe31e2b8b1fc2)
-
6f52ae4c
by Eric Engestrom at 2024-11-13T15:30:48+01:00
lima/ci: marking two failures as known to make the ci useful again
-
46f84327
by Eric Engestrom at 2024-11-13T16:28:52+01:00
docs: add release notes for 24.2.7
-
39008282
by Eric Engestrom at 2024-11-13T16:28:52+01:00
VERSION: bump for 24.2.7
-
2e66d63c
by Timo Aaltonen at 2024-11-14T09:32:40+02:00
Merge branch 'upstream-unstable' into debian-unstable
-
cc4be595
by Timo Aaltonen at 2024-11-14T09:33:16+02:00
version bump
-
1bc3e88e
by Timo Aaltonen at 2024-11-14T14:08:44+02:00
releasing package mesa version 24.2.7-1
-
3b03ca6b
by Dylan Aïssi at 2024-11-23T10:13:11+01:00
Merge tag 'debian/24.2.7-1' into debian/bookworm-backports
tagging package mesa version debian/24.2.7-1
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3f117e04
by Dylan Aïssi at 2024-11-23T10:13:44+01:00
Bump debian/changelog
Signed-off-by: Dylan Aïssi <dylan.aissi@collabora.com>