-
c11a9317
by Dylan Baker at 2024-11-14T09:31:30-08:00
.pick_status.json: Update to b8d253b30c0a8c1878f2429f0a4df0a068bbf0aa
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
439879ab
by Timothy Arceri at 2024-11-14T09:31:31-08:00
glsl/nir: fix function cloning at link time
As per the code comment added in this commit the nir produced from
glsl to nir doesn't always keep function declarations before the
code that calls them e.g. calls from within other function
implementations. The change in this commit works around this problem by
first cloning all function declarations in a first pass, then cloning
the implementations in a second pass once we have filled the remap
table.
Fixes: cbfc225e2bda ("glsl: switch to a full nir based linker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12115
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 59b25492795eb415b8d894b2238cb6bcc6b17169)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
41af3ea1
by David Heidelberg at 2024-11-14T09:31:32-08:00
util: Drop 3Dnow optimisation leftovers
Fixes: a3218e65d1e5 ("mesa: remove long dead 3Dnow optimisation") # 24.3
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
(cherry picked from commit ae85e6920c18c6f850c22e183f2f740c45b69ad3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
f6653b1f
by David Heidelberg at 2024-11-14T09:31:33-08:00
util: Remove MMX/MMXext detection code
Currently pointless, Pentium II or Celeron and later has SSE.
Cc: mesa-stable # 24.3
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
(cherry picked from commit a78c2bf2a41252045f7bb695d02d75fcd73a3957)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
cbb58f26
by David Heidelberg at 2024-11-14T09:31:34-08:00
util: Drop ancient Intel CPU detection
We don't use it for anything.
Cc: mesa-stable # 24.3
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
(cherry picked from commit ca947e1295a8aedd4b7f09ca89ab285156b1309e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
9116861d
by David Heidelberg at 2024-11-14T09:31:34-08:00
util: drop XOP detection code
Introduced in 2013 with prospect of being used in future.
... 11 years later.
Fixes: 4b45b61fef6e ("util: add avx2 and xop detection to cpu detection code") # 24.3
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
(cherry picked from commit 962b996d4c569835e0c453a60bb4680d432d30f1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
a725b137
by David Heidelberg at 2024-11-14T09:31:35-08:00
llvmpipe: align with u_cpu_detect struct changes
Cc: mesa-stable # 24.3
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
(cherry picked from commit d21f7f75ff38ed26769235daf98af4a18b02f0ab)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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ecc3f03d
by David Rosca at 2024-11-14T09:31:36-08:00
radv/video: Fix H264 slice control
This needs to use aligned size, otherwise it will output two
slices when the size is not 16 aligned.
Fixes: 54d499818ca ("radv/video: add initial support for encoding with h264.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6a121f150750f0a3316a317274b14a4d0ac077f6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
42822bbc
by David Rosca at 2024-11-14T09:31:36-08:00
radv/video: Fix HEVC slice control
This needs to use aligned size, otherwise it will output two
slices when the size is not 64 aligned.
Fixes: 967e4e09dee ("radv/video: add h265 encode support")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e4ec135d8bbd94ef552c94fe1d09cf326417b14d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
bab33913
by David Rosca at 2024-11-14T09:31:37-08:00
radv/video: Report correct encodeInputPictureGranularity
Only aligned size can be encoded.
Fixes: 54d499818ca ("radv/video: add initial support for encoding with h264.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e941acfb9d055f2cef4bc2f21166e7c2c4821099)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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c1517edd
by David Rosca at 2024-11-14T09:31:38-08:00
radv/video: Avoid selecting rc layer over maximum
Vulkan spec doesn't say if this is allowed or not, but trying
to do this will hang.
Fixes: 4a19047d329 ("radv/video: Select temporal layer when encoding each frame")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit d1c1a33b35a0ae14bff0ecd03255a7dab3399f1c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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9c55d783
by Lionel Landwerlin at 2024-11-14T09:31:39-08:00
brw: allocate physical register sizes for spilling
All of the spilling code should work with physical register units
because for example SEND messages will expect a physical register as
destination.
So always allocate a full physical register for the spilled/unspilled
values and adjust the offsets of the registers to physical sizes too.
Cc: mesa-stable
Fixes: aa494cba ("brw: align spilling offsets to physical register sizes")
Closes: mesa/mesa#11967
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Found-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit a21cd8c5b623e9b8b199518331a148835844660f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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743b2fdf
by Friedrich Vock at 2024-11-14T09:31:39-08:00
vulkan/rmv: Correctly set heap size
RMV expects the size to be in bits 5-68, not 4-68.
Fixes: 845792db ("vulkan: Add RMV file exporter")
(cherry picked from commit 73d513c5be2f0cd2ca8f3c0aca0a536cabc8df58)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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bd8fb8a9
by Danylo Piliaiev at 2024-11-14T09:31:40-08:00
nir/nir_opt_offsets: Do not fold load/store with const offset > max
When (off_const > max) there is a wrap around uint when calling
try_extract_const_addition.
Exit early since folding doesn't make sense in this case.
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
(cherry picked from commit b501cbf153552a27c9a58554716288609337b491)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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72271ed3
by Michel Dänzer at 2024-11-14T09:31:42-08:00
Revert "util/mesa-db: Further simplify mesa_db_compact"
This reverts commit 92893309bcc0c1a9ab9eab844a896d99cbc4b4e2.
Need to revert this as well for the next revert.
(cherry picked from commit 66d68263f8fe2fff70bccdb91f700e58a9e8019c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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14f9d645
by Michel Dänzer at 2024-11-14T09:31:43-08:00
Revert "util: Use persistent array of index entries"
This reverts commit 031f2c2a691d9fbb84ea6146eeeda09d4a4d05a6.
It broke the macOS build.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12083
(cherry picked from commit fdc1c61306ddf72713b06aeaa963517636f02072)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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3c450c64
by Dylan Baker at 2024-11-18T09:39:55-08:00
.pick_status.json: Update to 8845255881f03df9a695fae164a64201c4211d35
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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1e9229fd
by David Heidelberg at 2024-11-18T09:39:57-08:00
compiler/rust: drop duplicated bindgen check
The same check is present in meson file in root directory.
Cc: mesa-stable # 24.3
Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
(cherry picked from commit 1368ee5e1aee9a760b445b7dd24d8b77be1b0800)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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232c6b2d
by Iván Briano at 2024-11-18T09:39:58-08:00
anv: remove unused/misleading/wrong parameters from the RT trampoline
Since the shader parameters are passed as inline data, push constants
are no longer used and so, not actually set on dispatch. But the
nr_params = 4 was still making the shader emit the code to load them,
causing page faults on simulation, and would also on HW if we didn't
always have a scratch page set.
The uses_inline_data parameter will be set from brw_compile_cs(), called
shortly after this point, so we don't need it here.
The subgroup_size is misleading, as we don't actually require that size
and the code that checks for it isn't even running for this shader.
Fixes: 97b17aa0b1b ("brw/nir: rework inline_data_intel to work with compute")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12152
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit d32a26b3e6915b9bcbe7d881011b97712229dc23)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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b4b12c67
by Samuel Pitoiset at 2024-11-18T09:40:05-08:00
radv: fix ignoring src stage mask when dst stage mask is BOTTOM_OF_PIPE
Otherwise the driver doesn't synchronize if there are image layout
transitions.
This fixes rendering issues with displayable DCC (usually black squares
in the bottom of screen). This mostly happens when an application
uses a lower resolution than the screen supports and fshack
(wine/proton) which upscales images uses COMPUTE_SHADER->BOTTOM_OF_PIPE
for the barrier after a dispatch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11547
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11600
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11789
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8705
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9890
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit c08d2c40ed3ae4008da31669f3d3b24c9b5aff0d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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922a339d
by Sam Lantinga at 2024-11-18T09:40:06-08:00
util: Fixed crash in HEVC encoding on 32-bit systems
This builds on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25059, and extends that change to all 32-bit systems.
This fixes a crash on SteamOS with the following test case:
unsigned char data[] = {
0x00, 0x00, 0x00, 0x01, 0x40, 0x01, 0x0c, 0x01, 0xff, 0xff, 0x01, 0x60,
0x00, 0x00, 0x03, 0x00, 0xb0, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00,
0x99, 0x2c, 0x0c, 0x01, 0x64, 0x7c, 0x00, 0x7c, 0xd2, 0x56, 0x01, 0x40,
0x00, 0x00, 0x00, 0x01, 0x42, 0x01, 0x01, 0x01, 0x60, 0x00, 0x00, 0x03,
0x00, 0xb0, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x99, 0xa0, 0x02,
0x80, 0x80, 0x32, 0x16, 0x24, 0xbb, 0x90, 0x84, 0x48, 0x9a, 0x83, 0x03,
0x03, 0x02, 0x00, 0xb2, 0x3e, 0x00, 0x3e, 0x69, 0x2b, 0x00, 0x5f, 0x08,
0x04, 0x10, 0x00, 0x00, 0x00, 0x01, 0x44, 0x01, 0xc0, 0x62, 0x0f, 0x02,
0x24
};
vlVaContext context;
vlVaBuffer buf;
memset(&context, 0, sizeof(context));
memset(&buf, 0, sizeof(buf));
context.packed_header_emulation_bytes = true;
buf.data = ""
buf.size = sizeof(data);
vlVaHandleVAEncPackedHeaderDataBufferTypeHEVC(&context, &buf);
Cc: mesa-stable
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 4ed8ef74b4dc111425d6596eb3341d91d563bf00)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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436e5c06
by Robert Mader at 2024-11-18T09:40:07-08:00
v3d: Support SAND128 base modifier
The BROADCOM_SAND128 modifier is usually used with an extra parameter
to pass in the stride via a side channel. Quoting from drm_fourcc.h:
> The pitch between the start of each column is set to optimally
> switch between SDRAM banks. This is passed as the number of lines
> of column width in the modifier (we can't use the stride value due
> to various core checks that look at it , so you should set the
> stride to width*cpp).
So apparently this is just a workaround for limitations in some kernel
APIs. DRM modifiers, however, are arguably a bad fit for extra
parameters that aren't known in advance. In the Wayland/KMS ecosystem
many components depend on being able to treat modifiers as opaque, e.g.
for negotiations etc. In practice the current approach requires various
software components to manually use the
`DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT()` macro - using the
`DRM_FORMAT_MOD_BROADCOM_SAND128` modifier directly with formats like
`NV12` results in a rejection in the KMS driver and corrupted output
in Mesa (because we'd bail out early in `v3d_sand8_blit()`).
Fortunately the stride check limitations mentioned above don't seem to
apply to Mesa though. Thus we can just add support for the base modifier
and stride (coming from V4L2), allowing various toolkits, Wayland
compositors and V4L2 decoder implementations to support e.g.
`NV12` + `DRM_FORMAT_MOD_BROADCOM_SAND128` (`NC12` in V4L2) in a generic
way.
Notes:
1. Wayland compositors trying to offload composition to KMS will still
fail when doing a test commit.
2. There is another limitation - in the V4L2 MPLANE API - that
requires userspace to know the correct offset of the second plane. That's
a known API limitation though and only affects V4L2 decoder implementations.
Cc: mesa-stable
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
(cherry picked from commit 758941ab0cf36676664f1082a100c9bdcaf2b1a9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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1c6b2f70
by Karol Herbst at 2024-11-18T09:40:09-08:00
rusticl/kernel: fix kernel variant selection
Apparently I messed up enough so that the optimized kernel variant was
almost never selected.
This fixes that :)
Fixes: f098620c215 ("rusticl/kernel: add optimized Kernel variant")
(cherry picked from commit a5149f3feff8de11b5dd90a0e618721e8f4a5d67)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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de9faec6
by Boris Brezillon at 2024-11-18T09:40:10-08:00
panvk/csf: Fix a wait-LS operation in finish_cs()
cs_wait_slots() expects a mask, cs_wait_slot() a slot ID.
Fixes: 5544d39f4420 ("panvk: Add a CSF backend for panvk_queue/cmd_buffer")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit c3ff3f2405104104cf1506c66fc3d3ea7698d8b4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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a3a064b9
by Matt Turner at 2024-11-18T09:40:11-08:00
vulkan: Avoid pointer aliasing
Avoids the sanitizer errors:
```
Test case 'dEQP-VK.pipeline.monolithic.spec_constant.graphics.vertex.basic.mixed_packed'..
../src/vulkan/util/vk_util.c:111:38: runtime error: load of misaligned address 0x603002b1c591 for type 'const uint16_t', which requires 2 byte alignment
0x603002b1c591: note: pointer points here
00 00 00 98 76 98 54 76 98 ba 10 32 54 76 98 ba dc fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff
^
../src/vulkan/util/vk_util.c:108:38: runtime error: load of misaligned address 0x603002b1c593 for type 'const uint32_t', which requires 4 byte alignment
0x603002b1c593: note: pointer points here
00 98 76 98 54 76 98 ba 10 32 54 76 98 ba dc fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
^
../src/vulkan/util/vk_util.c:105:38: runtime error: load of misaligned address 0x603002b1c597 for type 'const uint64_t', which requires 8 byte alignment
0x603002b1c597: note: pointer points here
54 76 98 ba 10 32 54 76 98 ba dc fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 03 11 00
^
```
Fixes: 476dc3c050d ("vulkan: add vk_spec_info_to_nir_spirv util method")
(cherry picked from commit 3d24f0ece139e040d515c3d15af11af4dbe44bd2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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d857c4a4
by Lionel Landwerlin at 2024-11-18T09:40:12-08:00
anv: fix incorrect aspect flag for depth/stencil formats
We're asking if compression is supported and
anv_formats_ccs_e_compatible() is assuming color aspect.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0317c44872 ("anv: add VK_EXT_host_image_copy support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12155
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
(cherry picked from commit 431f353bfef6eb754e5e9cf0ed064308897afa0b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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3567dac7
by Mary Guillemard at 2024-11-18T09:40:12-08:00
bi: Execute nir_opt_algebraic after nir_lower_pack
nir_lower_pack can generate split operations, execute algebraic again
to handle them.
This fix an assert on
"dEQP-VK.spirv_assembly.instruction.compute.opphi.vartype_float16" and
probably others tests.
Fixes: 3904cfabd6a ("bi: Use nir_opt_load_store_vectorize")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: John Anthony <john.anthony@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
(cherry picked from commit e5d64ca69c180cd5443d77b6e1b165529e7124b8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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f4d83eb5
by Erik Faye-Lund at 2024-11-18T09:40:13-08:00
glx: avoid null-deref
psc can be NULL here, so let's avoid dereferencing it.
Fixes: 34dea2b38eb ("glx: unify extension binding")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 5ced8b0ea24984f315e0934209a04a4e7f316829)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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9728a907
by Karol Herbst at 2024-11-18T09:40:14-08:00
vtn: handle struct kernel arguments passed by value
Due to LLVM ABI reasons the SPIRV-LLVM-Translator always uses pointers to
private memory for struct function parameters. This includes kernel entry
points.
However technically it's also legal to pass those parameters by value
according to the OpenCL SPIR-V Env spec.
One compiler making use of this is e.g. artic based on Thorin.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12149
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
(cherry picked from commit d0560f59cedf7ca88efe25bfbee72ff0819bcd15)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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8e45bd63
by Kenneth Graunke at 2024-11-18T09:40:15-08:00
brw: Fix try_rebuild_source's ult32/ushr handling to use unsigned types
We were accidentally doing a signed integer comparison here for ult32,
or a sign-extending shift for ushr.
One notable bit of fallout was that load_global_uniform_block_intel
address calculations broke on platforms that don't have native 64-bit
integer support, as the iadd64 lowering for "do I need to carry?" was
using ult32...and performing the wrong comparison. We spotted this in
Borderlands 3 on Alchemist once we turned on other optimizations.
Thanks to Lionel Landwerlin for helping spot the problem!
Fixes: c7b312ad45 ("brw: factor out source extraction for rematerialization")
Fixes: 339630ab05 ("brw: enable A64 loads source rematerialization")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 58480354432e8a0ee7b8ad80a1d1ae4ec01edfe6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
7dc34f11
by Lionel Landwerlin at 2024-11-18T09:40:16-08:00
anv: fix missing push constant reallocation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 62d96a6546 ("anv: add dirty tracking for push constant data")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12151
(cherry picked from commit 8845255881f03df9a695fae164a64201c4211d35)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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f35c690b
by Francisco Jerez at 2024-11-19T14:28:55-08:00
intel/fs/xe2: Fix up subdword integer region restriction with strided byte src and packed byte dst.
This fixes a corner case of the LNL sub-dword integer restrictions
that wasn't being detected by has_subdword_integer_region_restriction(),
specifically:
> if(Src.Type==Byte && Dst.Type==Byte && Dst.Stride==1 && W!=2) {
> // ...
> if(Src.Stride == 2) && (Src.UniformStride) && (Dst.SubReg%32 == Src.SubReg/2 ) { Allowed }
> // ...
> }
All the other restrictions that require agreement between the SubReg
number of source and destination only affect sources with a stride
greater than a dword, which is why
has_subdword_integer_region_restriction() was returning false except
when "byte_stride(srcs[i]) >= 4" evaluated to true, but as implied by
the pseudocode above, in the particular case of a packed byte
destination, the restriction applies for source strides as narrow as
2B.
The form of the equation that relates the subreg numbers is consistent
with the existing calculations in brw_fs_lower_regioning (see
required_src_byte_offset()), we just need to enable lowering for this
corner case, and change lower_dst_region() to call lower_instruction()
recursively, since some of the cases where we break this restriction
are copy instructions introduced by brw_fs_lower_regioning() itself
trying to lower other instructions with byte destinations.
This fixes some Vulkan CTS test-cases that were hitting these
restrictions with byte data types.
Fixes: 217d41236076280 ("intel/fs/gfx20+: Implement sub-dword integer regioning restrictions.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
a3543ebc
by Dylan Baker at 2024-11-19T14:28:55-08:00
.pick_status.json: Update to 9b779068c3a7a8ded00f1d2519fd01dd1d05f3d8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
e3f886ac
by David Rosca at 2024-11-19T14:29:03-08:00
radeonsi/vcn: Use correct frame context buffer for preencode on VCN5
Fixes: 3c5fe03b92c ("radeonsi/vcn: Add support for VCN5 dpb tier2")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
(cherry picked from commit 4ec43c59da8f8f03a27f2ac4ea2481586071c3fc)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
-
5a8be9c6
by Job Noorman at 2024-11-19T14:29:05-08:00
ir3,tu: include ir3 debug flags in shader hash key
Many debug flags influence shader codegen but are currently not included
in the hash key. This causes surprising effects as cache lookups may
return shaders compiled with different debug flags than currently in
effect. This patch fixes this by including all debug flags in the
shader hash key.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: c323848b0b7 ("ir3, tu: Plumb through support for per-shader robustness")
(cherry picked from commit d8c90806e4a103c63de534b2cb4fe662e1bee19d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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bc1c6a15
by Vldly at 2024-11-19T14:29:05-08:00
freedreno: Fix resource tracking on repeated map with discard
In two functions implementing resource discard rebind_resource is called
on resource before its track record is reset. This prevents update of
dirty_resource or dirty_shader_resource because of conditions in
needs_dirty_resource. With rsc->track reset and dirty_resource bits
missing further calls to transfer_map will not try to reallocate
resource storage when needed.
A way to reproduce the issue in both functions is by executing at least
3 draws modifying bound texture or VBO each time. This patch fixes those
cases and some related piglit tests on a5xx and should fix it on other
GPUs. Also it fixes rendering in Firefox and vsraytrace (except vertical
line at right edge).
Fixes: 0a62a874fc5 ("freedreno: Re-work dirty-resource tracking")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10374
Reviewed-by: Rob Clark <robclark@freedesktop.org>
(cherry picked from commit 6d14cad330a34e15db6dae184c45c98c3256eeae)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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49e5090f
by Michel Zou at 2024-11-19T14:29:06-08:00
ac/gpu_info: Fix missing prototype mingw error
Fixes: 246051ebc687 ("ac/gpu_info: print 32bpp modifiers")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes #8858
(cherry picked from commit 795a36325af637079ea283d73ea56eab833771bd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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185ae191
by Samuel Pitoiset at 2024-11-19T14:29:07-08:00
radv: add a new drirc option to disable DCC for mips and enable it for RDR2
The game aliases two images. It binds a memory object to two different
images, the first one being an image with 4 mips and the second with
only one mip but the bind offset is incorrect. It's like it queried
the first image size with different usage flags, so that DCC was
disabled.
Force disabling DCC for mips fixes the incorrect rendering and doesn't
hurt performance.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10200
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 2f13723c0aad358778d87ca7e844f438ca5fcfaf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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5cb4c5bd
by Marek Olšák at 2024-11-19T14:29:07-08:00
radeonsi: fix gl_FrontFace elimination when one side is culled
Fixes: 55d81214c9d800c066 - radeonsi: replace gl_FrontFacing with a constant if one side is always culled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(cherry picked from commit 51aa1d8381682789a666ed2e6575a79be7241f7a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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5ad75481
by Matt Turner at 2024-11-19T14:29:08-08:00
nir: Get correct number of components
The code wants the number of components used by the variable in the
current attribute slot, not the total number of components.
For e.g. a 4x3 matrix, glsl_get_components() returns 12, leading to the
following error reported by AddressSanitizer:
```
Test case 'dEQP-VK.tessellation.shader_input_output.cross_invocation_per_patch_mat4x3'..
../src/compiler/nir/nir_lower_io_to_vector.c:265:16: runtime error: index 4 out of bounds for type 'nir_variable *[4]'
```
Fixes: 5ef2b8f1f2e ("nir: Add a pass for lowering IO back to vector when possible")
(cherry picked from commit ba5c65f10b453ec71264027119e390e11e7aae21)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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ca6cccfe
by David Rosca at 2024-11-19T14:29:08-08:00
frontends/va: Create surfaces with correct fourcc for RT format
If applications doesn't send any attributes to describe the format,
we would always use driver preferred format (NV12). This is wrong
for any RT format other than the driver preferred (YUV420).
Driver doesn't have a choice here, we must use the matching format.
Cc: mesa-stable
Reviewed-by: Leo Liu <leo.liu@amd.com>
(cherry picked from commit c8a893becd0a9fd952339710d83d2084d0332aff)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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b3cb911e
by David Rosca at 2024-11-19T14:29:09-08:00
frontends/va: Use compositor blit with different number of planes
This fixes Y8_U8_V8_444_UNORM -> NV12 conversion for example.
Cc: mesa-stable
Reviewed-by: Leo Liu <leo.liu@amd.com>
(cherry picked from commit 217d70fc38aaa6a20dd866d9d1f0c3d3f87a9255)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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4af6a474
by Rhys Perry at 2024-11-19T14:29:09-08:00
nir/algebraic: fix iabs(ishr(iabs(a), b)) optimization
iabs(a) is not positive if "a" is the minimum signed value, so this is
incorrect in that case for some values of "b".
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 2b76de9b5dd5 ("nir/algebraic: Add a couple optimizations for iabs and ishr")
(cherry picked from commit ecd6ae12fbd487d759aaf347c6947a78483c1642)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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8790de10
by Rhys Perry at 2024-11-19T14:29:10-08:00
nir/algebraic: check bit sizes in lowered unpack(pack()) optimization
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 894f7f438745 ("nir_opt_algebraic: Add a couple optimizations for lowered unpack(pack())")
(cherry picked from commit 327e5465fca3275bac866729783d3f7c4ea11848)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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faacd804
by Rhys Perry at 2024-11-19T14:29:10-08:00
nir/lcssa: fix premature exit of loop after rematerializing derefs
If we have NIR such as:
32x4 %48 = @load_vulkan_descriptor (%47) (desc_type=SSBO)
32x4 %76 = deref_cast (tint_symbol_11 *)%48 (ssbo tint_symbol_11) (ptr_stride=0, align_mul=4, align_offset=0)
32x4 %77 = deref_struct &%76->tint_symbol_10 (ssbo int) // &((tint_symbol_11 *)%48)->tint_symbol_10
A single nir_rematerialize_deref_in_use_blocks() will rematerialize the
deref_struct and then it's deref_cast. However,
nir_foreach_instr_reverse_safe is not safe if the next iteration's
instruction is removed. This can result in the instruction loop exiting
and the load_vulkan_descriptor never having an LCSSA phi.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 439e8c42cc4b ("nir/lcssa: Fix rematerializing derefs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11770
(cherry picked from commit 65a54b4ec41f4de33c770ceb1535358d008fbaad)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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0bf0f66c
by Lionel Landwerlin at 2024-11-19T14:29:11-08:00
anv: prevent access to destroyed vk_sync objects post submission
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 36ea90a361 ("anv: Convert to the common sync and submit framework")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12145
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit 9b779068c3a7a8ded00f1d2519fd01dd1d05f3d8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32261>
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ae339fb1
by Dylan Baker at 2024-11-21T08:27:37-08:00
docs: add release notes for 24.3.0
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f1f246cf
by Dylan Baker at 2024-11-21T08:27:38-08:00
VERSION: bump for 24.3.0 release
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>