-
7021c676
by Eric Engestrom at 2024-08-28T21:37:10+02:00
docs: add sha sum for 24.2.1
-
25482678
by Eric Engestrom at 2024-08-29T16:29:23+02:00
.pick_status.json: Update to 51e05c284465786bf125d9d36081e9152c80619b
-
b558fb25
by Jesse Natalie at 2024-08-29T16:29:25+02:00
d3d12: Don't use a vertex re-ordering GS for line primitives
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30903>
(cherry picked from commit dac44e02f72d645418a1c6059342a60b508c6eb8)
-
139398f1
by Kenneth Graunke at 2024-08-29T16:30:13+02:00
intel/brw: Drop misguided sign extension attempts in extract_imm()
This function never expands a type - it only narrows it. As such, we
don't need to ever sign extend to fill additional new bits. I think
this code was left over from earlier versions of my optimization pass
that was buggy and trying to handle cases it should not have.
Fixes: 580e1c592d90 ("intel/brw: Introduce a new SSA-based copy propagation pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30884>
(cherry picked from commit 51c85e03632c85da64a65d925bbfc30e3908dbb3)
-
a7b7b875
by Kenneth Graunke at 2024-08-29T16:30:16+02:00
intel/brw: Fix extract_imm for subregion reads of 64-bit immediates
We could be trying to extract a D/UD from a Q/UQ, for example. We were
ignoring the top 32-bits, which is incorrect.
Fixes: 580e1c592d90 ("intel/brw: Introduce a new SSA-based copy propagation pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30884>
(cherry picked from commit da395e6985ab32978ebe120fe83ef05989c1a3e6)
-
b4f0699d
by Eric Engestrom at 2024-08-29T16:49:41+02:00
v3dv/ci: fix test timeout for v3dv-rpi5-vk-full:arm64
It was set to 170min, which made sense when the job timeout was 3h, but
then 4bb564f40dc1ba758c40 ("broadcom/ci: add more jobs to test with rpi5")
lowered the job timeout to 2h without lowering the test timeout to match.
Fixes: 4bb564f40dc1ba758c40 ("broadcom/ci: add more jobs to test with rpi5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
(cherry picked from commit aac9c74a8341975aa7b49415da8d3072c878a848)
-
369c1fd4
by Eric Engestrom at 2024-08-29T17:32:38+02:00
etnaviv/ci: fix gc2000_piglit test timeout
Setting it to the same value as (or higher than) the job timeout
effectively bypasses the safety mechanism.
Let's change it to `job timeout - 5min`.
Fixes: f39ffc69110d1da0d87f ("ci/etnaviv: Get the gc2000_piglit manual job mostly working.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
(cherry picked from commit b978d3eb54b081228d040e58f722d2007f331e84)
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972eabb3
by Eric Engestrom at 2024-08-29T17:34:08+02:00
.pick_status.json: Mark 4888d39f29ae84dd279f2bd4714eb0f6e8ba5d20 as denominated
-
467e2638
by Eric Engestrom at 2024-08-29T17:34:13+02:00
.pick_status.json: Mark 033818fdd99a543fd1cb17cc8e4be07f831a9003 as denominated
-
c3cdff39
by Iván Briano at 2024-08-29T18:42:36+02:00
nir: add pass to convert ViewIndex to DeviceIndex
Used to implement VK_PIPELINE_CREATE_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30329>
(cherry picked from commit 7fce39484e68c0022b64357f844c9cc7e5853ea1)
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b336bc37
by Faith Ekstrand at 2024-08-29T18:42:36+02:00
vulkan/pipeline: Handle VIEW_INDEX_FROM_DEVICE_INDEX_BIT
The rehash we're doing here is a bit of a hack but it's a back-portable
hack. We'll fix it properly in following commits.
Fixes: 9308e8d90d26 ("vulkan: Add generic graphics and compute VkPipeline implementations")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30876>
(cherry picked from commit c0191b20de5f41c0c66ac534d6b735275c4916bb)
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a98bd06d
by Faith Ekstrand at 2024-08-29T18:42:36+02:00
nvk: Hash minSampleShading in nvk_hash_graphics_state()
We put minSampleShading in the nvk_shader and [de]serialize that to/from
the binary so it also needs to go in the hash. We could also plumb the
pipeline state through to the deserialize callback but that's quite a
stretch and this literally only affects minSampleShading which is a
rarely used feature.
Fixes: 813b253939ee ("nvk: Switch to shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30914>
(cherry picked from commit 5f402f3aae492d29de00c6027fdf4cb8aa042c19)
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8390fe99
by Tapani Pälli at 2024-08-29T18:42:37+02:00
anv: set correct miplevel for anv_image_hiz_op
Fixes: 5efecc9782c ("anv: Enable HiZ on multi-LOD depth buffers.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11787
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30892>
(cherry picked from commit 44e1cf2748972e9289d5ab595be89f75ffb4654b)
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be036a77
by Konstantin Seurer at 2024-08-29T18:42:37+02:00
nir/opt_loop: Fix handling else-breaks in merge_terminators
If both breaks are in the else branch, we have to use iand.
Fixes: 9995f33 ("nir: add merge loop terminators optimisation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11726
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30850>
(cherry picked from commit 0fc3c52e438cc2f0fb8fd0e04094423736afa0b6)
-
ff6d97f8
by Rohan Garg at 2024-08-29T18:42:37+02:00
anv: prefetch samplers when dispatching compute shaders
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30922>
(cherry picked from commit 32f606486fa79ba4b549f42b45f646de6bc38bd2)
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8b277994
by Eric Engestrom at 2024-08-30T12:11:20+02:00
.pick_status.json: Update to 3e4f73b3a0e0b9420f9614d3e271c49225c6f5d3
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2950194e
by Roland Scheidegger at 2024-08-30T12:13:38+02:00
llvmpipe: Fix type mismatch when storing residency info
The storage allocated was always the same for both the ordinary texture
result data as well as the residency info. However, the former can be
float vector, whereas the latter is always int vector.
At least some llvm versions/builds will assert on this mismatch when
storing the data.
While here, also cut unnecessary zero initialization (lp_build_alloca()
already explicitly does this).
Fixes: 6168317b8491 (lavapipe: Implement shaderResourceResidency)
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30878>
(cherry picked from commit 9b717596b21175036b361986f0db5c12c4dccb45)
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7291e2fb
by Job Noorman at 2024-08-30T12:20:16+02:00
ir3: fix recognizing const/imm registers as a0
Fixes: 72bb4d79dcc ("ir3/legalize: handle scalar ALU WAR hazards for a0.x")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30611>
(cherry picked from commit 7cc24aa506beb09847181c64a4a14507e77d840f)
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56d048a4
by Lionel Landwerlin at 2024-08-30T12:23:41+02:00
anv: fix utrace compute timestamp reads on Gfx20
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30923>
(cherry picked from commit 14d772d67876a25cca0bd9161df5315a4d3055a1)
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61212390
by Lionel Landwerlin at 2024-08-30T12:25:10+02:00
iris: fix utrace compute end timestamp reads on Gfx20
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30923>
(cherry picked from commit 91b3ae71d71789c0846d592c83782b6885c48e2a)
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41ae7150
by Valentine Burley at 2024-08-30T12:27:22+02:00
tu: Fix VK_EXT_extended_dynamic_state3 feature
Don't claim to support extendedDynamicState3SampleLocationsEnable on pre-A650 GPUs,
which can't advertise VK_EXT_sample_locations.
Fixes dEQP-VK.info.device_mandatory_features on A6xx Gen 1 and Gen 2.
Fixes: 84726da2f44 ("tu: Implement extendedDynamicState3SampleLocationsEnable")
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30730>
(cherry picked from commit 98d52cf292883898b7432b932aaed1e2ddf89129)
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68dd5f48
by Jordan Justen at 2024-08-30T12:27:39+02:00
intel/dev: Update hwconfig => max_threads_per_psd for Xe2
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30887>
(cherry picked from commit 3e4f73b3a0e0b9420f9614d3e271c49225c6f5d3)
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e7da81c3
by Jordan Justen at 2024-08-30T16:18:03-07:00
intel/dev: Re-enable LNL PCI IDs (without INTEL_FORCE_PROBE) on Mesa 24.2
This reverts 2fc396ae75e ("intel/dev: Disable LNL PCI IDs on Mesa 24.2
(require INTEL_FORCE_PROBE)") from the 24.2 branch.
Mesa's 2fc396ae75e was needed because, although we were compatible
with Linux 6.11, this kernel change which will appear in Linux 6.12
would break our previous LNL support, causing the driver to fail to
load:
7108b4a589cd ("drm/xe/uapi: Expose SIMD16 EU mask in topology query")
Since d8b5ee8d657 ("intel/dev: Support new topology type with SIMD16
EUs"), this issue was resolved, but we were told we had to wait for
the kernel to remove force_probe before they would guarantee backwards
compatibility with uapi changes.
Since drm-next 6d0ebb390485 ("Merge tag 'drm-intel-next-2024-08-29' of
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next"), the
upstream drm kernel has now removed force_probe for LNL. Ref:
9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Tested with upstream drm kernel:
commit 6d0ebb3904853d18eeec7af5e8b4ca351b6f9025
Merge: 8bdb468dd7a5 b5d4657e192b
Author: Dave Airlie <airlied@redhat.com>
Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30959>
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2a9a4578
by Dylan Baker at 2024-09-05T12:54:35-07:00
.pick_status.json: Update to 4aa1259eb4a86a94596dd31d6b80a99ce6d91299
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6460525c
by Samuel Pitoiset at 2024-09-05T12:54:35-07:00
radv: fix emitting DGC indirect draws with drawid/base_instance
This fixes test_execute_indirect_state_vbo_offsets, a new vkd3d-proton
test.
The drawid/base_instance bits were cleared by mistake.
Fixes: e59a16bbb8f ("radv: use an indirect draw when IBO isn't updated as part of DGC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30971>
(cherry picked from commit 88733827030a054a89c6fb5d83fb2564d289021d)
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5591651b
by Dave Airlie at 2024-09-05T12:54:35-07:00
vulkan/video: fix vui encoding
This is a single bit field.
Fixes: d46162981a78 ("vulkan/video: add h264 headers encode")
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Tested-by: Bernhard C. Schrenk <clemy@clemy.org>
Reviewed-by: Bernhard C. Schrenk <clemy@clemy.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30968>
(cherry picked from commit af425a63f7fa47308cf0e80da32a433386228756)
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f87fd87d
by Jordan Justen at 2024-09-05T12:54:35-07:00
intel/dev: Enable BMG PCI IDs (without INTEL_FORCE_PROBE)
Tested with upstream drm-next kernel:
commit 6d0ebb3904853d18eeec7af5e8b4ca351b6f9025
Merge: 8bdb468dd7a5 b5d4657e192b
Author: Dave Airlie <airlied@redhat.com>
Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Ref: drm-next 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30056>
(cherry picked from commit e32989a698a78560c3bce935d6bf1feecd267c91)
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b3e98474
by Pierre-Eric Pelloux-Prayer at 2024-09-05T12:54:35-07:00
radeonsi: don't always update shader coherency draw call counter
The bug report has a sequence that looks like this:
* set tex as framebuffer
* dispatch a compute shader that doesn't use tex
* dispatch a compute shader that uses it
Since we were updating the counters at step 2, step 3 failed to realize
that calling si_make_CB_shader_coherent was needed.
While at it, this commit splits the draw call tracking counter in 2: one
for CB, one for DB.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11638
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30591>
(cherry picked from commit bfcee149eda243d3b0f3091ee6819dbdcbd7d33a)
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9b0b6243
by Lucas Stach at 2024-09-05T12:54:35-07:00
etnaviv: emit SAMPLER_LOG_SIZE on sampler state changes
The int filter enable bit in that state depends on both sampler view
and sampler state, so the state need to be re-evaluated and emitted
not only on sampler view changes, but also when the sampler state
changes.
CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30605>
(cherry picked from commit 8fc977cb292bd32428884c673b05f5eb0e5ec148)
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5f17610f
by David Rosca at 2024-09-05T12:54:35-07:00
frontends/va: Fix locking in vlVaDeriveImage
The mutex needs to be locked before accessing the handle table.
After 64ca0fd2f28 ("frontends/va: Allocate surface buffers on demand")
the issue is now much more likely to happen and can be reproduced when
transcoding using ffmpeg.
Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30935>
(cherry picked from commit fccf31c231a2b724f335509bebd102fcf9b289f7)
Conflicts:
src/gallium/frontends/va/image.c
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d13e6294
by David Rosca at 2024-09-05T12:54:35-07:00
frontends/va: Fix locking in vlVaQueryVideoProcPipelineCaps
The mutex needs to be locked before accessing the handle table.
Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30935>
(cherry picked from commit 93a749c44974aa901041f12d241a6ac833c6f014)
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9ad801d9
by Mike Blumenkrantz at 2024-09-05T12:54:35-07:00
dril: use the super fallback path for software fallback
just in case gbm init fails somehow, swrast should still be able to
return some kind of fbconfigs
Fixes: ef88af84676 ("dril: always take the egl init path")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30979>
(cherry picked from commit 06d417af80bc1f171cadc338e63a7aa75c877754)
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00cfae94
by Patrick Lerda at 2024-09-05T12:54:35-07:00
iris: fix indirect draw refcnt imbalance
Indeed, the object ring_bo was not freed.
For instance, this issue is triggered with:
"piglit/bin/arb_shader_image_load_store-host-mem-barrier -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.
Fixes: 5438b1910464 ("iris: enable generated indirect draws")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30975>
(cherry picked from commit 6ac3beeb85033a23efbcc160a7d392e29807f345)
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25235a9f
by Rhys Perry at 2024-09-05T12:54:35-07:00
aco/ra: fix sub-dword get_reg_specified in some cases
For example, v6b MIMG can have sdw_def_info={4, 6}. This now has similar
behaviour as the DefInfo constructor.
fossil-db (navi31):
Totals from 5 (0.01% of 79395) affected shaders:
CodeSize: 29460 -> 29408 (-0.18%); split: -0.29%, +0.11%
Latency: 22133 -> 21934 (-0.90%); split: -2.51%, +1.61%
InvThroughput: 2953 -> 2963 (+0.34%); split: -0.03%, +0.37%
Copies: 410 -> 409 (-0.24%); split: -1.95%, +1.71%
VALU: 3242 -> 3241 (-0.03%); split: -0.25%, +0.22%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 56345b8c610e ("aco: allow reading/writing upper halves/bytes when possible")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30761>
(cherry picked from commit 1e6741bf6b23a201af13b9368f06a2d8325c5dbb)
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12deeb2a
by Jesse Natalie at 2024-09-05T12:54:35-07:00
microsoft/compiler: Move nir_lower_undef_to_zero out of the optimization loop
Otherwise after https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7710
I'm getting fighting between this pass and nir_opt_if.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31003>
(cherry picked from commit 44cc67e659fa77bf1d0e7455d120ca37412efa4d)
-
5bab67ae
by Mike Blumenkrantz at 2024-09-05T12:54:35-07:00
dril: also create double-buffered configs in swrast fallback
Fixes: 06d417af80b ("dril: use the super fallback path for software fallback")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31013>
(cherry picked from commit 56ac37845487b62f495428b0f20d145489f621e2)
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4bc14040
by Lionel Landwerlin at 2024-09-05T12:54:35-07:00
brw: align spilling offsets to physical register sizes
In commit fe3d90aedf ("intel/fs/xe2+: Fix calculation of spill message
width for Xe2 regs.") we aligned the width of scratch messages to
physical register sizes (32B prior to Xe2, 64B for Xe2+).
But our spilling offsets are computed using the register allocations
sizes which are in units of 32B. That means on Xe2, you can end up
spilling a virtual register allocated at 32B (which we use for surface
state computations with exec_all) and then the spilling of that
register will be emitted in SIMD16, having the upper 8 lanes
overwriting the next spilled register.
We could potentially limit spills to SIMD8 messages on Xe2 (only
writing 32B of data), but we're also unlikely to have all 32B virtual
register spilled next to one another. And if not tightly packed, we
would have 64B registers stored on 2 different cachelines which sounds
inefficient.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fe3d90aedf ("intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.")
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30983>
(cherry picked from commit aa494cbacf3bfa57163bbed8b5552ad25434e713)
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ea7f5d9a
by Zan Dobersek at 2024-09-05T12:54:35-07:00
tu: use instance indices in RD dump filenames
Until now the RD dumps were stored in files on a per-device basis, using
the device index but assuming only one Vulkan instance is active. With
multiple active instances, different devices separated across those
instances could end up storing RD dumps into files with the same name.
tu_instance struct now has an index member variable that's assigned upon
creation with an incrementally-increasing global counter value. RD dump
output name now also contains this instance index, avoiding the described
naming collisions.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Fixes: f9c4e25483f ("freedreno: add fd_rd_output facilities for gzip-compressed RD dumps")
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30977>
(cherry picked from commit 4c359eae016a5ca92308d40f75887f8d331ac6c8)
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993c4c19
by Karol Herbst at 2024-09-05T12:54:35-07:00
clc: fix compilation error with llvm-20
LLVM commit:
https://github.com/llvm/llvm-project/commit/924a7d83b4287b3b85dd1ca29d2d3e1f0a10ea68
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11814
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30980>
(cherry picked from commit 14ebecd78711804bc60f56cc53632bfab9d375df)
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cb81063f
by David Heidelberg at 2024-09-05T12:54:35-07:00
panfrost: drop leftover definition after pan_nir_lower_64bit_intrin removal
Fixes: bd0d3c7b1c61 ("panfrost: drop pan_nir_lower_64bit_intrin")
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30994>
(cherry picked from commit 63781071dbe524ab2f1dd140af47813adc34b6dc)
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41f579fb
by Faith Ekstrand at 2024-09-05T12:54:35-07:00
nvk: Don't do linear<->tiled copies for rendering suspend/resume
This also fixes a bug where we were potentially emitting copy commands
after we'd called nvk_cmd_buffer_push() but before finishing the current
push. Rust would have caught this...
Fixes: bca2f13dd8ee ("nvk: enable rendering to DRM_FORMAT_MOD_LINEAR images")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
(cherry picked from commit d7d02872373cd4737639542adf54c380fe4659d9)
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4bf65751
by Faith Ekstrand at 2024-09-05T12:54:35-07:00
nvk: Take depth image layer counts from the VkRenderingInfo
Otherwise OOB layers may render to the wrong layer in the depth image.
While we're here, add the same layer count asserts for color images.
Fixes: 9345b95346dd ("nvk: Bind 3D depth/stencil images as 2D arrays")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
(cherry picked from commit e533484d06ff9635dfdd41df89eaa6662842f28d)
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832fdfd7
by Faith Ekstrand at 2024-09-05T12:54:35-07:00
vulkan: Allow pColorAttachmentLocations == NULL in CmdSetRenderingAttachmentLocationsKHR()
Fixes: fe19405c4640 ("vulkan/runtime: handle new dynamic states for attachment remapping")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31033>
(cherry picked from commit ea783a96b86b317ec253af95a8e4fcd6854ff5d9)
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a5330b42
by Jordan Justen at 2024-09-05T12:54:35-07:00
anv: Drop "not yet supported" warning for Xe2
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31011>
(Cherry picked from commit 16a835ed3d4ed4edf7ebb31d04fe549226bc8492)
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54e7fae6
by Dylan Baker at 2024-09-05T15:27:45-07:00
docs: add release notes for 24.2.2
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3f77b0de
by Dylan Baker at 2024-09-05T15:28:45-07:00
VERSION: bump for 24.2.2