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[Git][xorg-team/vulkan/spirv-headers][upstream-unstable] 3 commits: Register spq tools for SPIR-V (#399)

Title: GitLab

Timo Aaltonen pushed to branch upstream-unstable at X Strike Force / vulkan / spirv-headers

Commits:

  • 04db24d6
    by PENGUINLIONG at 2024-03-20T08:38:06-07:00 
    Register spq tools for SPIR-V (#399)

* Update spir-v.xml

* Update spir-v.xml

* Update spir-v.xml
  • 7d500c4d
    by Michal Paszkowski at 2024-03-22T10:23:05-07:00 
    Register LLVM SPIR-V Backend as SPIR-V generator (#423)

* Register LLVM SPIR-V Backend as SPIR-V generator

* Change LLVM SPIR-V Backend vendor from "Intel" to "LLVM"
  • 4f7b471f
    by Adel Ejjeh at 2024-03-27T08:37:11-07:00 
    Update bit reservations for loop controsl and memory operands (#424)

1 changed file:

Changes:

  • include/spirv/spir-v.xml
    ... ... @@ -92,7 +92,9 @@
    92 92 
             <id value="39"  vendor="SirLynix" tool="Nazara ShaderLang Compiler" comment="Contact Jérôme Leclercq, https://github.com/NazaraEngine/ShaderLang"/>
    93 93 
             <id value="40"  vendor="NVIDIA" tool="Slang Compiler" comment="Contact Theresa Foley, tfoley@nvidia.com, https://github.com/shader-slang/slang/"/>
    94 94 
             <id value="41"  vendor="Zig Software Foundation" tool="Zig Compiler" comment="Contact Robin Voetter, https://github.com/Snektron"/>
    95 
    -        <unused start="42" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
    95 
    +        <id value="42"  vendor="Rendong Liang" tool="spq" comment="Contact Rendong Liang, admin@penguinliong.moe, https://github.com/PENGUINLIONG/spq-rs"/>
    96 
    +        <id value="43"  vendor="LLVM" tool="LLVM SPIR-V Backend" comment="Contact Michal Paszkowski, michal.paszkowski@intel.com, https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/SPIRV"/>
    97 
    +        <unused start="44" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
    96 98 
         </ids>
    97 99
    98 100 
         <!-- SECTION: SPIR-V Opcodes and Enumerants -->
    ... ... @@ -208,8 +210,8 @@
    208 210
    209 211 
         <!-- Reserved loop control bits -->
    210 212 
         <ids type="LoopControl" start="0" end="15" vendor="Khronos" comment="Reserved LoopControl bits, not available to vendors - see the SPIR-V Specification"/>
    211 
    -    <ids type="LoopControl" start="16" end="25" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
    212 
    -    <ids type="LoopControl" start="26" end="30" comment="Unreserved bits reservable for use by vendors"/>
    213 
    +    <ids type="LoopControl" start="16" end="27" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
    214 
    +    <ids type="LoopControl" start="28" end="30" comment="Unreserved bits reservable for use by vendors"/>
    213 215 
         <ids type="LoopControl" start="31" end="31" vendor="Khronos" comment="Reserved LoopControl bit, not available to vendors"/>
    214 216
    215 217
    ... ... @@ -269,8 +271,8 @@
    269 271
    270 272 
         <!-- Reserved memory operand bits -->
    271 273 
         <ids type="MemoryOperand" start="0" end="15" vendor="Khronos" comment="Reserved MemoryOperand bits, not available to vendors - see the SPIR-V Specification"/>
    272 
    -    <ids type="MemoryOperand" start="16" end="17" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
    273 
    -    <ids type="MemoryOperand" start="18" end="30" comment="Unreserved bits reservable for use by vendors"/>
    274 
    +    <ids type="MemoryOperand" start="16" end="18" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
    275 
    +    <ids type="MemoryOperand" start="19" end="30" comment="Unreserved bits reservable for use by vendors"/>
    274 276 
         <ids type="MemoryOperand" start="31" end="31" vendor="Khronos" comment="Reserved MemoryOperand bit, not available to vendors"/>
    275 277
    276 278 
         <!-- SECTION: SPIR-V Image Operand Bit Reservations -->

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