-
90dcd95c
by Eric Engestrom at 2024-03-14T00:11:24+00:00
docs: add sha256sum for 24.0.3
-
5b8ee85c
by Eric Engestrom at 2024-03-14T08:39:49+00:00
.pick_status.json: Update to 9b6d6c1d2d0c8a517e974abbf7b75a47a607f6ec
-
9e5f6d42
by Samuel Pitoiset at 2024-03-14T11:41:35+00:00
ac/nir: fix exporting NGG streamout outputs with implicit PrimId from VS/TES
With RADV, when VS/TES and FS are compiled separately, the PrimitiveId
is exported unconditionally because it's not possible to know if the
FS reads it or not. This happens with fast-link GPL and shader object.
Though, the PrimitiveID should be ignored when it's implicitly exported
because otherwise the stream output LDS offset is incorrect.
This fixes a bunch of failures with transform feedback and Zink/RADV
when shader object is enabled on RDNA3.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27981>
(cherry picked from commit d12984edb8a9de6cfd6ade8201fd229c494880d2)
-
2eb71d15
by Iván Briano at 2024-03-14T11:44:18+00:00
compiler/types: fix serialization of cooperative matrix
Encoding of cmat_desc is overwriting the base_type with the type of the
elements of the matrix.
Fixes: 2d0f4f2c17b ("compiler/types: Add support for Cooperative Matrix types")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28086>
(cherry picked from commit e1b66f9707c010a4b554b3039649afb13cba61de)
-
7f56248f
by Mike Blumenkrantz at 2024-03-14T11:44:20+00:00
zink: destroy batch states after copy context
the copy context contains its own batch states, so these must
not be destroyed yet
Fixes: b06f6e00fba ("zink: fix heap-use-after-free on batch_state with sub-allocated pipe_resources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28118>
(cherry picked from commit 7fd12a446d09cb2b21311cad09515cad08987051)
-
724b1c19
by Marek Olšák at 2024-03-14T11:44:21+00:00
amd/registers: add correct gfx11.x enums for BINNING_MODE
Fixes: ced3fbbcf93 - amd/registers: add gfx11.json
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 62d360c287193609e921cfd9886c3f5b37c4b9ed)
-
d5b22fa7
by Marek Olšák at 2024-03-14T11:44:21+00:00
radeonsi: disable binning correctly on gfx11.5
Fixes: b44a886b84c - amd/common: add registers for gfx11.5
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 20445f296bfcf3be40436617aad5d8378ad09bce)
-
03bc6156
by Marek Olšák at 2024-03-14T11:44:22+00:00
radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT
Fixes: 25a66477d02 - radeonsi/gfx11: register changes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 7d3a414662ed4aaffd80762532a1c3c9f4cfc4f1)
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822212ce
by Marek Olšák at 2024-03-14T11:44:23+00:00
radeonsi/gfx10.3: add a GPU hang workaround for legacy tess+GS
Fixes: a23802bcb9a - ac,radeonsi: start adding support for gfx10.3
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit ea94cb95e4dc6da8ee458db276942be1f72afa44)
-
319f9314
by Marek Olšák at 2024-03-14T11:44:23+00:00
radeonsi/gfx11: add missing DCC_RD_POLICY setting
Fixes: 5acff16ce4e ("radeonsi: add a separate gfx10_init_gfx_preamble_state function")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 2347259f1da7ae7bece064f224401956212333c3)
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640932a6
by Hyunjun Ko at 2024-03-14T11:44:32+00:00
anv/video: fix scan order for scaling lists on H265 decoding.
The default scan order of scaling lists is up-right-diagonal
according to the spec. But the device requires raster order,
so we need to convert from the passed scaling lists.
Fixes: 8d519eb ("anv: add initial video decode support for h265")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28063>
(cherry picked from commit db8eaa3620393f504e12c8bab99285eb679e7e9e)
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29afc1c5
by Lionel Landwerlin at 2024-03-14T11:44:33+00:00
intel/fs: fixup sampler header message
If you look at the sampler message header on Gfx9+, you'll see that we
mostly only use 2 dwords (dw2 & dw3). DW2 has a bunch of sampler
parameters, DW3 is the sampler handle.
On Gfx9 we can micro optimize by copying r0 into the header because
the HW mostly doesn't care about other DWs. We just have to clear dw2
on non VS/FS stages.
On Gfx11+, we always have to do a careful copy of the r0.3 bits to
mask out the bottom unrelated bits. So there, just clearing the entire
header makes more sense.
On Xe2+, the dw4 of the header references the sampler feedback surface
handle and bit0 is a boolean to know whether to use that surface or
not. So it *REALLY* matters to have that as 0. If we copy r0, we'll
get random bits in dw4, leading to enable that surface.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28082>
(cherry picked from commit 75c6ad99073ff4632955ae899057653902e6839f)
-
84abf14d
by Karol Herbst at 2024-03-14T11:44:36+00:00
rusticl/kernel: assign sampler locations before DCEing variables
This fixes an issue hit by one of darktable's kernels, where the sampler
argument got assigned the location of a dead kernel parameter turning it
into a zombie and leading us to trash the kernel input buffer's layout.
Fixes: 25b8a34b48f ("rusticl/kernel: inline samplers")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28121>
(cherry picked from commit 2df640c4f66c4064dfa94711602af49dcaf53d69)
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ef52324f
by Mike Blumenkrantz at 2024-03-14T11:44:37+00:00
mesa: force rendertarget usage on required-renderable formats
the existing guesswork during format selection for teximage is
accurate most of the time, but it's not accurate all of the time.
GL/ES each have a set of sized formats that are required to be
color renderable, and so any time one of these is allocated as a
texture, it MUST have the rendertarget usage bit attached so that
it can later be bound as a framebuffer attachment
an alternative might be to relax this and then try to do migration
to a different format/buffer later if necessary, but that's hard and
probably not actually as useful
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28055>
(cherry picked from commit 0f66589c2a461524f324655ffc62503f259cb79b)
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babead0a
by Mary Guillemard at 2024-03-14T11:45:07+00:00
nvk: Always copy conditional rendering value before compare
The spec requires a compare on 32-bit but the hardware actually compare 64-bit.
As such, we are required to copy the value to a temporary buffer before
the compare.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 8c25cd307af ("nvk: EXT_conditional_rendering")
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28106>
(cherry picked from commit 80eac1337d47dd7899781bdc74796bf167b33c90)
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47bbdbec
by Mike Blumenkrantz at 2024-03-14T11:45:08+00:00
zink: try getting sparse page size again without storage bit on fail
only certain formats are required to have the storage bit, so be more
tolerant of failure in the case where drivers actually check flags
and reject storage usage when it's actually unsupported
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28115>
(cherry picked from commit 61e5b6ad9dcde1f2a75dfd09cdbf9ea86b352223)
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63218f41
by Mike Blumenkrantz at 2024-03-14T12:04:33+00:00
zink: set the sparse format usage flags directly based on queried props
this should yield more consistent results and avoid weird cases where
various formats are queried for things they don't support and won't use
Fixes: 9a412c10b7a ("zink: set all usage flags when querying sparse features")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28115>
(cherry picked from commit 8fa413fef05ceaf4e811d2c564e766431c1d6701)
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895bc568
by Marek Olšák at 2024-03-14T12:04:33+00:00
ac/llvm: fix SSBO bounds checking by using raw instead of struct opcodes
Setting vindex != NULL (even if it's 0) selects a struct.buffer.load opcode,
which causes LLVM to look for "index * stride + offset" in voffset and
moves "index" to vindex (i.e. not 0 anymore), but the bounds checking
(OOB_SELECT) is set to ignore vindex. Setting vindex = NULL selects
a raw.buffer.load opcode.
Fixes: 6b573c00c9156 - ac/nir: use ac_build_buffer_load() for SSBO load operations
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10794
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28119>
(cherry picked from commit e589833ee1e6833f4611c200f2044ff303dd6346)
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c3185610
by Marek Olšák at 2024-03-14T12:04:33+00:00
radeonsi: fix the DMA compute shader
It was correct for the parameters that the driver was using, but incorrect
for other parameters.
1. The address computation must multiply the workgroup size (wave size)
by num_mem_ops to fix the case when num_dwords_per_thread > 4.
2. nir_load_ssbo shouldn't set the number of components to 4 when
num_dwords_per_thread < 4.
Fixes: 6584088cd5e - radeonsi: "create_dma_compute" shader in nir
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28119>
(cherry picked from commit e99765df08c7fe6be836022896152bbca7a94ff4)
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90386f2a
by Mike Blumenkrantz at 2024-03-14T12:04:33+00:00
zink: rename optimal_key in update_gfx_program_optimal()
no functional changes
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28017>
(cherry picked from commit daf2f4a583cd02d80d0acb200279411d1247356e)
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ff06623b
by Mike Blumenkrantz at 2024-03-14T12:04:33+00:00
zink: use the sanitized key in update_gfx_program_optimal()
this otherwise pulls in unused state values that are otherwise
sanitized away
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28017>
(cherry picked from commit 460c7eeecbd5439baeb86a3d3648b1c63afba0cf)
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ff466be7
by Mike Blumenkrantz at 2024-03-14T12:04:33+00:00
zink: always sync and replace separable progs even with ZINK_DEBUG=noopt
this otherwise breaks when shader variants are needed and aren't created
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28017>
(cherry picked from commit 5910ce4b86343cf92ddae6d9fd813eb2f8367bc8)
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b1065530
by Mike Blumenkrantz at 2024-03-14T12:04:33+00:00
zink: add even more strict checks for separate shader usage
this blocks e.g., shader object usage with sample shading which
cannot be used with current vk spec
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28017>
(cherry picked from commit 485b4d9abedfd747bc324d5b3858e5df3b38eec2)
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b71cae26
by Karol Herbst at 2024-03-14T12:04:34+00:00
nouveau: call glsl_type_singleton_init_or_ref earlier
Fixes: 91029b7e87b ("nouveau: take glsl_type ref unconditionally")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27853>
(cherry picked from commit 1a4c2cba956fe593a0fc09416bd8142a5a34423f)
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a38268cf
by Francisco Jerez at 2024-03-17T21:53:36+00:00
intel/eu/xe2+: Translate brw_reg fields in REG_SIZE units to physical 512b GRF units during codegen.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27165>
(cherry picked from commit 43c9620dbf169fd7a66f9d5a34ee95f3bd9a923a)
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9909b84f
by Caio Oliveira at 2024-03-17T21:53:36+00:00
intel/brw: Use helper to create accumulator register
This ensure the region triple <V,W,H> is set correctly, in this case the
desired region is a sequential like <8,8,1>. Without the helper the
sequence we get is <0,1,0> -- which the generator currently partially
adjusts when emitting code, but is not sufficient when doing validation
earlier.
The code generated code is slightly modified. From crucible test
func.shader.subtractSaturate.uint in the fragment shader for SIMD8, the
diff looks like
```
mov(8) acc0<1>UD g21<8,8,1>UD { align1 1Q $0.dst };
-add.sat(8) g22<1>UD -acc0<0,1,0>UD g16<8,8,1>UD { align1 1Q @1 $0.dst };
+add.sat(8) g22<1>UD -acc0<8,8,1>UD g16<8,8,1>UD { align1 1Q @1 $0.dst };
```
Note that without the patch generator adjusted the hstride for acc0 used
as destination (see brw_set_dest), but kept the src region as is. For
the source, it is not clear to me why the <0,1,0> would work correctly
here since it is a scalar, but using <8,8,1> it is correct.
Fixes: 58907568ec5 ("intel/fs: Add SHADER_OPCODE_[IU]SUB_SAT pseudo-ops")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28059>
(cherry picked from commit db8022dc4d30cc1dc2903f1a8be0b2354d406357)
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57d1d404
by Caio Oliveira at 2024-03-17T21:53:36+00:00
intel/brw: Fix validation of accumulator register
The `stride` and `offset` attributes are meaningful for the "virtual"
register files (VGRFs, UNIFORMs and ATTRs). Accumulator is an ARF so
validation should check `hstride` (part of the <V,W,H> triple) and `subnr`
instead.
Fixes: 12d7aaf2b82 ("intel/compiler: add more validation for acc register usage")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28059>
(cherry picked from commit e324fbbe68df870dede5a7b4efbd6528dd041de6)
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2832e9fe
by Lionel Landwerlin at 2024-03-17T21:53:36+00:00
anv: return unsupported for FSR images on Gfx12.0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28131>
(cherry picked from commit 2a77a46837f637c068dc1720b460f14e36ac182d)
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ebd28f22
by Eric Engestrom at 2024-03-17T21:55:33+00:00
.pick_status.json: Update to eac703f69128d5aa6879c9becbad627ce08a7920
-
95f7e7ce
by Mike Blumenkrantz at 2024-03-17T21:59:06+00:00
glx: only print zink failure-to-load messages if explicitly requested
if zink is inferred, let it fail silently
ref #10293
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27836>
(cherry picked from commit e4d45c582b445686b82fc47b4474aa27ca45a08b)
-
aaf2417c
by Corentin Noël at 2024-03-17T22:06:01+00:00
st_pbo/compute: Use the correct structure type when allocating a specialized key
Use pbo_spec_async_data instead of pbo_async_data.
Cc: mesa-stable
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28173>
(cherry picked from commit 812be09cd2095562617febc73e932d69389b056b)
-
ddbf64ab
by Lionel Landwerlin at 2024-03-17T22:06:03+00:00
anv: ignore descriptor alignment for inline uniforms
For this particular case only it doesn't matter. Fixes some new CTS
tests with small inline uniform sizes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28040>
(cherry picked from commit 20df1d2b1f85711732eb190cf373b56df573e36e)
-
3a8b733d
by Corentin Noël at 2024-03-17T22:10:55+00:00
zink: Make sure to initialize all the fields of VkMemoryBarrier
Fixes several random validation errors as the value of dstAccessMask could be
anything.
Cc: mesa-stable
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28166>
(cherry picked from commit e7de9ab62a5c5d9d9ec678475ee26871aab27086)
-
daf78a80
by Mike Blumenkrantz at 2024-03-17T22:11:00+00:00
zink: iterate all the modes when doing separate shader fixups
otherwise this might only do the inputs without also handling outputs
Fixes: 0a12cedec91 ("zink: add a special separate shader i/o mode for legacy variables")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28185>
(cherry picked from commit e931ef4884cc6eb910b7448309900c0d1ef53a4b)
-
fdf70bb8
by Jordan Justen at 2024-03-17T22:11:01+00:00
intel/compiler/fs: Restore SIMD32 restriction for ray_queries on Xe2
In 96e0d979a7b, the restriction was dropped because we don't compile a
SIMD8 program on Xe2. This change moves it to run_fs() so the
restriction will be added when compiling SIMD16 on Xe2.
Fixes: 96e0d979a7b ("intel/fs: Check fs_visitor instance before using it")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28191>
(cherry picked from commit 72d289b8d1491281a1c3011cdea78a6465546024)
-
bd8d5d19
by Friedrich Vock at 2024-03-17T22:11:02+00:00
radv: Only enable SEs that the device reports
Matches PAL behavior.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28195>
(cherry picked from commit cc61409ea6ae14cf4ceb8af4e98d847065693029)
-
65399c4d
by Friedrich Vock at 2024-03-17T22:11:03+00:00
radeonsi: Only enable SEs that the device reports
Matches PAL behavior.
Cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28196>
(cherry picked from commit 3f1cb470f0b634a7412cb229223ee7abdf4c6d97)
-
1d6cc85e
by Samuel Pitoiset at 2024-03-17T22:11:04+00:00
radv: disable binning correctly on GFX11.5
Ported from RadeonSI 20445f296bfcf3be40436617aad5d8378ad09bce
("radeonsi: disable binning correctly on gfx11.5").
Fixes: b44a886b84c ("amd/common: add registers for gfx11.5")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
(cherry picked from commit 8203284c036d780803c5a5e1b7ae931889ae903d)
-
a12c72fc
by Samuel Pitoiset at 2024-03-17T22:11:04+00:00
radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11
Ported from RadeonSI 7d3a414662ed4aaffd80762532a1c3c9f4cfc4f1
("radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT")
Fixes: 25a66477d02 ("radeonsi/gfx11: register changes")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
(cherry picked from commit d81809618f08e8d20ccd6a317078b5e0a08443a0)
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6358b96b
by Iván Briano at 2024-03-17T22:16:01+00:00
intel/cmat: fix stride calculation in cmat load/store
The stride given in the shader is in number of elements of the of the
type pointed by the given pointer, which may not match the matrix own
element type.
Since we cast the pointer to match the element type, the stride needs to
be ajusted accordingly.
v2:
- Fix mismatching bit-width in matrix element type and pointer type (Caio)
- Do the stride calculation in one place
Fixes dEQP-VK.compute.pipeline.cooperative_matrix.khr_*.multicomponent.*
Fixes: 3a35f8b29bb ("intel/cmat: Lower cmat_load and cmat_store")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10820
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27903>
(cherry picked from commit 446f652cde22a3292b0860c16efb9d28bf89e1a9)
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a006716a
by Marek Olšák at 2024-03-17T22:16:01+00:00
r300: port scanout pitch alignment from the DDX to fix DRI3
This wasn't needed with DRI2 because only the DDX allocates scanout
surfaces with DRI2.
Fixes: d779a5d16ae - r300g: cleanup texture creation code
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2780
Reviewed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28209>
(cherry picked from commit 58b773bd9a4c108ee7c2b8a1405f832fa147b13a)
-
75acf5c4
by Eric Engestrom at 2024-03-24T19:39:32+00:00
.pick_status.json: Update to 912e203a534be8b70b3ef8bf00294e9c962e385a
-
86436376
by Rhys Perry at 2024-03-24T23:04:53+00:00
aco: don't reuse misaligned attribute destination VGPRs in VS prologs
Since we split misaligned attributes, we could overwrite one of these
VGPRs in the middle of loading the attribute.
For example:
v_add_u32_e32 v4, vcc, s7, v1
s_waitcnt lgkmcnt(0)
buffer_load_dword v4, v4, s[32:35], 0 idxen
buffer_load_dword v5, v4, s[32:35], 0 idxen offset:4
can overwrite the vertex index in the load of the first component.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>
(cherry picked from commit ec892c4d2b6360efdae4e2dc9a23ce320b6aa1d6)
-
97ce8810
by David Rosca at 2024-03-24T23:04:53+00:00
radv/video: Set maxActiveReferencePictures to 16 for H264/5
H265 supports 16 reference frames too.
Fixes validation errors when decoding H265 stream with more than 8 reference
frames.
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27541>
(cherry picked from commit 4b7b185711548b955cf173d3fc2a425604922a79)
-
c9c61a2f
by Gert Wollny at 2024-03-24T23:04:53+00:00
nir-to-spirv: Cast SSBO input pointer when needed
Fixes validation error:
VUID-VkShaderModuleCreateInfo-pCode-08737
AtomicFAddEXT: expected Pointer to point to a value of type Result
Type
%51 = OpAtomicFAddEXT %float %49 %uint_1 %uint_0 %50
when running
spec@nv_shader_atomic_float@execution@ssbo-atomicadd-float
Fixes: 9f6be8effb43fcd4ce2fd00045bc6244ddf63529
zink: store and use alu types for ntv defs
v2: Fix commit message (Mike)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28243>
(cherry picked from commit 50a6c5d5fa3df34ec4e56cdbda1c833c3f7c1879)
-
1ef65115
by Konstantin Seurer at 2024-03-24T23:04:53+00:00
zink: Handle aoa derefs of images
Only the index of the inner array was used.
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28250>
(cherry picked from commit 995727e57501f7a35eb5e6797124f8ec3d6911a0)
-
c01e1566
by Samuel Pitoiset at 2024-03-24T23:04:53+00:00
radv: fix occlusion queries with MSAA and no attachments
The number of samples should be the rasterization samples and not the
framebuffer samples.
Fixes recent dEQP-VK.query_pool.occlusion_query.no_attachments_*.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28198>
(cherry picked from commit 9b089ca943cffc6fc0cc2a779da66add25bc135f)
-
721997fc
by Pierre-Eric Pelloux-Prayer at 2024-03-24T23:04:53+00:00
winsys/radeon: pass priv instead NULL to radeon_bo_can_reclaim
This fixes a NULL pointer issue.
Fixes: 4a078e693e9 ("r300,r600,radeon/winsys: always pass the winsys to radeon_bo_reference")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10613
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28240>
(cherry picked from commit 99017891cad55972c26c0ca8354f48e722b37a66)
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90575edf
by Samuel Pitoiset at 2024-03-24T23:04:53+00:00
radv: add radv_force_pstate_peak_gfx11_dgpu and enable it for Helldivers 2
This seems to definitely improve stability issues (random GPU hangs)
with Helldivers 2 on RDNA3 dGPUs. RDNA3 APUs and other generations
shouldn't be affected.
This is a workaround.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10584
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28260>
(cherry picked from commit 4d4b1820ca17b71acc56365d0488966e5d4ffa16)
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a2f3d6b4
by Lucas Stach at 2024-03-24T23:04:53+00:00
etnaviv: fix fixpoint conversion of negative values
The hand rolled etnaviv conversion functions were able to handle
negative input values when converting to fixpoint. By replacing
them with U_FIXED all negative values are clamped to zero, which
breaks usages where negative inputs are valid, like lodbias.
Fixes: 8bce68edf553 ("etnaviv: switch to U_FIXED(..) macro")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28224>
(cherry picked from commit 4b8981e4717259935ee4db2fe8b49648c174ebb9)
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e07d16f3
by Rhys Perry at 2024-03-24T23:04:53+00:00
radv: use dual_color_blend_by_location with Half-Life Alyx
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Ethan Lee <flibitijibibo@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10462
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28269>
(cherry picked from commit f88922e8161624e52bbeb7f918bee23f94b1aafd)
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be542ad9
by Mike Blumenkrantz at 2024-03-24T23:04:54+00:00
zink: do io fixup on patch variables too
fixes spec@arb_separate_shader_objects@rendezvous by location (5 stages)
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28296>
(cherry picked from commit f79557dd38db2fdf6fc1c009aec969508b69d50a)
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2e08bfb5
by Samuel Pitoiset at 2024-03-24T23:04:54+00:00
radv: add a workaround for null IBO on GFX6
Based on PAL.
Fixes dEQP-VK.draw.*nulldescriptor_maintenance_5_maintenance6 on GFX6.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28263>
(cherry picked from commit be4a6b946a1b6ce9805f839d71bc2ff28b0b4918)
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12ac7ecd
by Rhys Perry at 2024-03-24T23:04:54+00:00
aco/cssa: reset equal_anc_out if merging fails
try_merge_merge_set() expects equal_anc_out to be Temp() in the beginning,
so we need to reset it in case it's used again.
Fixes compilation of metro_exodus/163b3b895730d37b with
VK_PIPELINE_CREATE_2_DISABLE_OPTIMIZATION_BIT_KHR.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 18ba93e6732a ("aco/cssa: rewrite lower_to_cssa pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28248>
(cherry picked from commit 0c0819f0da49b38c980a8e4a42aca1e89d40b984)
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4f34ef90
by Paulo Zanoni at 2024-03-24T23:04:54+00:00
anv: don't leak device->vma_samplers
The vma_samplers vma heap is initialized unconditionally. Don't use
device->physical->indirect_descriptors as a condition on whether to
free it or not.
>From my TGL machine:
==373617== 32 bytes in 1 blocks are definitely lost in loss record 1 of 1
==373617== at 0x48459F3: calloc (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==373617== by 0x6926DC0: util_vma_heap_free (vma.c:339)
==373617== by 0x6925ED3: util_vma_heap_init (vma.c:53)
==373617== by 0x5334EDA: anv_CreateDevice (anv_device.c:3404)
==373617== by 0x685593A: vk_tramp_CreateDevice (vk_dispatch_trampolines.c:78)
==373617== by 0x48A6D56: terminator_CreateDevice (loader.c:5833)
==373617== by 0x9C2293F: vulkan_layer_chassis::CreateDevice(VkPhysicalDevice_T*, VkDeviceCreateInfo const*, VkAllocationCallbacks const*, VkDevice_T**) (chassis.cpp:497)
==373617== by 0x48B0690: loader_create_device_chain (loader.c:4937)
==373617== by 0x48B1327: loader_layer_create_device (loader.c:4317)
==373617== by 0x48B8D79: vkCreateDevice (trampoline.c:1004)
==373617== by 0x10CC7A: MyApp::MyApp(int, bool) (sparse.cpp:608)
==373617== by 0x1201E8: main (sparse.cpp:6025)
Fixes: 7c76125db25d ("anv: use 2 different buffers for surfaces/samplers in descriptor sets")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28303>
(cherry picked from commit 6ec1e322f0a9bb211fe0b9b6703f94bc35513cb9)
-
8428accd
by Patrick Lerda at 2024-03-24T23:04:54+00:00
ac/llvm,radeonsi: fix memory leaks triggered by ac_nir_translate() errors
For instance, this issue is triggered with
"piglit/bin/glslparsertest tests/spec/arb_bindless_texture/compiler/images/arith-bound-image.frag pass 3.30 GL_ARB_bindless_texture GL_ARB_shader_image_load_store":
Direct leak of 176 byte(s) in 1 object(s) allocated from:
#0 0x7f84c3fbe9a7 in calloc (/usr/lib64/libasan.so.6+0xb19a7)
#1 0x7f84ba7e0801 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4391
#2 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
#3 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
#4 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
#5 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
#6 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
#7 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#8 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a)
Direct leak of 136 byte(s) in 1 object(s) allocated from:
#0 0x7f84c3fbff57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
#1 0x7f84b1a5f749 in LLVMCreateBuilderInContext (/usr/local/lib64/libLLVM-17.so+0xc84749)
#2 0x7f84ba7817b0 in ac_llvm_context_init ../src/amd/llvm/ac_llvm_build.c:54
#3 0x7f84ba542b7a in si_llvm_context_init ../src/gallium/drivers/radeonsi/si_shader_llvm.c:120
#4 0x7f84ba542b7a in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:832
#5 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
#6 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
#7 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
#8 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#9 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a)
Indirect leak of 176 byte(s) in 1 object(s) allocated from:
#0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
#1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
#2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152
#3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232
#4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163
#5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186
#6 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381
#7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
#8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
#9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
#10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
#11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
#12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#13 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a)
Indirect leak of 176 byte(s) in 1 object(s) allocated from:
#0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
#1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
#2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152
#3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232
#4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163
#5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186
#6 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382
#7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
#8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
#9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
#10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
#11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
#12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#13 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a)
Indirect leak of 128 byte(s) in 1 object(s) allocated from:
#0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
#1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
#2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182
#3 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382
#4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
#5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
#6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
#7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
#8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
#9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#10 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a)
Indirect leak of 128 byte(s) in 1 object(s) allocated from:
#0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
#1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
#2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182
#3 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381
#4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
#5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
#6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
#7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
#8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
#9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#10 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a)
SUMMARY: AddressSanitizer: 920 byte(s) leaked in 6 allocation(s).
Fixes: d92d35c9db6d ("ac/llvm: add a return value to ac_nir_translate")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28099>
(cherry picked from commit 0fd907fc7b66cb4700c21761667d76565ef6fc38)
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0a04f001
by Mike Blumenkrantz at 2024-03-24T23:04:54+00:00
zink: defer present barrier to flush if a clear is pending
this otherwise submits the swapchain with the wrong layout
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
(cherry picked from commit 1670c40557ad5c6eb0deccddb2223896e2ec35ef)
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b0ada349
by Mike Blumenkrantz at 2024-03-24T23:04:54+00:00
zink: clamp swapchain renderarea instead of asserting
in a sequence like:
* resize A
* clear
* resize B
* clear
* resize C
* clear
for a swapchain resource, the geometry for a given op after the resize
may desync for the op with which it was executed, but this is fine
since the underlying swapchain object will have to be re-created anyway
fixes #10827
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
(cherry picked from commit ee13512a624153913e2789f31ab24aa925313fdd)
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2e028d7c
by Pierre-Eric Pelloux-Prayer at 2024-03-24T23:04:54+00:00
radeonsi: preserve alpha if needed in kill_ps_outputs_cb
Some features (eg: ALPHA_TEST) relies on the alpha value being
exported even if color_mask.a = false.
In these cases, override comp_mask to preserve the alpha value.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10841
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10845
Fixes: 6d2a7f53 ("radeonsi: decrease NUM_INTERP if export formats/colormask eliminated PS inputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28268>
(cherry picked from commit 53f9cdac9b15eb705fd8e7ba7e9bfed61a51c2e0)
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53ad33ce
by Rhys Perry at 2024-03-24T23:04:54+00:00
aco/gfx11: fix scratch ST mode assembly
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27913>
(cherry picked from commit 5651aa7644319843092ebbaa688a40e53ba16789)
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3e0fc344
by Matthew Waters at 2024-03-24T23:04:54+00:00
teximage: allow glCopyTex{Sub}Image[123]D into R/RG textures with OpenGL ES 2.0
This is explicitly allowed in the GL_EXT_texture_rg extension.
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28313>
(cherry picked from commit cf8f89492153cf0fa2ca5364cdbcf1b74925b3eb)
-
b75b707f
by Eric Engestrom at 2024-03-27T18:48:21+00:00
.pick_status.json: Update to c0875d21563257442fd91aab5740248b0fd96a5c
-
90dc45bc
by Philipp Zabel at 2024-03-27T19:06:01+00:00
rusticl: work around reference-to-mutable-static warnings
Creating mutable or shared references to mutable static variables is
discouraged, but still possible by taking a detour to a raw pointer
via the addr_of! / addr_of_mut! macros.
For details, see: https://github.com/rust-lang/rust/issues/114447
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10887
Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28415>
(cherry picked from commit f4199a9b21951533625461ec5773e6bb50aa782d)
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21e95719
by Samuel Pitoiset at 2024-03-27T19:06:37+00:00
radv: invalidate L2 metadata for VK_ACCESS_2_MEMORY_READ_BIT
When shaders might read metadata (DCC) this must be flushed.
VK_ACCESS_2_MEMORY_READ_BIT includes all READ bits that are relevant.
I think this issue has been uncoverd since vkd3d-proton d1425ee4
("vkd3d: Use VK_ACCESS_MEMORY_{READ,WRITE}_BIT where appropriate")
because RADV used to be missing VK_ACCESS_2_MEMORY_{READ,WRITE} in the
past and vkd3d-proton added a special workaround that has been removed.
This fixes some DCC corruption in WWE 2K24.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10774
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28332>
(cherry picked from commit 585b4c5a010442e07d37e9ce69528c997d43f293)
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27c7c507
by Ruijing Dong at 2024-03-27T19:07:22+00:00
radeonsi/vcn: add enc surface alignment caps
set [64x16] as the alignment for hevc
encoding surface.
Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
(cherry picked from commit 7525d2242bd70ee4acbcb9507286593a935f64e8)
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aade4643
by Ruijing Dong at 2024-03-27T19:07:24+00:00
frontends/va: add surface alignment attribute
It is only taking effect in hevc encoding so far.
Cc: mesa-stable
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
(cherry picked from commit b24748a93ab164c5c5884e49974de0902a42c3be)
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465e9bd9
by Ruijing Dong at 2024-03-27T19:07:26+00:00
radeonsi/vcn: update to use correct padding size.
Update padding size calculation to use cropping.
Original method could result in 0 padding, which
generated unnessary noise in the encoding result.
Cc: mesa-stable
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9196
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
(cherry picked from commit fecbb4177c63e2df91aa72798d2668bf42c0e6e9)
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cd6b71cd
by Faith Ekstrand at 2024-03-27T19:07:27+00:00
nir/builder: Correctly handle decl_reg or undef as the first instruction
These are both handled by inserting them directly at the top of the
nir_function_impl. However, if the cursor is already at the top, it
never gets updated so we end up inserting other stuff after the newly
inserted undef or decl_reg. It's an odd edge case to be sure but I hit
it with my new NIR CF pass for NAK.
Fixes: 1be4c61c957d ("nir/builder: Add a helper for creating undefs")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
(cherry picked from commit a782809f81dc32079691b3a280580dbf7b800dba)
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32c80c96
by Faith Ekstrand at 2024-03-27T19:07:29+00:00
nir/gather_types: Support unstructured control-flow
This fixes nir_print for unstructured control-flow. It's safe to
backport just this patch because the worst case is that we don't set as
many types and not as much gets printed.
Fixes: 260a9167db54 ("nir/print: Improve NIR_PRINT=print_consts by using nir_gather_ssa_types()")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28300>
(cherry picked from commit 2be97717e696d70ce3153e8e2f54e5b20e1d51d2)
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31be238f
by Boris Brezillon at 2024-03-27T19:08:23+00:00
panvk: Disable global offset on varying and non-VS attribute descriptors
We are not supposed to apply the vertex index offset to our varying or
non-VS attribute (AKA image) descriptors. While at it, explicitly set
offset_enable to true when emitting vertex attribute descriptors, to
clarify our intentions.
Fixes: c0d65398279d ("panvk: Drop support for Midgard")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28182>
(cherry picked from commit d9d6514fbccd05343e3f7cc48a8d07218b9c28ef)
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cdfe4171
by Yusuf Khan at 2024-03-27T19:18:44+00:00
nvk: fix valve segfault from setting a descriptor set from NULL
Reported by Nikita Vilunov and fix found by him when analyzing his
CS2 dump.
cc: mesa-stable
v2: these two need to be zero when set == NULL
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10719
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28353>
(cherry picked from commit 561fae6845479b81d8f41f23376c469524004166)
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7c6ea901
by Lionel Landwerlin at 2024-03-27T19:33:04+00:00
blorp: handle a few allocation failure cases
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28387>
(cherry picked from commit 1d7c38a5def7f6f8b4441ca60780ddb78b4c5216)
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0edfbaaf
by Lionel Landwerlin at 2024-03-27T19:33:04+00:00
anv: fix block pool allocation failure
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28387>
(cherry picked from commit 0264fc688f08e4720090b85216e1cfa5a552dc85)
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acee5427
by Lionel Landwerlin at 2024-03-27T19:33:04+00:00
anv: fix bitfield checks in gfx runtime flushing
s/SET/TEST/
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28387>
(cherry picked from commit 601d2192573d15f24244af95906d1f08e3d624aa)
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9900dc15
by Gert Wollny at 2024-03-27T19:33:04+00:00
nir_to_spirv: Allow LOD for external images
External images translate to 2D images in ntv, so we will have to emit
OpImageQuerySizeLod instead of OpImageQuerySize (thanks Faith for
pointing that out). This quells
VUID-VkShaderModuleCreateInfo-pCode-08737
Image must have either 'MS'=1 or 'Sampled'=0 or 'Sampled'=2
%32 = OpImageQuerySize %v2int %31
triggred by piglit
spec@oes_egl_image_external_essl3@oes_egl_image_external_essl3
on Zink.
Fixes: 3f783a3c507e16bffb2e460484fbf65eb11ba826
zink: omit Lod image operand in ntv when not using an image texture dim
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28389>
(cherry picked from commit b6c1390354bbcb99687fa60774697cfa90b5f271)
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f942a506
by Charlie Turner at 2024-03-27T19:33:04+00:00
{vulkan,radv,anv}/video: fix issue in H264 scaling lists derivation
Originally was trying to copy a pps's scaling list when an sps's was
signaled.
Fixes: 8daa32963 ("vulkan/video: add helper to derive H264 scaling lists")
Signed-off-by: Charlie Turner <cturner@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28352>
(cherry picked from commit 9e3932e99018bbb3ae0ae716bd7d9f53fcebf698)
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0bc81390
by Kenneth Graunke at 2024-03-27T19:33:04+00:00
intel/brw: Fix opt_split_sends() to allow for FIXED_GRF send sources
opt_copy_propagation() can sometimes propagate FIXED_GRF sources into
SHADER_OPCODE_SENDs as the message payload. For example, GS input
reads, which simply take a URB handle and have the offset in the
descriptor. For non-VGRFs, there isn't a payload to split, so just
skip past such send messages.
Fixes: 589b03d02f0 ("intel/fs: Opportunistically split SEND message payloads")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28067>
(cherry picked from commit ba11127944d898581eab17dc76ea56372b97d0bd)
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25dac7bc
by Dave Airlie at 2024-03-27T19:33:04+00:00
radv/video: fix h265 decode with unaligned w/h
This is similiar to the h264 fix done previously.
Fixes decoding with the nvpro samples app and a test video.
Fixes: db62c38091a3 ("radv: add vcn h265 decode.")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28359>
(cherry picked from commit 4fc2ab43c0004a972a36685a845d12d38064281c)
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ea5e99da
by Eric Engestrom at 2024-03-27T21:44:22+00:00
docs: add release notes for 24.0.4
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bb6a55b7
by Eric Engestrom at 2024-03-27T21:45:03+00:00
VERSION: bump for 24.0.4
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88c9222e
by Timo Aaltonen at 2024-03-29T17:15:26+02:00
Merge branch 'upstream-unstable' into debian-unstable
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ed91278b
by Timo Aaltonen at 2024-03-29T17:15:54+02:00
version bump
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8dd70bf1
by Timo Aaltonen at 2024-03-29T17:45:01+02:00
patches: Dropped upstreamed patches.
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21ff0b34
by Fabio Pedretti at 2024-03-29T17:54:28+02:00
control: libllvmspirvlib-*-dev is needed even with rusticl disabled (Closes: #1061287)
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59bf634d
by Fabio Pedretti at 2024-03-29T17:54:31+02:00
control: Bump meson build-dep
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cd9e6d47
by Timo Aaltonen at 2024-03-29T18:00:21+02:00
release to sid