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[Git][xorg-team/lib/mesa][debian-unstable] 85 commits: docs: add sha256sum for 23.1.6



Title: GitLab

Timo Aaltonen pushed to branch debian-unstable at X Strike Force / lib / mesa

Commits:

  • d16943e3
    by Eric Engestrom at 2023-08-16T20:34:16+01:00
    docs: add sha256sum for 23.1.6
    
  • d3459561
    by Eric Engestrom at 2023-08-18T11:34:50+01:00
    .pick_status.json: Update to 9d442b459a43264c28994e65dcaacfe303feedd1
    
  • 6db94e35
    by Eric Engestrom at 2023-08-18T11:37:42+01:00
    .pick_status.json: Mark aebe58458611e0bb585a5bce8e16c1175783f3cc as denominated
    
  • 39da24e5
    by Matt Turner at 2023-08-18T11:39:23+01:00
    Revert "intel/fs: only avoid SIMD32 if strictly inferior in throughput"
    
    This reverts commit 6b494745be0900a67004d6f3e4b730c3cd67da79.
    
    The logic is not entirely correct: the comparison is between two
    static-analysis estimates of a dynamic system with variables that aren't
    captured by the shader source, so using ">" will always have greater potential
    to cause regressions whenever the performance difference between the two builds
    is something not captured by the static model, no matter how much the model is
    improved.
    
    Reference: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9262
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24615>
    (cherry picked from commit d142c845d05732f7858839493e0dba6a1fa5d6c0)
    
  • 71c80cd5
    by Rhys Perry at 2023-08-18T11:39:24+01:00
    radv: disable 64-bit color attachments
    
    These work in some circumstances (dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc),
    but I'm not sure if they work in all, blending certainly doesn't work and
    this probably wasn't intended in the first place.
    
    Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
    Fixes: 01bd012edd20 ("amd: fix 64-bit integer color image clears")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
    (cherry picked from commit 405f3bf9903f8a8b65da113adc9ef32e02b84fa2)
    
  • 86433882
    by Rhys Perry at 2023-08-18T12:08:35+01:00
    radv: fix 128bpp comp-to-single clears
    
    We were clearing GB to A, instead of R.
    
    This fixes some red tinting in Overwatch 2 when shadow quality is set to
    "Ultra".
    
    Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
    Fixes: 7451eb1d6112 ("radv: implement DCC fast clears with comp-to-single")
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9446
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
    (cherry picked from commit e2c7ce37192cef693c7a228b997402d480674a0a)
    
  • 126b2e89
    by Faith Ekstrand at 2023-08-18T12:08:46+01:00
    nir: Fix nir_op_mov handling in nir_collect_src_uniforms
    
    For mov we need to follow the swizzle for the destination component, not
    grab swizzle[0] for some random source.
    
    Fixes: a406fff78a57 ("nir/inline_uniforms: support vector uniform")
    Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
    (cherry picked from commit 9bcc9597a5bb82f2013ea70bc8daa0bfd233b4c3)
    
  • 3de303c2
    by Faith Ekstrand at 2023-08-18T12:08:46+01:00
    nir: Handle nir_op_mov properly in opt_shrink_vectors
    
    If the opcode is a mov, it falls into the nir_alu_src_is_trivial_ssa
    case, not the vec case.
    
    Fixes: 94eff7ccd866 ("nir: shrink phi nodes in nir_opt_shrink_vectors")
    Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
    (cherry picked from commit f9a17c6fef92b1316c9a06465712e094f33add68)
    
  • e115eece
    by Faith Ekstrand at 2023-08-18T12:08:46+01:00
    nir: Don't handle nir_op_mov in get_undef_mask in opt_undef
    
    It's unnecessary because earlier parts of the pass will ensure that a
    mov of undef is turned into an undef.  It's also wrong because
    nir_op_mov has different semantics from nir_op_vecN when it comes to how
    sources map to destination components.
    
    Fixes: 5f26c21e6246 ("nir: Expand opt_undef to handle undef channels in a store intrinsic")
    Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
    (cherry picked from commit 408929289aadaf44e57ef60cb7c1ace4958199c7)
    
  • dd15752c
    by Mike Blumenkrantz at 2023-08-18T12:08:46+01:00
    vk/graphics: fix CWE handling with DS3
    
    VkPipelineColorBlendStateCreateInfo::attachmentCount cannot be used to
    generate the CWE mask since it cannot be read if enough dynamic state is in use
    
    instead just pass the max mask and let drivers figure it out
    
    cc: mesa-stable
    
    Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24673>
    (cherry picked from commit 0fb9064231687ff7af4cb48697ee24b48715b80f)
    
  • 0d1f0b2a
    by Emma Anholt at 2023-08-18T12:08:46+01:00
    freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads.
    
    We don't emit tex descriptors for the SSBOs, so if we took this path we'd
    fault.
    
    Fixes: 75eb0d2891c2 ("freedreno/ir3: Allow isam for non-bindless ssbo loads")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24682>
    (cherry picked from commit 5a8672952aeab60c8abf727cbc606ef8cd014b43)
    
  • cb1ac95e
    by Karol Herbst at 2023-08-18T12:08:46+01:00
    rusticl/kernel: optimize nir between lowering io and explicit types
    
    This is required to get rid of unneeded memory operations, like direct
    scratch stores/loads to the same location.
    
    Fixes: 66c6061491a ("rusticl/kernel: get rid of initial function_temp type lowering")
    Signed-off-by: Karol Herbst <git@karolherbst.de>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24734>
    (cherry picked from commit cc2f59d840bb3a6d9327ae9d4e0b868911da4fbc)
    
  • 8c06445a
    by Eric Engestrom at 2023-08-18T12:11:02+01:00
    .pick_status.json: Update to 61dd0ff97d8d670e1b7dfea8a37e73b67a7f5ff3
    
  • 2f956ef0
    by Emma Anholt at 2023-08-18T12:11:10+01:00
    disk_cache: Disable the "List" test for RO disk cache.
    
    It uses a poll function that waits for a second hoping for another thread
    to catch up, which is not a reliable way to do synchronization.  The test
    has been spuriously failing merges on a regular basis recently.
    
    This is issue #9222, which I'm leaving open until the author can fix the test.
    
    Fixes: 3b69b67545b6 ("util/fossilize_db: add runtime RO foz db loading via FOZ_DBS_DYNAMIC_LIST")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24755>
    (cherry picked from commit 4dfd306454a4653a8c0b0a37a3e6bb1632abfc9e)
    
  • 20f82b28
    by Karol Herbst at 2023-08-18T12:11:11+01:00
    nv50: limit max code uploads to 0x8000
    
    I have no idea why a bigger size doesn't work, the hardware doesn't
    complain, but it turns out that uploading big shaders still causes issues
    with the old limit. *shrug*
    
    Fixes: 7f63d2ebdbc ("nv50: fix code uploads bigger than 0x10000 bytes")
    Signed-off-by: Karol Herbst <git@karolherbst.de>
    Reviewed-by: M Henning <drawoc@darkrefraction.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24758>
    (cherry picked from commit 3e0cd6dfb9b5c87ad18c3576017c6cc5c7f240a0)
    
  • 3ee2a15f
    by Eric Engestrom at 2023-08-24T16:33:38+01:00
    .pick_status.json: Update to 5fa9f842b09694a91310640ae949327a74d1bcd2
    
  • d42f6ee8
    by David Heidelberg at 2023-09-04T11:30:23+01:00
    ci: disable Material Testers.x86_64_2020.04.08_13.38_frame799.rdc trace
    
    This change will be revert as soon, as Collabora proxy gets fixed.
    
    Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24819>
    (cherry picked from commit 6079c3ca49925b0b713ae5517a7650ddc4a206ad)
    
  • 96cf78be
    by Sviatoslav Peleshko at 2023-09-04T11:30:23+01:00
    dri: Use RGB internal formats for RGBX formats
    
    These formats do not contain alpha channel, so their internal formats
    should reflect that.
    
    Fixes: bf576772 ("dri_util: add driImageFormatToSizedInternalGLFormat function")
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9429
    Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
    Reviewed-by: Daniel Stone <daniels@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24580>
    (cherry picked from commit e62f2c48a0836495381b38b3ab055b0787545de4)
    
  • 5d64fe2e
    by Faith Ekstrand at 2023-09-04T11:30:23+01:00
    nir: Fix metadata in nir_lower_is_helper_invocation
    
    It does not preserve everything.  It adds and removes instructions and
    even adds a variable.
    
    Fixes: f17b41ab4f01 ("nir: add lowering pass for helperInvocationEXT()")
    Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24760>
    (cherry picked from commit 831085afa3f68cef851dca7e50f979a375dab548)
    
  • 523d3556
    by Eric Engestrom at 2023-09-04T11:30:23+01:00
    vc4: drop duplicate .lower_ldexp
    
    It's set 3 lines above already.
    
    Fixes: 2a33ea95d66cd7ba83e2 ("glsl: Retire ldexp lowering in favor of the nir lowering flag.")
    Signed-off-by: Eric Engestrom <eric@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24786>
    (cherry picked from commit af28356de06d7b5adfa3fa87dac157021c3a68a9)
    
  • d7c15358
    by Eric Engestrom at 2023-09-04T11:30:23+01:00
    zink: fix format in zink_make_{image,texture}_handle_resident()
    
    `ds->db.format` is a `pipe_format`, while `buffer_infos[handle].format` is
    a `VkFormat`; the conversion from one to the other was missing.
    
    Fixes: 99ba529feed6f9917a44 ("zink: implement descriptor buffer handling of bindless texture")
    Signed-off-by: Eric Engestrom <eric@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24790>
    (cherry picked from commit ab0f0d1563365ea29175bd0b07ba34e1f96c9999)
    
  • 4d648286
    by Eric Engestrom at 2023-09-04T11:30:23+01:00
    .pick_status.json: Mark 04ba4059b7243fb9258df12154ce1e7a01e019c8 as denominated
    
  • 2269e32b
    by Eric Engestrom at 2023-09-04T11:30:24+01:00
    .pick_status.json: Mark fe4208ed4c9a08c7963caa287ae34e9357de68af as denominated
    
  • 30043964
    by Alyssa Rosenzweig at 2023-09-04T11:30:24+01:00
    nir/passthrough_gs: Fix array size
    
    Triangle strips with adjacency have 6 vertices input, so we need an array big
    enough for all 6 vertices to avoid overflow. Fixes passthrough GS generated for
    KHR-GLES31.core.draw_indirect.basic-mode-*-triangle*adj*.
    
    Fixes: ea14579f3dc ("nir: handle primitives with adjacency")
    Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Reviewed-by: Antonino Maniscalco <antonino.maniscalco@collabora.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24780>
    (cherry picked from commit 558e36f64196ec734e4c7502db491f56f76118cd)
    
  • c0d09600
    by Eric Engestrom at 2023-09-04T11:30:24+01:00
    v3dv: fix VK_PIPELINE_ROBUSTNESS_{BUFFER,IMAGE}_BEHAVIOR_DEVICE_DEFAULT_EXT copy/paste typo
    
    Fixes: 24d9a80247605ac2c237 ("v3dv: implement VK_EXT_pipeline_robustness")
    Signed-off-by: Eric Engestrom <eric@igalia.com>
    Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24787>
    (cherry picked from commit 4dc0cb1ebea1cc8f9e1b46bb38dd21cdf2643437)
    
  • 5794559a
    by Eric Engestrom at 2023-09-04T11:30:24+01:00
    v3dv: fix copy/pasted type of `sample`
    
    And use the type in functions instead of a generic `uint32_t` to make it
    easier to notice the wrong type.
    
    Fixes: 47e02a2ef11237cf4c2c ("v3dv: add a fast path for vkCmdClearAttachments")
    Signed-off-by: Eric Engestrom <eric@igalia.com>
    Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24787>
    (cherry picked from commit ae0cb0b998fb772fc76226d9b85b21c1fadea448)
    
  • b027b459
    by Eric Engestrom at 2023-09-04T11:30:24+01:00
    v3dv: fix shader stage name in error message
    
    Fixes: 60145629a2bdcd4e7835 ("v3dv: initial CreateGraphicsPipeline/DestroyPipeline implementation")
    Signed-off-by: Eric Engestrom <eric@igalia.com>
    Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24787>
    (cherry picked from commit 8a1f3d0d73f0908d679bf8a97bafcb2dbc4661fd)
    
  • 761eab9c
    by Eric Engestrom at 2023-09-04T11:30:24+01:00
    v3d/qpu: fix type of function argument
    
    Fixes: 05c7d9715b8a419fd6fb ("broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.")
    Signed-off-by: Eric Engestrom <eric@igalia.com>
    Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24787>
    (cherry picked from commit 953ac9da7949a7d2333680aa77ff20288a247f19)
    
  • f141107a
    by Samuel Pitoiset at 2023-09-04T11:30:24+01:00
    Revert "radv/amdgpu: workaround a kernel bug when replacing sparse mappings"
    
    This workaround was added temporarily but it can actually cause
    stuttering in some games like Forza Horizon 5.
    
    The kernel fix
    (https://lists.freedesktop.org/archives/amd-gfx/2023-June/094648.html)
    landed in some stable kernels (5.15.121+, 6.1.40+ and 6.4.5+). Sadly,
    older stable kernels don't have it, so you might experiment random GPU
    hangs in games that use sparse mapping. Please ensure your kernel is
    up-to-date for the best experience.
    
    This reverts commit 9b00867327c2b266fcdebcef8bc7e7497eaab06b.
    
    Cc: mesa-stable
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9443
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24774>
    (cherry picked from commit f67eb9ce07e6b19fa5cae6f14551094bf236765b)
    
  • fd6bcc53
    by Samuel Pitoiset at 2023-09-04T11:30:24+01:00
    Revert "radv/amdgpu: skip adding per VM BOs for sparse during CS BO list build"
    
    This reverts commit 51caece74cd54e99a5f89521e8feacd894781ca2.
    
    Cc: mesa-stable
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24774>
    (cherry picked from commit e3fae0173005801ba39d50de3944bc6113e2a624)
    
  • 4e203b40
    by Tatsuyuki Ishi at 2023-09-04T11:30:24+01:00
    radv/amdgpu: Do not pass in a BO handle when clearing PRT VA region.
    
    This field is invalid to access for virtual BOs.
    
    Fixes: a931d5a4a4d ("radv/winsys: clear the PRT VA range when destroying a virtual BO")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24805>
    (cherry picked from commit 6c5512568b18e5c16f695c9d4d2dd862dc3c54f8)
    
  • 23e098db
    by Mike Blumenkrantz at 2023-09-04T11:30:24+01:00
    zink: wait on async fence during ctx program removal
    
    removed=true implies that no async jobs are outstanding
    
    fixes #9580
    
    cc: mesa-stable
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24811>
    (cherry picked from commit ca987c0dfb97d22d3cf2632f38d9d749162767b0)
    
  • 81ad2e61
    by Chia-I Wu at 2023-09-04T11:30:24+01:00
    ac/surface: limit RADEON_SURF_NO_TEXTURE to color surfaces
    
    For z surfaces, flags.texture should be based on
    RADEON_SURF_TC_COMPATIBLE_HTILE alone.  Otherwise, addrlib could pick a
    _X/_T swizzle mode for a MSAA depth texture, which is said to be broken:
    
      When _X/_T swizzle mode was used for MSAA depth texture, TC will get zplane
      equation from wrong address within memory range a tile covered and use the
      garbage data for compressed Z reading which finally leads to corruption.
    
    Fixes: de0885cdb89 ("amd/surface: add RADEON_SURF_NO_TEXTURE flag")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24767>
    (cherry picked from commit e74c3dbb70706f1a2bcf863b5058295fcd456ae4)
    
  • 8d9aeaaa
    by Marek Vasut at 2023-09-04T11:30:24+01:00
    etnaviv: Fully replicate back stencil config
    
    The blob replicates both the value mask as well as the stencil reference
    of the back-facing stencil to the front-facing stencil. This fixes the
    remaining failures in the following dEQPs:
    
       dEQP-GLES2.functional.fbo.render.*_stencil_index8
    
    Fixes: c8ccd63911d ("etnaviv: Fix depth stencil ops on GC880/GC2000")
    Signed-off-by: Marek Vasut <marex@denx.de>
    Acked-by: Lucas Stach <l.stach@pengutronix.de>
    Acked-by: Christian Gmeiner <cgmeiner@igalia.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4867>
    (cherry picked from commit ef4cb2431d4c2df402ae1036aa773a38fbc478d7)
    
  • 59a25fc8
    by Friedrich Vock at 2023-09-04T11:30:24+01:00
    nir/load_store_vectorize: Handle intrinsics with constant base
    
    This includes nir_load_stack and nir_store_stack, which are vectorized
    in nir_lower_shader_calls. If not adjusted, we end up loading from
    the wrong base.
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9596
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9587
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24789>
    (cherry picked from commit a28ff7f2405a4ddd0bcc309af252520e342b7ffe)
    
  • c1dae7d2
    by Daniel Schürmann at 2023-09-04T11:30:25+01:00
    nir/opt_move: fix handling of if-condition
    
    By accident, this used the parent of the nir_src which is a nir_if
    instead of the parent of the SSA value.
    
    Totals from 10814 (8.10% of 133461) affected shaders: (GFX11)
    Instrs: 21759185 -> 21757190 (-0.01%); split: -0.02%, +0.01%
    CodeSize: 112320272 -> 112316008 (-0.00%); split: -0.02%, +0.01%
    SpillSGPRs: 11220 -> 11212 (-0.07%)
    SpillVGPRs: 911 -> 903 (-0.88%); split: -1.54%, +0.66%
    Latency: 258334759 -> 258316073 (-0.01%); split: -0.02%, +0.01%
    InvThroughput: 31428650 -> 31426394 (-0.01%); split: -0.02%, +0.01%
    VClause: 309119 -> 309090 (-0.01%); split: -0.01%, +0.01%
    SClause: 657028 -> 657150 (+0.02%); split: -0.03%, +0.04%
    Copies: 1434209 -> 1432420 (-0.12%); split: -0.28%, +0.15%
    Branches: 481804 -> 481801 (-0.00%)
    PreSGPRs: 829995 -> 829966 (-0.00%)
    PreVGPRs: 758249 -> 758253 (+0.00%)
    
    Fixes: 8a78706643ecad8a1f303cc9358873abc29978b4 ('nir: refactor nir_opt_move')
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24695>
    (cherry picked from commit 7e246f7f2bde0c859269c4b81505bd0887045e7b)
    
  • 9dd36706
    by Mike Blumenkrantz at 2023-09-04T11:30:25+01:00
    zink: don't start multiple cache jobs for the same program
    
    if there's already a cache job in flight then starting a second one
    is illegal
    
    cc: mesa-stable
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24831>
    (cherry picked from commit d5157356ceffad6161ccc773cd6a3a9219f6b4e0)
    
  • 7c043d68
    by Rhys Perry at 2023-09-04T11:30:25+01:00
    aco: fix p_bpermute_gfx6 with input at non-zero byte
    
    Same as the other bpermute pseudo instructions.
    
    Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
    Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24693>
    (cherry picked from commit 85957dd6e5572dfe424f6fca2ca7a04e95084191)
    
  • e4f5c03f
    by Georg Lehmann at 2023-09-04T11:30:25+01:00
    aco: fix u2f16 with 32bit input
    
    The vulkan spec says all conversions are correctly rounded, so if the input
    is larger than the largest fp16 value, we need to return MAX_FLOAT/inf
    instead of cutting off the msbs.
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24826>
    (cherry picked from commit 6d949e18fd514ef386a9fce6710ca8e275778ddd)
    
  • b15f54d0
    by Tapani Pälli at 2023-09-04T11:30:25+01:00
    mesa: fix some TexParameter and SamplerParameter cases
    
    EXT extension was added without tests so these functions did
    not work properly.
    
    Fixes: 799710be889 ("mesa: Add EXT_texture_mirror_clamp_to_edge to extension table")
    Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
    Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24845>
    (cherry picked from commit d65fe6eff1fbba390d885c84630a96be37ea76a0)
    
  • b1ef60d9
    by Jordan Justen at 2023-09-04T11:30:25+01:00
    intel/dev: Use RPL-U name on RPL-U devices
    
    Ref: https://patchwork.freedesktop.org/patch/553646/?series=122712&rev=1
    Cc: mesa-stable
    Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
    Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24820>
    (cherry picked from commit 27f6b4b1c663108967a76b33db9e076c415484df)
    
  • bfff34a4
    by Jordan Justen at 2023-09-04T11:30:25+01:00
    intel/dev: Add more RPL PCI IDs
    
    Ref: https://patchwork.freedesktop.org/patch/553646/?series=122712&rev=1
    Cc: mesa-stable
    Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
    Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24820>
    (cherry picked from commit d65b0b042476f1fa785b93991dba338d1071f880)
    
  • 8389e5da
    by Sviatoslav Peleshko at 2023-09-04T11:30:25+01:00
    intel/isl: Don't over-allocate CLEAR_COLOR size to use whole cache line
    
    At the time this was added to fix some test failures. But it seems that
    the failures were happening due to missing cache flushes, so
    this extra space is no longer neccessary.
    
    Fixes: 37b4eacc ("intel/isl: Resize clear color buffer to full cacheline")
    Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
    Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24768>
    (cherry picked from commit caa5c23e481457bc0d717c758b9c90bf73cbce9e)
    
  • 612d6508
    by Eric Engestrom at 2023-09-04T11:30:25+01:00
    .pick_status.json: Update to 939845e424da7b2433902a9954cb6b615cd06d41
    
  • d98e8c09
    by Eric Engestrom at 2023-09-04T11:30:25+01:00
    .pick_status.json: Mark 5d19a0a19ba2ffe50a7d05fcf0ff17e0078c2d8e as denominated
    
  • ea31da6e
    by Eric Engestrom at 2023-09-04T11:30:25+01:00
    .pick_status.json: Mark 9865e5dff49395543da4331a943ba5a03ce6a413 as denominated
    
  • 117130be
    by Dmitry Baryshkov at 2023-09-04T11:30:25+01:00
    tu: Pass real size of prime buffers to allocator
    
    The msm driver reserves the actual DMABUF size in the memory map, while
    TU can request smaller memory chunk to be allocated. This potentially
    can lead to a situation when next allocation IOVA will be in the middle
    of the address space which is reserved for the DMABUF. Pass the
    `real_size' to TU allocator instead, so that kernel and userspace have
    the same picture of memory allocations.
    
    Cc: mesa-stable
    Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24861>
    (cherry picked from commit 2fdcc00b0154cb094a5fd2c9253904fc9073d96e)
    
  • 059ae38c
    by Kenneth Graunke at 2023-09-04T11:30:26+01:00
    iris: Check prog[] instead of uncompiled[] for BLORP state skipping
    
    Huge thanks to Tapani Pälli for debugging this issue, figuring out
    what was going wrong, proposing fixes, and walking me through where
    things were going off the rails.
    
    BLORP always disables tessellation and geometry shaders.  Our handling
    tried to look at ice->shaders.uncompiled[] to determine whether the next
    draw needed those shaders.  If not, we can leave BLORP's residual state
    that disabled those stages in place, and skip looking at it.
    
    Unfortunately, predicting the future is a bit fraught, in part due to
    the uncompiled[] and prog[] arrays being slightly out of sync at times.
    
    Consider the following case:
    
    1. Draw with tessellation shaders in place
    
       => uncompiled[TES] and prog[TES] will both point at valid shaders.
    
    2. Gallium calls pipe->bind_tes_state(NULL).
    
       => This makes uncompiled[TES] point at NULL, and flags
          IRIS_STAGE_DIRTY_UNCOMPILED_TES.
    
          Because iris_update_compiled_shaders() hasn't happened yet,
          uncompiled[TES] is NULL but prog[TES] has the stale TES from
          the previous draw still.
    
    3. BLORP operations happen
    
       => BLORP sees uncompiled[TES] == NULL and decides that tessellation
          is off for the upcoming draws.  So it skips flagging tess state.
    
    4. Gallium calls pipe->bind_tes_state(shader from step #1).
    
       => uncompiled[TES] points at the original shader.
          IRIS_STAGE_DIRTY_UNCOMPILED_TES gets flagged again.
    
    5. Draw again
    
       => This calls iris_update_compiled_shaders(), which sees that
          a TES is bound, and calls iris_update_compiled_tes().  But
          because the same shader was bound as before, the program it
          comes up with is identical to the one already bound at
          ice->shaders.prog[TES].  So, it thinks it doesn't have to
          flag any tessellation state dirty because it was already
          set up for the last draw.
    
    This random unbind and rebind between draws leads to a situation
    where, at step #3, BLORP thinks it can skip flagging tessellation
    state (nothing is bound), and at step #5, normal state handling
    thinks it can skip flagging tessellation state (nothing changed
    since last time).  So nobody does, and things break.
    
    This unbind appears to be happening when st_release_variants()
    decides it wants to free some shaders.  Then a rebind happens to
    put back the actual shader for the draw.  So, it's not theoretical.
    
    To fix this, we change BLORP to look at ice->shaders.prog[] rather
    than uncompiled[].  This is equivalent to thinking about the previous
    draw, rather than the next.  If the last draw had tessellation off,
    then BLORP's disabling was a no-op, and the GPU is still in the same
    state as the previous draw.  This is more reliable than predicting
    the future.
    
    Cc: mesa-stable
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8308
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9678
    Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24880>
    (cherry picked from commit d693027a00fe5f2cf2b9548b69b50078ec0113be)
    
  • 46378419
    by Eric Engestrom at 2023-09-06T16:16:56+01:00
    .pick_status.json: Update to 3a949de28c42d8714320e56bd99168148503da7d
    
  • dfe1857e
    by Paul Gofman at 2023-09-06T16:17:07+01:00
    driconf: add a workaround for Rainbow Six Extraction
    
    CC: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24784>
    (cherry picked from commit 3e66eba59e6617d51d8315727e3adf41b42b56f7)
    
  • ddf78b24
    by Timothy Arceri at 2023-09-06T16:17:10+01:00
    util: add radeonsi workaround for Nowhere Patrol
    
    Cc: mesa-stable
    
    Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24919>
    (cherry picked from commit ddac37a8b3bc9e199887dfd9ead2ccadefa34e55)
    
  • b5d66e01
    by Rhys Perry at 2023-09-06T16:17:15+01:00
    aco/spill: skip p_branch in process_block
    
    Fixes compilation of a Dead by Daylight shader.
    
    fossil-db (gfx1100):
    Totals from 58 (0.04% of 133461) affected shaders:
    Instrs: 319824 -> 319421 (-0.13%); split: -0.13%, +0.00%
    CodeSize: 1711260 -> 1708744 (-0.15%); split: -0.15%, +0.00%
    SpillSGPRs: 2567 -> 2459 (-4.21%)
    Latency: 3274930 -> 3274921 (-0.00%); split: -0.00%, +0.00%
    InvThroughput: 924106 -> 924105 (-0.00%); split: -0.00%, +0.00%
    Copies: 41883 -> 41757 (-0.30%); split: -0.31%, +0.00%
    Branches: 9144 -> 9146 (+0.02%)
    
    Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
    Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
    Cc: mesa-stable
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9599
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24896>
    (cherry picked from commit cb096b85ff14e62aba4275128d0c082e98a21d80)
    
  • 8e8b126e
    by Eric Engestrom at 2023-09-06T16:19:32+01:00
    .pick_status.json: Mark f97e38f9cdabf6e1cfab11ebaabf193492bd403c as denominated
    
  • b95e0085
    by Helen Koike at 2023-09-06T16:19:34+01:00
    ci/android: remove strace output from cuttlefish-runner.sh
    
    strace output is only used for debug and its output takes too much
    space. Remove it to save resources.
    
    Signed-off-by: Helen Koike <helen.koike@collabora.com>
    Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
    Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
    Fixes: 7b51a583edb7 ("ci/android: add android to the ci")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24913>
    (cherry picked from commit e6625fa25a46095baa75b35caa9b3dab00f9b1b8)
    
  • ccdec6f9
    by Lionel Landwerlin at 2023-09-06T16:19:35+01:00
    intel/compiler: disable per-sample interpolation modes with non-per-sample dispatch
    
    Fixes hangs in dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.*
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: 5644011f06 ("intel/compiler: Convert wm_prog_key::persample_interp to a tri-state")
    Reviewed-by: Emma Anholt <emma@anholt.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>
    (cherry picked from commit d74c3010268e6d2b7c0ef9a4d3caaf1f7e1b3a5a)
    
  • fec6eacb
    by Lionel Landwerlin at 2023-09-06T16:21:42+01:00
    intel/compiler: fix dynamic alpha-to-coverage handling
    
    Got the wrong logic operation. Let's reuse the nicer NIR builder
    helper.
    
    Fixes a bunch of KHR-GL46.sample_variables.mask.rgba8.*.samples*.mask*
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: fd7debc8bb ("intel/fs: make alpha_to_coverage a tristate")
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9568
    Reviewed-by: Emma Anholt <emma@anholt.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>
    (cherry picked from commit 9bf2a89127f0f4ef3c98190b266c9346122eabe3)
    
  • 6a7023cd
    by Lionel Landwerlin at 2023-09-06T16:21:49+01:00
    intel/fs: implement dynamic interpolation mode for dynamic persample shaders
    
    There is no restriction for query per sample positions from the
    interpolator when in non-per-sample dispatch mode. But apparently
    that's not giving us the expected values for fragment shaders compiled
    without per-sample dispatch knowledge (graphics pipeline libraries).
    
    So when per-sample dispatch is dynamic and we're doing at_sample
    interpolation, turn the interpolation back into at_offset at runtime
    when we detect that the fragment shader is not run per sample.
    
    Fixes a bunch of dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.*
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: d8dfd153c5 ("intel/fs: Make per-sample and coarse dispatch tri-state")
    Reviewed-by: Emma Anholt <emma@anholt.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>
    (cherry picked from commit 68027bd38e134f45d1fe8612c0c31e5379ed7435)
    
  • 3f60927f
    by Corentin Noël at 2023-09-06T16:21:59+01:00
    virgl: Do not expose EXT_texture_mirror_clamp when using a GLES host
    
    The GL_MIRROR_CLAMP_EXT wrap parameter is never available in GLES.
    
    This fixes the `spec@!opengl 1.1@texwrap 2d proj` piglit test when using a GLES
    host.
    
    Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
    Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24935>
    (cherry picked from commit 9c39ea796cd689670ab17e0c5dcc0c0b76db2cb4)
    
  • ec01ebd1
    by Rhys Perry at 2023-09-06T16:22:00+01:00
    aco/spill: add all live-in to merge block spill candidates
    
    Previously, only already spilled live-in or phis were added to the spill
    candidates. Because of branch definitions, this might not be enough.
    
    Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
    Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9722
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24949>
    (cherry picked from commit c7bb2f7bb9d81fe6236ca6f9df0631cae64ce573)
    
  • 3c40cff3
    by Friedrich Vock at 2023-09-06T16:22:59+01:00
    radv/rt: Pre-initialize instance address
    
    It's not disallowed by spec to load instance-related data in case of a
    miss where no instance was ever visited. Such loads make no sense, so we
    can return garbage, but it mustn't hang the GPU. Initialize the instance
    addresses to the TLAS base to make sure we always have valid memory to load from.
    
    Partially fixes GPU hangs in RTX Remix games.
    
    Cc: mesa-stable
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24971>
    (cherry picked from commit 728f6c0b70cf3c184fc13801fcb8f9ada37e132a)
    
  • 56249130
    by Karol Herbst at 2023-09-06T16:23:01+01:00
    rusticl/memory: do not verify pitch for IMAGE1D_BUFFER
    
    Devices might report an image_pitch_alignment of 0 leading to a division
    by 0 trap.
    
    Fixes: 06daa03c5cd ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
    Signed-off-by: Karol Herbst <git@karolherbst.de>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>
    (cherry picked from commit 526380261821cf820d70963ba07f61f46436ba9e)
    
  • 2d35e451
    by Lionel Landwerlin at 2023-09-06T16:23:04+01:00
    anv: add missing ISL storage usage
    
    ISL makes a bunch of decision on programming (MOCS,
    RENDER_SURFACE_STATE values) based on this flag. It's important to set
    it if we're going to use an image as storage.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Cc: mesa-stable
    Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
    (cherry picked from commit 34d5db05835b89a87a29865570047a52fe506048)
    
  • 0ccdcb1a
    by Rohan Garg at 2023-09-06T16:23:07+01:00
    crocus: fix GFX_VERx10 macro
    
    Signed-off-by: Rohan Garg <rohan.garg@intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    cc: mesa-stable
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
    (cherry picked from commit 99a88ca4a2419dd2efb02d5b2f5352b8fb5786a0)
    
  • 6c6ac51d
    by Rohan Garg at 2023-09-06T16:23:08+01:00
    blorp: drop undefined macro
    
    Signed-off-by: Rohan Garg <rohan.garg@intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: 97d6ceaf04 ("intel: Remove GEN_IS_HASWELL macro")
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
    (cherry picked from commit ca7ae1a53f83e71a8a117f12a7079cd57485166b)
    
  • f2eba1ae
    by Eric Engestrom at 2023-09-06T16:23:58+01:00
    .pick_status.json: Mark fa6562b239f00f9f72c988459e252bdee072fd73 as denominated
    
  • ff9db864
    by Eric Engestrom at 2023-09-06T18:06:54+01:00
    .pick_status.json: Update to 318b83899056d02ee83817cf16201a128fb81443
    
  • ec388fea
    by David Rosca at 2023-09-06T18:12:38+01:00
    Revert "radeonsi/vcn: add an exception of field case for h264 decoding"
    
    This change causes page faults when playing corrupted video from the
    bugreport. The original issue have now been resolved in firmware.
    
    This reverts commit bfce57c7a5ba62d8e6f65addb2df136cab603a68.
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9210
    
    Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24836>
    (cherry picked from commit ee1132bd793d26f512d0eaab7a6fb198634968c5)
    
  • a848887a
    by Timur Kristóf at 2023-09-06T18:15:58+01:00
    ac/nir: Add done arg to ac_nir_export_position.
    
    This prepares for a workaround where we won't need to add
    the done flag to the last export in this function, because
    it will be added in a subsequent call to the same function.
    
    Cc: mesa-stable
    Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
    Reviewed-by: Qiang Yu <yuq825@gmail.com>
    Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
    (cherry picked from commit 838d886d901ab2adc4c317652aebdd0bf3d52481)
    
  • 06f66ff2
    by Timur Kristóf at 2023-09-06T18:26:18+01:00
    ac/nir: Slightly refactor how pos0 exports are added when missing.
    
    Prepares for a workaround. Makes it possible for this function
    to not emit the pos0 export at all so that it can be emitted
    by a subsequent call to the function later.
    
    Cc: mesa-stable
    Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
    Reviewed-by: Qiang Yu <yuq825@gmail.com>
    Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
    (cherry picked from commit 9c096e4ace70c0b4f9c390bfc275596b10a0bd72)
    
  • b4954af8
    by Timur Kristóf at 2023-09-06T18:29:56+01:00
    ac/nir/ngg: Wait for attribute stores before VS/TES/GS pos0 export.
    
    This is a HW bug workaround for some (all?) GFX11 chips.
    
    On these chips, rasterization can start before the attribute ring
    stores are finished, which can cause issues.
    As a workaround, wait for attribute ring stores to finish
    before doing the position export.
    
    Mesh shaders will be taken care of in another commit.
    
    Cc: mesa-stable
    Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
    Reviewed-by: Qiang Yu <yuq825@gmail.com>
    Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
    (cherry picked from commit edd51655f0eb44178c9e402ae35667bd184adf2a)
    
  • b86865c0
    by Timur Kristóf at 2023-09-06T18:34:58+01:00
    ac/nir/ngg: Refactor mesh shader primitive export.
    
    Cleanup the code that generates the two channels of the
    primitive export instruction, and move storing the built-in
    per-primitive outputs out to match how vertex attributes work.
    
    Prepares the mesh shader lowering for a workaround that
    affect export instructions.
    
    Cc: mesa-stable
    Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
    Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
    (cherry picked from commit 0721784b78ad85d5c281530858bfb50490d741b9)
    
  • 4ddc9267
    by Timur Kristóf at 2023-09-06T18:37:48+01:00
    ac/nir/ngg: Wait for attribute ring stores in mesh shaders.
    
    Make sure that both per-vertex and per-primitive attribute
    ring stores are finished before position or primitive export
    instructions are executed.
    
    This is necessary because we need to ensure that mesh shader
    waves work correctly when they have either vertex-only or
    primitive-only waves.
    
    Cc: mesa-stable
    Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
    Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
    (cherry picked from commit 93b4f200dead198e680991a1e95bf3d3b58f87bd)
    
  • 0621ca00
    by Leo Liu at 2023-09-06T18:38:21+01:00
    radeonsi/vcn: fix the incorrect dt_size
    
    Issue: For texture with multiple planes, the planes will point to the
    same BO with the total size, so current vcn dt_size is incorrect.
    
    (gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[0]))
    ...
      buf = 0x5555558daa30,
      gpu_address = 0xffff800101000000,
      bo_size = 0xa2000,
    ...
    }
    (gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[1]))
    ...
      buf = 0x5555558daa30,
      gpu_address = 0xffff800101000000,
      bo_size = 0xa2000,
    ...
    }
    
    This is because: in function static struct si_texture *si_texture_create_object(),
       if (plane0) {
          /* The buffer is shared with the first plane. */
          resource->bo_size = plane0->buffer.bo_size;
          ...
          radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
          resource->gpu_address = plane0->buffer.gpu_address;
       }
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9728
    Cc: mesa-stable
    
    Signed-off-by: Leo Liu <leo.liu@amd.com>
    Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25013>
    (cherry picked from commit 7876a2f68532a2bc5ab044cab726eae7fba328fa)
    
  • e055eef4
    by Lionel Landwerlin at 2023-09-06T18:42:13+01:00
    intel/nir: rerun lower_tex if it lowers something
    
    nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
    also need to lower into constant offsets.
    
    Unfortunately the nir_lower_tex pass is not able to lower the
    instructions it itself generates, so the easy fix for when
    nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
    Cc: mesa-stable
    Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
    Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
    (cherry picked from commit 10e75aae1bddee9795b1ff04ffd656b0da79b5b5)
    
  • c93039d6
    by antonino at 2023-09-06T18:43:04+01:00
    vulkan/wsi: add `vk_wsi_force_swapchain_to_current_extent` driconf
    
    Add a driconf to force the swapchain size to match
    `VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
    misbehaved games
    
    Fixes: 6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
    Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
    (cherry picked from commit aa657247ce8e4da53503c584a7a869a87b45f9fb)
    
  • f9dcca05
    by antonino at 2023-09-06T18:48:29+01:00
    drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "The Talos Principle"
    
    This game handles swapchain size incorrecly and can crash because of
    it.
    
    Enable this driconf as a workaround.
    
    Fixes: 6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
    Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
    (cherry picked from commit 142e317024c17814549f23c5ae745ae8a495eb8c)
    
  • 4c71800e
    by antonino at 2023-09-06T18:53:10+01:00
    drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "Serious Sam Fusion"
    
    This game handles swapchain size incorrecly and can crash because of
    it.
    
    Enable this driconf as a workaround.
    
    Fixes: 6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
    Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
    (cherry picked from commit 1456cb9c0bb896467bee9f45135fa38700f4cf52)
    
  • 9fd2a458
    by Rohan Garg at 2023-09-06T18:53:28+01:00
    iris: migrate preemption streamwout wa to WA infra
    
    Fixes: db6c374 ('iris: disable preemption for 3DPRIMITIVE during streamout')
    Signed-off-by: Rohan Garg <rohan.garg@intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25080>
    (cherry picked from commit a57faf50370f60e06e03062b0ff4a0c2c3258004)
    
  • 301d04b3
    by Eric Engestrom at 2023-09-06T18:53:47+01:00
    .pick_status.json: Mark 83716b08cf103622829d84e673584781ee8850f6 as denominated
    
  • 471d8df0
    by Eric Engestrom at 2023-09-06T18:53:48+01:00
    .pick_status.json: Mark 8b93fa149bfbe1ca1a59d89ec53d576aa4ede2ec as denominated
    
  • 3af72c97
    by Eric Engestrom at 2023-09-06T22:28:26+01:00
    docs: add release notes for 23.1.7
    
  • 98d9d5f5
    by Eric Engestrom at 2023-09-06T22:29:52+01:00
    VERSION: bump for 23.1.7
    
  • 22d8eb0b
    by Timo Aaltonen at 2023-09-08T13:25:06+03:00
    Merge branch 'upstream-unstable' into debian-unstable
    
  • 1bae2361
    by Timo Aaltonen at 2023-09-08T13:25:37+03:00
    version bump
    
  • af4e2c96
    by Timo Aaltonen at 2023-09-08T13:32:35+03:00
    release to sid
    

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