-
60a8ab59
by Eric Engestrom at 2022-12-14T20:46:59+00:00
docs: add release notes for 22.3.0
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6fae6b40
by Lionel Landwerlin at 2022-12-14T20:47:00+00:00
iris: move bindless surface state heap inside the surface state heap
We're about to make scratch surface states part of the surface state
heap. Because those are required to be in the low 26bits parts surface
state heap (we're limited in bits handed in the CFE_STATE, 3DSTATE_VS,
etc... instructions), this change splits the 32bit surface state heap
as follow:
- 8Mb of surface states for scratch
- 1Gb - 8Mb of binding tables
- 3Gb of surface states
That way all of the surfaces are located within a 4Gb region visible
from STATE_BASE_ADDRESS::SurfaceStateBaseAddress
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
(cherry picked from commit daab161535747cf5aef443e4cee46c5415662848)
-
88cb57c8
by Eric Engestrom at 2022-12-14T20:47:00+00:00
.pick_status.json: Update to 264a0cabd1dd2a619f24e34f21f767c6bf36fe76
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ba9ee546
by Alyssa Rosenzweig at 2022-12-14T20:47:00+00:00
pan/mdg: Emulate 8-bit with the 16-bit pipe
We don't care to support i8vec16, we just need a bit of 8-bit support to
implement format packing/unpacking in blend shaders. We're already doing
this by using the 16-bit pipe, we just need to commit to it all the way
-- reporting the correct sizes in max_bitsize_for_alu so the mask
packing logic works as intended -- and dropping the imov-specific hack
that was introduced to workaround a similar class of bugs.
With the previous patch, fixes:
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1
Fixes: 39e4b7279dc ("pan/midg: Fix swizzling on 8-bit sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
(cherry picked from commit 976405907e35629b42501a9f86b067986599cb28)
-
68fc987c
by Georg Lehmann at 2022-12-14T20:47:00+00:00
aco: Use wave size specific opcode for s_or in cube map coord code.
Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20041>
(cherry picked from commit a3beb82cf6bcf84425431ec17c046a80b2b7fc79)
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2cabe416
by Bas Nieuwenhuizen at 2022-12-14T20:47:00+00:00
radv: Handle nodes with 2 invalid children in internal node converter.
Fixes: 682dc5c28e4 ("radv: Add conversion shader for internal nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
(cherry picked from commit f531f671ef64acc8ea56a473c05aeb5ea9f4c1f0)
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b0227525
by Connor Abbott at 2022-12-14T20:47:00+00:00
freedreno/fdl: Set sRGB bit for storage images
This probably wasn't noticed earlier because tests using sRGB storage
images didn't exist, and we didn't know whether this works, but this
fixes dEQP-VK.image.store.without_format.2d.*_srgb which also proves
that the bit works.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20060>
(cherry picked from commit ccef6d1f5fdae95ee8aa5a68e83662e02645b64a)
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20ba98ab
by Marcin Ślusarz at 2022-12-14T20:47:00+00:00
intel/compiler: adjust [store|load]_task_payload.base too
Base also needs to be converted from bytes to words.
Fixes: c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit 7aaafaa8ae26ee1086a51089c12e4fa9e9645c2e)
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985a4eba
by Marcin Ślusarz at 2022-12-14T20:47:00+00:00
nir/lower_task_shader: allow offsetting of the start of payload
We need this, because on Intel task payload starts with private header,
followed by user-accessible data.
Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit f6adfd6278301aa772d3d44fc64ade21c9860574)
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2615b5a3
by Marcin Ślusarz at 2022-12-14T20:47:00+00:00
intel/compiler: user payload starts after TUE header & its padding
All data written by the user are offset by TUE header size.
Without this patch we copy the correct amount of user data, but both
"from" and "to" offsets are wrong.
Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit db0e6f9a07b49a95d99c2b2c25fd8a008466c4e8)
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e8a59e42
by Iago Toral Quiroga at 2022-12-14T20:47:00+00:00
v3dv: make single-sync paths more explicit
Instead of having functions that return early in multi-sync mode
let's only call them when we are in single-sync mode. I think this
makes the code more explicit.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 95b9293eeb02f3b43fb7de5afc6f7c89ffffe92f)
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8dcb79b6
by Iago Toral Quiroga at 2022-12-14T20:47:00+00:00
v3dv: fix job serialization for single sync path
The idea in the single sync path is that we serialize any job that
needs to wait, however, our ANY queue syncobj only tracks the last job
submitted to any hardware queue, so in practice when we wait on this
we are only serializing against the queue to which we have submitted
the last job, which is not correct.
Fix that by accumulating the last job sync into the ANY queue synbcobj
to ensure that waiting on this syncobj effectively waits on all
hardware queues.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 4276ec9f2af33da270ca9cf6a6a9a62b2a4d060a)
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bd5d5991
by Daniel Stone at 2022-12-14T20:47:00+00:00
ci: Rebalance radv/grunt testing
We've recently rebalanced our lab devices to get a fewer number of
grunts. Switch to scheduling only on the newer shinier ones, running
fewer tests. We'll evaluate the runtime, and if they're quick enough
then we can increase the amount of testing we do.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20081>
(cherry picked from commit 921cfcf4c4f5cb6f82ef978587e0462218093542)
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48e7b3a1
by Danylo Piliaiev at 2022-12-14T20:47:00+00:00
ir3: Reduce the maximum allowed imm offset for shared var load/store
STL/LDL have 13 bits to store imm offset. However the most significant
bit in the offset is a sign bit, so the positive offset is limited by
12 bits.
nir_opt_offsets only has the upper limit and doesn't deal with
negative offsets, so shared_max should be changed to `(1 << 12) - 1`.
The issue was found in "Monster Hunter: World".
Fixes: 0b2da9d795610df15346a594384c39a096be338f
("ir3: Limit the maximum imm offset in nir_opt_offset for shared vars")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20100>
(cherry picked from commit 8f0177b3345f8bcc3673b8a2a7c36ea36cbaa029)
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b81a2914
by Lionel Landwerlin at 2022-12-14T20:47:00+00:00
isl: don't report I915_FORMAT_MOD_Y_TILED_CCS on Gfx8
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
(cherry picked from commit 0626b68c88df50e30e61e9fd2ba3e46144ff9ad5)
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a1740911
by Lionel Landwerlin at 2022-12-14T20:47:00+00:00
anv: correctly predicate ray tracing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7479fe6ae093 ("anv: Implement vkCmdTraceRays and vkCmdTraceRaysIndirect")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20011>
(cherry picked from commit af3f7948d149faded1b4f24ec5e6ae03001e7cfb)
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dcf29607
by Danylo Piliaiev at 2022-12-14T20:47:00+00:00
nir/nir_opt_offsets: Prevent offsets going above max
In try_fold_load_store when trying to extract const addition from
non-const offset source, we should take into account that there is
already a constant base offset, which should count towards the limit.
The issue was found in "Monster Hunter: World" running on Turnip.
Fixes: cac6f633b21799bd1ecc35471d73a0bd190ccada
("nir/opt_offsets: Use nir_ssa_scalar to chase offset additions.")
Well, the issue was present before this commit but it made a lot
of changes in surrounding code.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20099>
(cherry picked from commit 5d025f4003b34c3540b62f9146a5e68da7756cf2)
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d988e3f3
by Konstantin Seurer at 2022-12-14T20:47:00+00:00
radv/rra: Set the metadata size correctly
Fixes: 5749806 ("radv: Add Radeon Raytracing Analyzer trace dumping utilities")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20047>
(cherry picked from commit bb6b45e26ed56af8a94357a58fd849143671cf7f)
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f2327830
by Jason Ekstrand at 2022-12-14T20:47:00+00:00
nir: Use nir_const_value_for_int in nir_lower_subgroups
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7670
Fixes: e4e79de2a420 ("nir/subgroups: Support > 1 ballot components")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit e6de164e0305d517fb66c01c9fc8931c278867f6)
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af63185b
by Jason Ekstrand at 2022-12-14T20:47:00+00:00
st/mesa: Use nir_const_value_for_bool() in ATIFS
Fixes: 0a179bb6e26b ("st/mesa: Generate NIR for ATI_fragment_shader instead of TGSI.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit 49d86200e5cd8ac15c14131772644b21bf57865e)
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3b5c8ec1
by Jason Ekstrand at 2022-12-14T20:47:00+00:00
r600/nir: Fix u64vec2 immediate lowering
There were a couple of issues here:
1. We should be using nir_const_value_for_uint instead of setting the
union fields directly to ensure the rest of the union is zeroed.
2. It was always filling out the first two components of val even if
the incoming constant had 2 64-bit components.
Fixes: 165fb5117bf7 ("r600/sfn: add lowering passes to get 64 bit ops lowered to 32 bit vec2")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit f3f1c28f8e6d40823e3d12415a8d0ea622f9fa20)
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b34f6c15
by Jason Ekstrand at 2022-12-14T20:47:00+00:00
dxil: Use nir_const_value_for_uint in dxil_nir_lower_int_samplers
This change should avoid any accidental rounding issues because of
border colors getting stored in a float in dxil_wrap_sampler_state. It
also switches us to using the correct helpers for nir_const_value so we
can avoid any weird uninitialized data failures that can be caused by
filling out the fields in the struct directly.
Fixes: b9c61379ab4c ("microsoft/compiler: translate nir to dxil")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit cd5c66e165374026d62692bcbf69a7157e460f91)
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d43425f7
by Sviatoslav Peleshko at 2022-12-14T20:47:00+00:00
anv: Defer flushing PIPE_CONTROL bits forbidden in CCS while in GPGPU mode
Fixes: 313aeee8 ("anv: Use pending pipe control mechanism in flush_pipeline_select()
")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7816
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20124>
(cherry picked from commit 77ecf9149c7fdadbb24b471785c4d5b4e285f2df)
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1b27820b
by Jan Alexander Steffens (heftig) at 2022-12-14T20:47:00+00:00
d3d12: Don't crash when libd3d12.so can't be found
`d3d12_destroy_screen` is called by `d3d12_create_dxcore_screen` after
`d3d12_init_screen_base` fails and attempts to call `util_dl_close` on
a NULL pointer, leading to an abort.
To fix this, only close the library after if it was actually opened.
Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20145>
(cherry picked from commit b3d1ae19f2f4d93cf0a5f45a598149ac4e8e05aa)
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ff39ada9
by Jan Alexander Steffens (heftig) at 2022-12-14T20:47:00+00:00
dzn: Don't crash when libd3d12.so can't be found
`dzn_instance_create` will call `dzn_instance_destroy` when the d3d12
library fails to load. Just like the issue in `d3d12_screen`, this will
lead to a crash because `d3d12_mod` is NULL.
To fix this, only close the library after if it was actually opened.
Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20145>
(cherry picked from commit b5133894005720db24a8e0cc17e047a291953ff4)
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b6e7aeb1
by Samuel Pitoiset at 2022-12-14T20:47:00+00:00
radv: fix emitting invalid color attachments
Note sure how this happened.
Fixes: 97dc28b1776 ("radv: fix configuring COLOR_INVALID on GFX11")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20127>
(cherry picked from commit 664aa7a37b540b27f8bd96b1d685c8e449d6a711)
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2510c6c5
by Samuel Pitoiset at 2022-12-14T20:47:00+00:00
radv: do not set ZPASS_INCREMENT_DISABLE on GFX11
This field no longer exists.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20090>
(cherry picked from commit b051719b05894c3c5b9f0f8ad919be478b43697b)
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e2fc0b33
by Lionel Landwerlin at 2022-12-14T20:47:01+00:00
intel: factor out dispatch PS enabling logic
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit b9403b1c477e7af04114ae6a4e16ca370e22253c)
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7b5ba2d3
by Lionel Landwerlin at 2022-12-14T20:47:01+00:00
intel: add missing restriction on fragment simd dispatch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7755
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit d4cd33630a9b90b95390f10d3aaa52f6f5e20245)
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3ef6b27b
by Chia-I Wu at 2022-12-14T20:47:01+00:00
nir: fix nir_link_varying_precision
link_varyings ignores precisions and can assign the same location to
variables with different precisions. nir_link_varying_precision should
check location_frac as well.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20113>
(cherry picked from commit 7244d885164aa59ca136358d256a0078b24a455d)
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64808162
by Samuel Pitoiset at 2022-12-14T20:47:01+00:00
radv: use LATE_Z for depth/stencil attachments used in feedback loops
To make sure shader invocations read the correct values.
Fixes dEQP-VK.rasterization.rasterization_order_attachment_access.*.samples_*.multi_draw_barriers
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19728>
(cherry picked from commit a42f8d49c39eb59a520fde05fdcab0ffab3a16c6)
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d8d1b094
by Ruijing Dong at 2022-12-14T20:47:01+00:00
radeonsi/vcn: adding av1 decoding film grain block
add the logic for calculating film grain related
coefficients for VCN to generate film grain output.
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19660>
(cherry picked from commit b28356745686571676742f3822fd371b95e8742b)
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91c565df
by Rhys Perry at 2022-12-14T20:47:01+00:00
aco: more carefully apply constant offsets into scratch accesses
Death stranding does scratch_arr[80-idx]. This doesn't seem to work if we
try to combine the subtraction into the access.
fossil-db (navi21):
Totals from 52 (0.04% of 135636) affected shaders:
Instrs: 78560 -> 79036 (+0.61%)
CodeSize: 427940 -> 431188 (+0.76%)
Latency: 1313809 -> 1318142 (+0.33%)
InvThroughput: 292833 -> 293842 (+0.34%)
VClause: 2361 -> 2555 (+8.22%); split: -0.51%, +8.73%
Copies: 8767 -> 8746 (-0.24%); split: -0.35%, +0.11%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 0e783d687a3 ("aco: use scratch_* for scratch load/store on GFX9+")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7735
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20117>
(cherry picked from commit 381de3c809fce5427308c696bbd313360194eff4)
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5f387adc
by Marcin Ślusarz at 2022-12-14T20:47:01+00:00
nir/lower_task_shader: fix task payload corruption when shared memory workaround is enabled
We were not taking into account that when all invocations within workgroup
are active, we'll copy more data than needed, corrupting task payload
of other workgroups.
Fixes: 8aff8d3dd42 ("nir: Add common task shader lowering to make the backend's job easier.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20080>
(cherry picked from commit ffefa386fda5aec8f66b4499d93b41a846a0b86c)
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7fa84a47
by Samuel Pitoiset at 2022-12-14T20:47:01+00:00
radv: fix guardband if the polygon mode is points or lines
If points or lines are drawn using the polygon mode, the guardband
should be adjusted for large points/lines.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20185>
(cherry picked from commit 12f26b5e6d57a1fd03c1f1fb0ab8ccae657026ab)
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0aecc208
by Dawn Han at 2022-12-14T20:47:01+00:00
venus: fix deqp tests failed on iub descriptor type
Fixes: abae9d4831b ("Add the iub binding count tracking")
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20064>
(cherry picked from commit fbf4c6e43ff810625ff916d40c6b00429adaaf14)
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1fa232af
by Erik Faye-Lund at 2022-12-14T20:47:01+00:00
zink: don't use defunct custom-flag
We're no longer respecting this flag, so there's no need in setting it.
Fixes: 00dc0036bb6 ("zink: flatten out buffer creation usage flags codepath")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20183>
(cherry picked from commit 2ccf481c17ccded161b9eecb63a257d81056e3ec)
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2fbea1fd
by Dave Airlie at 2022-12-14T20:47:01+00:00
glx: fix xshm check to init xshm_opcode.
Found and proposed by Ray Strode (halfline)
Fixes: 68e89401140d ("glx/drisw: use xcb instead of X to query connection")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20188>
(cherry picked from commit 57b7102ef96a282128ead4e7a8c03c7fdb53e71a)
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a0ffb410
by Danylo Piliaiev at 2022-12-14T20:47:01+00:00
meson: Do not enable drm for KGSL Turnip build
Android may use either DRM or some downstream solution, KGSL is a
downstream kernel driver for Adreno. Don't enable DRM when we want
Turnip to use KGSL instead of DRM.
Fixes: 09ac29cca9bf7978911f81bcfce12ce71c260a97
("meson: Enable system_has_kms_drm for android")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20168>
(cherry picked from commit 1cfc413c9a4cdd26222197ab0a518c2b603d82b1)
-
d4d1f522
by Otavio Pontes at 2022-12-14T20:47:01+00:00
anv/hasvk: Clamping Scissor Rect values in a valid range
On cmd_buffer_emit_scissor(), if VkViewport height or width are set to
a value lower than 1.0, y_max or x_max can be attributed negative values,
causing an overflow. That leads to ScissorRectangleYMax or
ScissorRectangleXMax to be set to values on an unsupported range.
Clamping x_max and y_max in the valid range solves the problem.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7471
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20200>
(cherry picked from commit 2e775b8bdbc5cd0d120b5c757188f6e85bf0d59d)
-
75e55ca0
by Iván Briano at 2022-12-14T20:47:01+00:00
vulkan: VkPolygonMode has a bit more than two values
Fixes: 9d0ed9cbcc0 ("vulkan: Add more dynamic rasterizer state")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20212>
(cherry picked from commit e1ab7629f8a459df87009c7cb28b41acfb17e45c)
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d936394c
by Kenneth Graunke at 2022-12-14T20:47:01+00:00
intel/compiler: Set NoMask on cr0 access for float controls mode
This is trying to clear a bit in the control register. However, it's
executing with whatever channel mask happens to be active. Typically
this is the one at the start of the program, so at least some channels
will be active. Typically the first channel will be active due to
packed dispatch, but that's not always guaranteed. Without NoMask,
the float controls writes may randomly not happen.
Recent GPUs also seem to have a hang issue when the first instruction in
the shader doesn't have any active channels. Having an instruction with
NoMask at the start of the program works around the issue. See HSD bug
14017989577. In our case, the float controls preamble was breaking that
restriction every time, causing us to run into this problem frequently.
Thanks to Tapani Pälli for finding this hang issue, and Francisco
Jerez and Lionel Landwerlin for helping pinpoint this issue during
review of a workaround patch in !20194.
Fixes GPU hangs in Elder Scrolls Online, Witcher 3, and likely more.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7639
Fixes: 9da56ffc522 ("i965/fs: add emit_shader_float_controls_execution_mode() and aux functions")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20214>
(cherry picked from commit bafbe7c23a1cdd8c27ee5ea2da6b0575c53e2c5f)
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5b671872
by Tapani Pälli at 2022-12-14T20:47:01+00:00
intel/fs: implement Wa_14017989577
The first instruction of any kernel should have non-zero emask. This
restriction needs to be obeyed to avoid GPU hangs.
Patch adds a function to insert dummy mov as first instruction
to make sure this requirement is fulfilled.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20194>
(cherry picked from commit bc4b7de0d0469e296f7ec4626fccdf97926b1c8e)
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bcc73ba6
by Boyuan Zhang at 2022-12-14T20:47:01+00:00
radeonsi: disable av1 decode for navi24
Disable AV1 decode for Navi24 since hardware doesn't support.
fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7855
cc: mesa-stable
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20230>
(cherry picked from commit 5233551e1912519b456515ac8da7a62c9779fca8)
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e1774049
by Tapani Pälli at 2022-12-14T20:47:01+00:00
anv: emit sample mask state independent of fragment stage
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7861
Fixes: 9f6af43743d ("anv: dynamic multisample sample mask")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20221>
(cherry picked from commit 68ef0d84481fd92df6cde8935f079d958e6b36e9)
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6922882d
by Ruijing Dong at 2022-12-14T20:47:01+00:00
frontends/va: fix gst videotestsrc h264 enc fail issue.
problem:
when doing "gst-launch-1.0 -v videotestsrc num-buffer=10 !
vaapih264enc ! fakeink"
The command will fail due to gst will fetch the first
available supported format in the list, it becomes P010_LE
due to the commit in
[0b02db3007]
frontends/va: fixed av1 decoding 10bit ffmpeg output YUV issue
fix:
move the P010_LE code block to the end of the function, the sequence
of the supported formats restored to its original.
cc: mesa-stable
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20242>
(cherry picked from commit a73e86e0a5eb58e2f25f7b7419a78c122cc5ab1a)
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2c738559
by Rhys Perry at 2022-12-14T20:47:01+00:00
aco/ra: don't swap p_create_vector operand with definition blocker for scc
SCC is 1-bit, and we can't copy a 32-bit value into it.
Fixes dEQP-VK.spirv_assembly.type.scalar.i32.iequal_tesse with
ACO_DEBUG=noopt.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 9476986e6f6 ("aco/ra: special-case get_reg_for_create_vector_copy()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20240>
(cherry picked from commit a05dd58309caf7e3857eb7f02084d8c9667c9efc)
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68fece9a
by Lionel Landwerlin at 2022-12-14T20:47:01+00:00
Revert "anv: compile anv_acceleration_structure.c"
This reverts commit 74d0be27ae9eb666df948874a20a3b4464df7db1.
Also remove anv_acceleration_structure.c, it was meant to be removed
earlier. There was probably a rebase issue somewhere.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20248>
(cherry picked from commit d608706875996b05df48b0e35ee0456f0f2ae8cf)
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57827e69
by Friedrich Vock at 2022-12-14T20:47:01+00:00
nir: Do not consider phis with incompatible dests equal
CSE tries to collapse equal instructions, and collapsing two phis with incompatible dests is illegal.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Fixes: 6bdce55c ("nir: Add a basic CSE pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19960>
(cherry picked from commit a54c2c828941ef1325fc1a3b49eba32f3c964f0d)
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5e0dfcb9
by Samuel Pitoiset at 2022-12-14T20:47:02+00:00
radv: fix hashing descriptor set layout
Shouldn't have pointers.
Fixes: 19f8d338761 ("radv: Use vk_descriptor_set_layout")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20250>
(cherry picked from commit 13f39da71a69026445fc5455d749858aa7ad94dc)
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bf1d05b8
by Lionel Landwerlin at 2022-12-14T20:47:02+00:00
intel/nir/rt: fixup primitive id
There is a delta index value in the hit structure, we forgot to add it
to the base value.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 046571479028 ("intel/nir/rt: add more helpers for ray queries")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7565
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19346>
(cherry picked from commit 610639682533783796fe32bdcb2b4d3375fae56f)
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dc889d95
by Iván Briano at 2022-12-14T20:47:02+00:00
hasvk: pipelineStageCreationFeedbackCount is allowed to be 0
Fixes: 6601e5d6fc6 ("anv: implement VK_EXT_pipeline_creation_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20216>
(cherry picked from commit 68b546ec3daacc93513b31583cbe6eb7f8fdc25c)
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0c7a3133
by Lionel Landwerlin at 2022-12-14T20:47:02+00:00
anv: fixup descriptor copies
I did not properly understood that we cannot access the views written
to the descriptor sets because they might have been destroyed after
the write operation and the copy operation is allowed to copy what is
invalid data. The shader just can't access it.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 03e1e19246 ("anv: Refactor descriptor copy")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20222>
(cherry picked from commit a0991c7c794da39bf1a4b5fb5484b77afde200cc)
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3e3def96
by Peng Huang at 2022-12-14T20:47:02+00:00
intel: Fix crashes for importing drm buffer
image_aspect_to_binding() converts aspect to index by subrracting
VK_IMAGE_ASPECT_MEMORY_PLANE_0_BIT_EXT, however these enum values
are bitfields, not consecutive numbers, so comparing and subtracting
them won't work.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20269>
(cherry picked from commit 7642f3b99c8b17c7cfa1f140c65ce82e7dbcea2b)
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63e1ccd5
by Friedrich Vock at 2022-12-14T20:47:02+00:00
radv: Handle NULL miss shaders
Fixes reflections in DOOM Eternal.
Fixes: 85580faa ("radv: Add ray traversal loop.")
Closes: #6210
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20270>
(cherry picked from commit 568fa71ef8d825b735fdbf6747ada3d7cfe95eff)
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a9b3fee4
by Jan Palus at 2022-12-14T20:47:02+00:00
vdpau: allow building vdpau st with virgl only
Fixes: 6b5aecb1955 ("virgl: add support for hardware video acceleration")
Signed-off-by: Jan Palus <jpalus@fastmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20108>
(cherry picked from commit 8560ce28c22f82895dd95c185b59dcaaab249c6a)
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a8911c50
by Samuel Pitoiset at 2022-12-14T20:47:02+00:00
radv: do not remove the PointSize built-in for polygon mode as points
Determine if it can be removed when generating the graphics pipeline
key because of dynamic states.
Fixes new CTS dEQP-VK.rasterization.polygon_as_large_points.* and also
spec@!opengl 1.1@polygon-offset with Zink/RADV.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20073>
(cherry picked from commit b4f940913d386bad0e25a1e224d0f39631124593)
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0565b834
by Sathishkumar S at 2022-12-14T20:56:02+00:00
radeonsi/vcn: enable yuv422 jpeg decode
add yuv422 to supported decode format on asics that support it.
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19445>
(cherry picked from commit 581220aa5471f4957a33d3156b07a03969972136)
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74d17cba
by Sathishkumar S at 2022-12-14T20:56:53+00:00
radeonsi/vcn: fix regression in yuv422 jpeg decode
- yuv422 decode was blocked in 12acee17fad5, enable it back.
- nv12 yuv422 and grayscale decode is supported on all versions.
- JPEG2 and higher versions supports 444p decode.
- add l8_unorm to supported formats, can be used for grayscale.
Fixes: 12acee17fad5 (frontends/va: reallocate surface for yuv400/yuv444 picture)
v2: indent the switch case correctly (Thong Thai)
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20165>
(cherry picked from commit 7ad4a5079e8ad0b9f3ab7924cc3dfec5f74ea88d)
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ae1fa524
by Eric Engestrom at 2022-12-14T20:56:54+00:00
v3dv: skip some invalid tests
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20305>
(cherry picked from commit 408f1c689c2bcd3e746d025bfbb623dd8c6c81ef)
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c1fad08d
by Ian Romanick at 2022-12-14T20:56:54+00:00
glsl_to_nir: Fix NIR bit-size of ir_triop_bitfield_extract and ir_quadop_bitfield_insert
Previously these would return result->bit_size of 32 even though the
type might have been int16_t or uint16_t. This prevents many assertion
failures in "glsl: Use nir_type_convert instead of
nir_type_conversion_op" on zink.
Fixes: 5e922fbc160 ("glsl_to_nir: fix bitfield_extract with 16-bit operands")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15121>
(cherry picked from commit 43da8223121b8807d2dd7fcf1276d145242365e6)
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b5820a84
by Lionel Landwerlin at 2022-12-14T20:56:54+00:00
isl: make Wa_1806565034 conditional to non robust access
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit 89a550a37b0bb32bc3dfd92062f9fe6eb05c11db)
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fcb34f03
by Lionel Landwerlin at 2022-12-14T20:56:54+00:00
intel/fs: make Wa_1806565034 conditional to non robust access
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit 94bb4a13fa294204e32b88a098c2d49a0c82a5c3)
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a60641d1
by Lionel Landwerlin at 2022-12-14T20:56:54+00:00
anv: disable Wa_1806565034 when robustImageAccess is enabled
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5711
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7859
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit a921486e2a6ca5fc873a6e2f9c61fb5bef4cf3d9)
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cdbba253
by Sathishkumar S at 2022-12-14T20:56:54+00:00
frontends/va: fix crash during grayscale rendering
crash is observed as format is assumed to be yuv and buffer plane
order is undefined for monochrome. luma only format is not to be
considered yuv format. It has to be rendered with rgb=rrr.
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20165>
(cherry picked from commit 6a3179c5a97f9a45006af2781d0af4b437784515)
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9b02e5c0
by Sathishkumar S at 2022-12-14T20:56:55+00:00
gallium/vl: return the buffer plane order for yuv444p format
plane order is expected when trying to render yuv surfaces, update it for yuv444p
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19445>
(cherry picked from commit f1ea0bc18aa6dd62554d7c556c087640dbc8a168)
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840eef75
by Eric Engestrom at 2022-12-14T21:05:30+00:00
docs: add release notes for 22.3.1
-
c3670614
by Eric Engestrom at 2022-12-14T21:06:11+00:00
VERSION: bump for 22.3.1
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7674759a
by Timo Aaltonen at 2022-12-15T12:37:16+02:00
Merge branch 'upstream-unstable' into debian-unstable
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8b8030f5
by Timo Aaltonen at 2022-12-15T12:39:10+02:00
version bump
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6ad58c77
by Timo Aaltonen at 2022-12-15T12:41:07+02:00
patches: Drop upstreamed patches.
-
483a2ca4
by Timo Aaltonen at 2022-12-15T13:17:32+02:00
control: Use Rules-Requires-Root: no.
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e036f0d1
by Timo Aaltonen at 2022-12-15T13:21:33+02:00
release to sid