[Git][xorg-team/lib/mesa][debian-experimental] 72 commits: radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache

[Timo Aaltonen <tjaalton@debian.org>]

Title: GitLab

Timo Aaltonen pushed to branch debian-experimental at X Strike Force / lib / mesa

Commits:

• 6e07ac33
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache
  
  It could load an NGG shader when we want a legacy shader and vice versa.
  

• 3dec21a8
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi: move some global shader cache flags to per-binary flags
  

• 78c603eb
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: fix tessellation for the legacy pipeline
  
  ported from PAL
  

• beea2dee
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy streamout
  

• a3a26680
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: create the GS copy shader if using legacy streamout
  

• 4d3097f3
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
  
  Legacy GS only works with Wave64.
  

• c0716446
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: fix InstanceID for legacy VS+GS
  

• f208b04d
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
  
  Only gfx9 and older use it to get InstanceID in VGPR1.
  

• e09d4696
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: always use the legacy pipeline for streamout
  
  The best way to prevent GDS hangs is not to use GDS.
  

• 0207c318
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: finish up Navi14, add PCI ID
  

• b9330a61
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: add AMD_DEBUG=nongg
  

• a935da7c
  by Marek Olšák at 2019-08-27T20:10:40Z

  winsys/amdgpu+radeon: process AMD_DEBUG in addition to R600_DEBUG
  

• 514eb158
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi: add PKT3_CONTEXT_REG_RMW
  

• d23bf14d
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
  
  It varies depending on si_shader_key::as_ngg.
  

• 5d775401
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags
  
  We need two different values of the register, one for NGG and one for
  legacy, in order to fix edge flags for the legacy pipeline.
  
  Passing the ngg flag to emit_clip_regs would be too complicated,
  so CONTEXT_REG_RMW is used for partial register updates.
  

• 25de4596
  by Marek Olšák at 2019-08-27T20:10:40Z

  radeonsi: consolidate determining VGPR_COMP_CNT for API VS
  

• 8ee40f6b
  by Ilia Mirkin at 2019-09-04T18:50:32Z

  gallium/vl: use compute preference for all multimedia, not just blit
  
  The compute paths in vl are a bit AMD-specific. For example, they (on
  nouveau), try to use a BGRX8 image format, which is not supported.
  Fixing all this is probably possible, but since the compute paths aren't
  in any way better, it's difficult to care.
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
  Fixes: 9364d66cb7 (gallium/auxiliary/vl: Add video compositor compute shader render)
  Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit 958390a9bf8904522a50f8e9c26c50c96179c183)
  

• 55334521
  by Bas Nieuwenhuizen at 2019-09-04T18:50:37Z

  radv: Use correct vgpr_comp_cnt for VS if both prim_id and instance_id are needed.
  
  Should take the max of the 2.
  
  Fixes: ea337c8b7e9 "radv/gfx10: fix VS input VGPRs with the legacy path"
  Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  (cherry picked from commit 2e763f7c87cefbb0c2c8d692e8e1584f89b4c747)
  

• 614def1a
  by Bas Nieuwenhuizen at 2019-09-04T18:50:42Z

  radv: Emit VGT_GS_ONCHIP_CNTL for tess on GFX10.
  
  Otherwise hangs are possible. This register was already set for
  GS and NGG.
  
  Fixes: 5eaed7ecfce "radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14"
  Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  (cherry picked from commit e04761d0f9b5b10eed01bc4c2893070a31aa35cf)
  

• 71daf2ef
  by Danylo Piliaiev at 2019-09-04T18:50:48Z

  nir/loop_unroll: Prepare loop for unrolling in wrapper_unroll
  
  Without loop_prepare_for_unroll loops are losing phis.
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111411
  Fixes: 5db98195 "nir: add loop unroll support for wrapper loops"
  Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
  Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
  (cherry picked from commit 84b3ef6a96eabc28b18e8cdf1b0d61826b1a8a67)
  

• 3ab1368c
  by Samuel Pitoiset at 2019-09-04T18:50:53Z

  radv: allow to enable VK_AMD_shader_ballot only on GFX8+
  
  Scans aren't implemented on SI/CIK.
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org>
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit e73d863a66caac796ed5fb543a77f0b892df8573)
  

• 690f0506
  by Samuel Pitoiset at 2019-09-04T18:50:59Z

  radv: add a new debug option called RADV_DEBUG=noshaderballot
  
  Shader ballot will be enabled by default for Wolfenstein
  Youngblood. This follows what we did for sisched.
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit f202ac27a99caf9009aa9d60e2e0d7f3b528e99f)
  

• 637a9cbd
  by Samuel Pitoiset at 2019-09-04T18:51:15Z

  radv: force enable VK_AMD_shader_ballot for Wolfenstein Youngblood
  
  This gives a nice boost, +20% at this time on my Vega 56. Shader
  ballot should be enabled by default at some point but it reduces
  performance a bit (-6%) with Wolfeinstein II. Enable it only for
  Youngblood at the moment, like what we did for Talos in the past.
  
  As a bonus point, it gets rid of some minor artifacts that only
  happens when ballot is disabled for some reasons.
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit a6ad9e8ccf970a0da68508eb2ce26b316045b9f0)
  

• 0504bff3
  by Jose Maria Casanova Crespo at 2019-09-04T18:51:25Z

  mesa: recover target_check before get_current_tex_objects
  
  At compressed_tex_sub_image we only can obtain the tex_object after
  compressed_subtexture_target_check is validated for TEX_MODE_CURRENT.
  So if the target is wrong the error is raised to the user.
  
  This completes the fix for the regression introduced on "mesa: refactor
  compressed_tex_sub_image function" of the pending failing tests:
  
  dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage3d
  dEQP-GLES31.functional.debug.negative_coverage.get_error.texture.compressedtexsubimage3d
  
  v2: Fix warning that texObj might be used uninitialized (Gert Wollny)
  
  Fixes: 7df233d68dc ("mesa: refactor compressed_tex_sub_image function")
  Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
  (cherry picked from commit 74a7e3ed3b297f441b406ff62ef9ba504ba3b06c)
  

• 07760c1c
  by Kenneth Graunke at 2019-09-04T18:51:31Z

  gallium/ddebug: Wrap resource_get_param if available
  
  Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
  Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit 0e6b573ae57da2fd15891c7e9d2a9024203aa507)
  

• 6e6f137a
  by Kenneth Graunke at 2019-09-04T18:51:39Z

  gallium/trace: Wrap resource_get_param if available
  
  Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
  Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit c43a44791bfce12da6fb86e05a29fc819c1c1878)
  

• 813ed862
  by Kenneth Graunke at 2019-09-04T18:51:44Z

  gallium/rbug: Wrap resource_get_param if available
  
  Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
  Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit f02d1a0b75c72f600ecdd73020673e4bec015153)
  

• 844fbc5c
  by Kenneth Graunke at 2019-09-04T18:51:50Z

  gallium/noop: Implement resource_get_param
  
  v2: Pass through to oscreen rather than faking it (review from Marek).
  
  Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit bc844d92ce0fd000a85c370ecef27ad42a27cf14)
  

• 6af303f6
  by Tapani Pälli at 2019-09-04T18:51:55Z

  util: fix os_create_anonymous_file on android
  
  Commit fixes current crashes with Vulkan applications on Android.
  
  Fixes: c0376a123418 "util: add anon_file.h for all memfd/temp file usage"
  Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
  Reviewed-by: Eric Engestrom <eric@engestrom.ch>
  (cherry picked from commit ce8fd042a5b0130cc5c62981828b122127711712)
  

• 7c615873
  by Samuel Pitoiset at 2019-09-04T18:52:02Z

  ac: fix exclusive scans on GFX8-GFX9
  
  This fixes a regression introduced with scan&reduce operations
  on GFX10. Note that some subgroups CTS still fail on GFX10 but
  I assume it's a different issue.
  
  This fixes dEQP-VK.subgroups.arithmetic.*.subgroupexclusive*.
  
  Fixes: 227c29a80de "amd/common/gfx10: implement scan & reduce operations"
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit 2d9f401a830693cd2a97a25ee49c0671606b1878)
  

• 18511e3f
  by Tapani Pälli at 2019-09-04T18:52:09Z

  iris/android: fix build and link with libmesa_intel_perf
  
  Fixes: 0fd4359733e "iris/perf: implement routines to return counter info"
  Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
  Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
  (cherry picked from commit 728ebcdec2bfc38f28fd7feb3b89194c64287ac6)
  

• 4385e6cf
  by Lionel Landwerlin at 2019-09-04T18:52:26Z

  util/timespec: use unsigned 64 bit integers for nsec values
  
  We added this utility for vulkan where all timeouts are given as
  uint64_t values. We can switch from signed to unsigned as this is the
  only user and if we ever deal with signed integers somewhere else
  we'll have to be careful to use the corresponding
  timespec_(add|sub)_msec and always pass absolute values.
  
  v2: Forgot to drop the test calling add_nsec() with a negative number
  
  Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
  Reported-by: Juan A. Suarez Romero <jasuarez@igalia.com>
  Fixes: d2d70c3bb5 ("util: add a timespec helper")
  Acked-by: Daniel Stone <daniels@collabora.com>
  (cherry picked from commit 5833f433055cbc259bfe53286a6d3f6687fdd7db)
  

• bd0300f8
  by Bas Nieuwenhuizen at 2019-09-04T18:52:30Z

  radv: Disable NGG for geometry shaders.
  
  A bunch of remaining issues including some that affect users.
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111248
  Fixes: ee21bd7440c "radv/gfx10: implement NGG support (VS only)"
  Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  (cherry picked from commit c037fe5ad1b3556809e5a549306a52a8a8bd1cbf)
  

• 58acce6d
  by Alyssa Rosenzweig at 2019-09-04T18:52:36Z

  pan/midgard: Fix writeout combining
  
  shader-db regression in the scheduler.
  
  Fixes: dff4986b1aa ("pan/midgard: Emit store_output branch just-in-time")
  
  total bundles in shared programs: 2055 -> 2019 (-1.75%)
  bundles in affected programs: 1055 -> 1019 (-3.41%)
  helped: 36
  HURT: 0
  helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
  helped stats (rel) min: 0.35% max: 20.00% x̄: 6.71% x̃: 5.16%
  95% mean confidence interval for bundles value: -1.00 -1.00
  95% mean confidence interval for bundles %-change: -8.45% -4.97%
  Bundles are helped.
  
  total quadwords in shared programs: 3444 -> 3408 (-1.05%)
  quadwords in affected programs: 1897 -> 1861 (-1.90%)
  helped: 36
  HURT: 0
  helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
  helped stats (rel) min: 0.19% max: 14.29% x̄: 3.97% x̃: 2.99%
  95% mean confidence interval for quadwords value: -1.00 -1.00
  95% mean confidence interval for quadwords %-change: -5.08% -2.86%
  Quadwords are helped.
  
  Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  (cherry picked from commit 272ce6f5a7cd646be495f1d71918476e94b29c4b)
  

• 973d58e9
  by Kenneth Graunke at 2019-09-04T18:52:41Z

  iris: Replace devinfo->gen with GEN_GEN
  
  This is genxml, we can compile out this code.
  
  Fixes: 26606672847 ("iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.")
  Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
  (cherry picked from commit f6c44549ee2dd0f218deea1feba3965523609406)
  

• 14588c07
  by Kenneth Graunke at 2019-09-04T18:52:46Z

  iris: Fix broken aux.possible/sampler_usages bitmask handling
  
  For renderable surfaces, we allocate SURFACE_STATEs for each bit in
  res->aux.possible_usages.  Sampler views use res->aux.sampler_usages.
  
  When pinning buffers, we call surf_state_offset_for_aux() to calculate
  the offset to the desired surface state.  surf_state_offset_for_aux()
  took an aux_modes parameter, which should be one of those two fields.
  However...it was not using that parameter.  It always used the broader
  res->aux.possible_usages field directly.
  
  One of the callers, update_clear_value(), was passing incorrect masks
  for this parameter.  It iterated through the bits in order, using
  u_bit_scan(), which destructively modifies the mask.  So each time we
  called it, the count of bits before our selected mode was 0, which would
  cause us to always update the SURFACE_STATE for ISL_AUX_USAGE_NONE,
  rather than updating each in turn.  This was hidden by the earlier bug
  where surf_state_offset_for_aux() ignored the parameter.
  
  Fixes: 7339660e803 ("iris: Add aux.sampler_usages.")
  Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
  (cherry picked from commit 117a0368b0cc741aec88d2538ffdebd26618a6fb)
  

• 1be5f26c
  by Kenneth Graunke at 2019-09-04T18:52:53Z

  iris: Update fast clear colors on Gen9 with direct immediate writes.
  
  Gen11 stores the fast clear color in an "indirect clear buffer", as
  a packed pixel value.  Gen9 hardware stores it as a float or integer
  value, which is interpreted via the format.  We were trying to store
  that in a buffer, for similarity with Icelake, and MI_COPY_MEM_MEM
  it from there to the actual SURFACE_STATE bytes where it's stored.
  
  This unfortunately doesn't work for blorp_copy(), which does bit-for-bit
  copies, and overrides the format to a CCS-compatible UINT format.  This
  causes the clear color to be interpreted in the overridden format.
  
  Normally, we provide the clear color on the CPU, and blorp_blit.c:2611
  converts it to a packed pixel value in the original format, then unpacks
  it in the overridden format, so the clear color we use expands to the
  bits we originally desired.
  
  However, BLORP doesn't support this pack/unpack with an indirect clear
  buffer, as it would need to do the math on the GPU.  On Gen11+, it isn't
  necessary, as the hardware does the right thing.
  
  This patch changes Gen9 to stop using an indirect clear buffer and
  simply do PIPE_CONTROLs with post-sync write immediate operations
  to store the new color over the surface states for regular drawing.
  BLORP continues streaming out surface states, and handles fast clear
  colors on the CPU.
  
  Fixes: 53c484ba8ac ("iris: blorp using resolve hooks")
  Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
  (cherry picked from commit 1cd13ccee7bc2733e7a56284dc02bdb1b1c40081)
  

• d78f39eb
  by Kenneth Graunke at 2019-09-04T18:54:05Z

  iris: Drop copy format hacks from copy region based transfer path.
  
  This doesn't work for compressed formats, as the source texture and
  temporary texture would have different block sizes.  (Forcing the driver
  to always take the GPU path would expose the bug.)  Instead, just use
  the source format for the temporary, and let blorp_copy deal with
  overrides.
  
  The one case where we can't do this is ASTC, because isl won't let us
  create a linear ASTC surface.  Fall back to the CPU paths there for now.
  
  Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls")
  Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
  (cherry picked from commit 136629a1e3aace12297ff61c2ee32caa21aba99b)
  

• dff3ab5c
  by Kenneth Graunke at 2019-09-04T18:54:10Z

  iris: Avoid unnecessary resolves on transfer maps
  
  We were always resolving the buffer as if we were accessing it via
  CPU maps, which don't understand any auxiliary surfaces.  But we often
  copy to a temporary using BLORP, which understands compression just
  fine.  So we can avoid the resolve, and accelerate the copy as well.
  
  Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls")
  Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
  (cherry picked from commit 2d799250346331a93b21678dc5605cff74dfa3a1)
  

• 966a2bdc
  by Tapani Pälli at 2019-09-04T18:54:16Z

  egl: reset blob cache set/get functions on terminate
  
  Fixes errors seen with eglSetBlobCacheFuncsANDROID on Android when
  running dEQP that terminates and reinitializes a display.
  
  Fixes: 6f5b57093b3 "egl: add support for EGL_ANDROID_blob_cache"
  Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
  Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
  (cherry picked from commit 3e03a3fc5315b488468b28aa40a7e9416f506520)
  

• 7200ed13
  by Samuel Pitoiset at 2019-09-04T18:54:20Z

  radv/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
  
  Only gfx9 and older use it to get InstanceID in VGPR1.
  Ported from RadeonSI.
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org>
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit 0813c27d8d4a7e9372a8a86d970b598fc4e3bfd1)
  

• 649040ed
  by Samuel Pitoiset at 2019-09-04T18:54:25Z

  radv/gfx10: do not use NGG with NAVI14
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org>
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit a4e6e59db82e61b47ef905f28dde80ae36a67d35)
  

• 5c136258
  by Kenneth Graunke at 2019-09-04T18:54:29Z

  iris: Fix large timeout handling in rel2abs()
  
  ...by copying the implementation of anv_get_absolute_timeout().
  
  Appears to fix a CTS test with 32-bit builds:
  GTF-GL46.gtf32.GL3Tests.sync.sync_functionality_clientwaitsync_flush
  
  Fixes: f459c56be6b ("iris: Add fence support using drm_syncobj")
  Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
  Reviewed-by: Eric Engestrom <eric@engestrom.ch>
  (cherry picked from commit 7ee7b0ecbc0de098cba631b2ca0b3291c3817665)
  

• 9fff4192
  by Andres Rodriguez at 2019-09-04T18:54:34Z

  radv: additional query fixes
  
  Make sure we read the updated data from the gpu in cases where WAIT_BIT
  is not set.
  
  Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org
  Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  (cherry picked from commit a410823b3ede9ff3bf7f56ffca295d1b3d04dbad)
  

• 7ff682a1
  by Lionel Landwerlin at 2019-09-04T18:54:45Z

  util: fix compilation on macos
  
  timespec_get() is not available on macos, we need to pull in the
  include/c11/threads_posix.h helper.
  
  Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103674
  Fixes: e2d761de03 ("util: drop final reference to p_compiler.h")
  Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
  (cherry picked from commit 9d3fc737afcb98e3882b4d54c9d093980cfb4874)
  

• 1ec895b4
  by Rafael Antognolli at 2019-09-04T18:54:49Z

  anv: Only re-emit non-dynamic state that has changed.
  
  On commit f6e7de41d7b, we started emitting 3DSTATE_LINE_STIPPLE as part
  of the non-dynamic state. That gets re-emitted every time we bind a new
  VkPipeline. But that instruction is non-pipelined, and it caused a perf
  regression of about 9-10% on Dota2.
  
  This commit makes anv_dynamic_state_copy() return a mask with only the
  state that has changed when copying it. 3DSTATE_LINE_STIPPLE won't be
  emitted anymore unless it has changed, fixing the problem above.
  
  v2: Improve commit message and add documentation about skipped checks
  (Jason)
  
  Fixes: f6e7de41d7b ("anv: Implement VK_EXT_line_rasterization")
  Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
  Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
  (cherry picked from commit 2b7ba9f239c09049408d86eb71be18887691dc58)
  

• 6ea07af9
  by Alex Smith at 2019-09-04T18:55:00Z

  radv: Change memory type order for GPUs without dedicated VRAM
  
  Put the uncached GTT type at a higher index than the visible VRAM type,
  rather than having GTT first.
  
  When we don't have dedicated VRAM, we don't have a non-visible VRAM
  type, and the property flags for GTT and visible VRAM are identical.
  According to the spec, for types with identical flags, we should give
  the one with better performance a lower index.
  
  Previously, apps which follow the spec guidance for choosing a memory
  type would have picked the GTT type in preference to visible VRAM (all
  Feral games will do this), and end up with lower performance.
  
  On a Ryzen 5 2500U laptop (Raven Ridge), this improves average FPS in
  the Rise of the Tomb Raider benchmark by up to ~30%. Tested a couple of
  other (Feral) games and saw similar improvement on those as well.
  
  Signed-off-by: Alex Smith <asmith@feralinteractive.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
  Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Cc: 19.2 <mesa-stable@lists.freedesktop.org>
  (Bas: CCing this to 19.2-rc due to high impact and limited complexity)
  (cherry picked from commit fe0ec41c4d36fd5a82e7579d89e34cce7423c4e5)
  

• 7d8eee2b
  by Dave Airlie at 2019-09-04T18:55:04Z

  virgl: fix format conversion for recent gallium changes.
  
  The virgl formats are fixed in time snapshots of the gallium ones,
  we just need to provide a translation table between them when
  we enter the hardware.
  
  This fixes a regression since Eric renumbered the gallium table.
  
  Fixes: c45c33a5a2 (gallium: Remove manual defining of PIPE_FORMAT enum values.)
  Bugzilla: https://bugs.freedesktop.org/111454
  
  v1 by Dave Airlie <airlied@redhat.com>
  v2: virgl: Add a number of formats to the table that are used, e.g. for vertex
      attributes
  v3: cover some more missing formats from a piglit run
  
  Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
  (cherry picked from commit bba4d2f442f33bc68a4573a6f1f559f277d7ec51)
  

• 80514527
  by Samuel Pitoiset at 2019-09-04T18:55:09Z

  radv: fix getting the index type size for uint8_t
  
  16-bit and 32-bit values match hardware values but 8-bit doesn't.
  
  This fixes dEQP-VK.pipeline.input_assembly.* with 8-bit index.
  
  Fixes: 372c3dcfdb8 ("radv: implement VK_EXT_index_type_uint8")
  Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
  Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
  (cherry picked from commit 89671ef205fa93d391e01884da48a876847a5682)
  

• b871874d
  by Kenneth Graunke at 2019-09-04T18:55:17Z

  isl: Drop UnormPathInColorPipe for buffer surfaces.
  
  Jason suggested I remove this in review, and he's right.  AFAICT this
  affects blending, and that just isn't going to happen on buffers.
  
  Fixes: f741de236b5 ("isl: Enable Unorm Path in Color Pipe")
  Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
  (cherry picked from commit 1b090f065e0f39856ef4b228091f76241f1bbe2b)
  

• 7160c70f
  by Kenneth Graunke at 2019-09-04T18:55:22Z

  isl: Don't set UnormPathInColorPipe for integer surfaces.
  
  This fixes dEQP-GLES3.functional.texture.specification subtests on iris:
  
  - texsubimage3d_depth.depth24_stencil8_2d_array
  - texsubimage3d_depth.depth32f_stencil8_2d_array
  - texsubimage3d_depth.depth_component32f_2d_array
  - texsubimage3d_depth.depth_component24_2d_array
  - texstorage2d.format.depth24_stencil8_2d
  - texstorage2d.format.depth32f_stencil8_2d
  - texstorage2d.format.depth_component24_2d
  - texstorage2d.format.depth_component32f_2d
  - texstorage3d.format.depth24_stencil8_2d_array
  - texstorage3d.format.depth32f_stencil8_2d_array
  - texstorage3d.format.depth_component24_2d_array
  - texstorage3d.format.depth_component32f_2d_array
  
  Here, something appears to be going wrong with having this bit set
  during blorp_copy operations for texture upload, which override the
  format to R8G8B8A8_UINT.
  
  AFAICT this bit should have no effect for integer surfaces, as it has
  to do with blending, and integer blending is not a thing.  So it should
  be harmless to disable it.
  
  The Windows driver appears to be setting this bit universally, so
  I am unclear why we would need to.  Perhaps they simply haven't run
  into this issue.
  
  Fixes: f741de236b5 ("isl: Enable Unorm Path in Color Pipe")
  Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
  (cherry picked from commit 2e1be771e47adf1d06901283ffb8df0d83f28b3c)
  

• 6e07e58e
  by Paulo Zanoni at 2019-09-04T18:55:31Z

  intel/fs: grab fail_msg from v32 instead of v16 when v32->run_cs fails
  
  Looks like a copy/paste error. This patch prevents a segfault when
  running the following on BDW:
  
      INTEL_DEBUG=no8,no16,do32 ./deqp-vk -n \
          dEQP-VK.subgroups.arithmetic.compute.subgroupmin_dvec4
  
  For the curious, the message we're getting is:
  
      CS compile failed: Failure to register allocate.  Reduce number
      of live scalar values to avoid this.
  
  Fixes: 864737ce6cd5 ("i965/fs: Build 32-wide compute shader when needed.")
  Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
  Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
  (cherry picked from commit 848d5e444a881a1a3ac6824f07d95988b312530b)
  

• 9433241c
  by Dave Airlie at 2019-09-04T18:55:35Z

  gallivm: fix atomic compare-and-swap
  
  Not sure how I missed this before, but compswap was hitting an
  assert here as it is it's own special case.
  
  Fixes: b5ac381d8f ("gallivm: add buffer operations to the tgsi->llvm conversion.")
  Reviewed-by: Roland Scheidegger <sroland@vmware.com>
  (cherry picked from commit 1eda49cc3de22e97a70944367d17d5afe611f3cc)
  

• 952fd550
  by Marek Olšák at 2019-09-04T18:55:40Z

  radeonsi: unbind blend/DSA/rasterizer state correctly in delete functions
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111414
  
  Fixes: b758eed9c37 ("radeonsi: make sure that blend state != NULL and remove all NULL checking")
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org>
  Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
  Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
  (cherry picked from commit f95a28d361e9dc542f49d88ccad112ca2beeedf2)
  

• c2aad5dc
  by Marek Olšák at 2019-09-04T18:55:44Z

  radeonsi: fix scratch buffer WAVESIZE setting leading to corruption
  
  Cc: 19.2 19.1 <mesa-stable@lists.freedesktop.org>
  Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
  (cherry picked from commit 360cf3c4b05679709574ef4d20b5097b0fd0be82)
  

• 07ac4269
  by Kenneth Graunke at 2019-09-04T18:55:50Z

  util: Add a _mesa_i64roundevenf() helper.
  
  This always returns a int64_t, translating to _mesa_lroundevenf on
  systems where long is 64-bit, and llrintf where "long long" is needed.
  
  Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().")
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  Reviewed-by: Matt Turner <mattst88@gmail.com>
  (cherry picked from commit b59914e179a9e5930af37e7f7c0d8eafd682caff)
  

• c96de002
  by Kenneth Graunke at 2019-09-04T18:56:04Z

  mesa: Fix _mesa_float_to_unorm() on 32-bit systems.
  
  This fixes the following CTS test on 32-bit systems:
  GTF-GL46.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_init
  
  It does glGetTexImage of a 16-bit SNORM image, requesting 32-bit UNORM
  data.  In get_tex_rgba_uncompressed, we round trip through float to
  handle image transfer ops for clamping.  _mesa_format_convert does:
  
     _mesa_float_to_unorm(0.571428597f, 32)
  
  which translated to:
  
     _mesa_lroundevenf(0.571428597f * 0xffffffffu)
  
  which produced different results on 64-bit and 32-bit systems:
  
     64-bit: result = 0x92492500
     32-bit: result = 0x80000000
  
  This is because the size of "long" varies between the two systems, and
  0x92492500 is too large to fit in a signed 32-bit integer.  To fix this,
  we switch to the new _mesa_i64roundevenf function which always does the
  64-bit operation.
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104395
  Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().")
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  Reviewed-by: Matt Turner <mattst88@gmail.com>
  (cherry picked from commit e18cd5452aa4434fb22105eb939843381771b91c)
  

• 91fa24a6
  by Ian Romanick at 2019-09-04T18:56:08Z

  nir/algrbraic: Don't optimize open-coded bitfield reverse when lowering is enabled
  
  This caused a problem on Sandybridge where an open-coded
  bitfieldReverse() function could be optimized to a
  nir_op_bitfield_reverse that would generate an unsupported BFREV
  instruction in the backend.  This was encountered in some Unreal4 tech
  demos in shader-db.  The bug was not previously noticed because we don't
  actually try to run those demos on Sandybridge.
  
  The fixes tag is a bit a lie.  The actual bug was introduced about
  26,000 commits earlier in 371c4b3c48f ("nir: Recognize open-coded
  bitfield_reverse.").  Without the NIR lowering pass, the flag needed to
  avoid the optimization does not exist.  Hopefully nobody will care to
  fix this on an earlier Mesa release.
  
  Reviewed-by: Matt Turner <mattst88@gmail.com>
  Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.")
  (cherry picked from commit d3fd1c761aab01e06665180ab86c9528c0b285b2)
  

• 753ea834
  by Ian Romanick at 2019-09-04T18:56:12Z

  intel/compiler: Request bitfield_reverse lowering on pre-Gen7 hardware
  
  See the previous commit for the explanation of the Fixes tag.
  
  Hurts 21 shaders in shader-db.  All of the hurt shaders are in Unreal
  Engine 4 tech demos.
  
  Reviewed-by: Matt Turner <mattst88@gmail.com>
  Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.")
  (cherry picked from commit b418269d7dd576a7c9afd728bf8a883b4da98b30)
  

• da03ddf6
  by Kenneth Graunke at 2019-09-04T18:56:30Z

  iris: Fix partial fast clear checks to account for miplevel.
  
  We enabled fast clears at level > 0, but didn't minify the dimensions
  when comparing the box size, so we always thought it was a partial
  clear and as a result never actually enabled any.
  
  This eliminates some slow clears in Civilization VI, but they are mostly
  during initialization and not the main rendering.
  
  Thanks to Dan Walsh for noticing we had too many slow clears.
  
  Fixes: 393f659ed83 ("iris: Enable fast clears on other miplevels and layers than 0.")
  Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
  (cherry picked from commit 30b9ed92ea423a4857023ca5e2222ae409672fa5)
  

• 2971f079
  by Ian Romanick at 2019-09-04T18:56:34Z

  nir/algebraic: Mark some value range analysis-based optimizations imprecise
  
  This didn't fix bug #111308, but it was found will trying to find the
  actual cause of that bug.
  
  Fixes piglit tests (new in piglit!110):
  
      - fs-fract-of-NaN.shader_test
      - fs-lt-nan-tautology.shader_test
      - fs-ge-nan-tautology.shader_test
  
  No shader-db changes on any Intel platform.
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111308
  Fixes: b77070e293c ("nir/algebraic: Use value range analysis to eliminate tautological compares")
  Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
  (cherry picked from commit ccb236d1bc6375bdf9bc47550bdfa348ea7369b9)
  

• a8525d77
  by Ian Romanick at 2019-09-04T18:56:39Z

  nir/range-analysis: Adjust result range of exp2 to account for flush-to-zero
  
  Fixes piglit tests (new in piglit!110):
  
      - fs-underflow-exp2-compare-zero.shader_test
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111308
  Fixes: 405de7ccb6c ("nir/range-analysis: Rudimentary value range analysis pass")
  Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
  
  Most of the shaders affected are, unsurprisingly, in Unigine Heaven.
  
  All Gen6+ platforms had similar results. (Ice Lake shown)
  total instructions in shared programs: 16278207 -> 16278465 (<.01%)
  instructions in affected programs: 11374 -> 11632 (2.27%)
  helped: 0
  HURT: 58
  HURT stats (abs)   min: 2 max: 13 x̄: 4.45 x̃: 4
  HURT stats (rel)   min: 0.54% max: 4.11% x̄: 2.42% x̃: 2.82%
  95% mean confidence interval for instructions value: 3.77 5.13
  95% mean confidence interval for instructions %-change: 2.19% 2.64%
  Instructions are HURT.
  
  total cycles in shared programs: 367134284 -> 367135159 (<.01%)
  cycles in affected programs: 81207 -> 82082 (1.08%)
  helped: 17
  HURT: 36
  helped stats (abs) min: 6 max: 356 x̄: 90.35 x̃: 6
  helped stats (rel) min: 0.69% max: 21.45% x̄: 5.71% x̃: 0.78%
  HURT stats (abs)   min: 4 max: 235 x̄: 66.97 x̃: 16
  HURT stats (rel)   min: 0.35% max: 27.58% x̄: 5.34% x̃: 1.09%
  95% mean confidence interval for cycles value: -20.36 53.38
  95% mean confidence interval for cycles %-change: -1.08% 4.67%
  Inconclusive result (value mean confidence interval includes 0).
  
  No changes on any earlier platforms.
  
  (cherry picked from commit 33ad2bab4bcb52c0f6be56e2f9cce5f52601a4ea)
  

• 97e44d68
  by Ian Romanick at 2019-09-04T18:56:43Z

  nir/range-analysis: Adjust result range of multiplication to account for flush-to-zero
  
  Fixes piglit tests (new in piglit!110):
  
      - fs-underflow-fma-compare-zero.shader_test
      - fs-underflow-mul-compare-zero.shader_test
  
  v2: Add back part of comment accidentally deleted.  Noticed by
  Caio. Remove is_not_zero function as it is no longer used.
  
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111308
  Fixes: fa116ce357b ("nir/range-analysis: Range tracking for ffma and flrp")
  Fixes: 405de7ccb6c ("nir/range-analysis: Rudimentary value range analysis pass")
  Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
  
  All Gen7+ platforms** had similar results. (Ice Lake shown)
  total instructions in shared programs: 16278465 -> 16279492 (<.01%)
  instructions in affected programs: 16765 -> 17792 (6.13%)
  helped: 0
  HURT: 23
  HURT stats (abs)   min: 7 max: 275 x̄: 44.65 x̃: 8
  HURT stats (rel)   min: 1.15% max: 17.51% x̄: 4.23% x̃: 1.62%
  95% mean confidence interval for instructions value: 9.57 79.74
  95% mean confidence interval for instructions %-change: 1.85% 6.61%
  Instructions are HURT.
  
  total cycles in shared programs: 367135159 -> 367154270 (<.01%)
  cycles in affected programs: 279306 -> 298417 (6.84%)
  helped: 0
  HURT: 23
  HURT stats (abs)   min: 13 max: 6029 x̄: 830.91 x̃: 54
  HURT stats (rel)   min: 0.17% max: 45.67% x̄: 7.33% x̃: 0.49%
  95% mean confidence interval for cycles value: 100.89 1560.94
  95% mean confidence interval for cycles %-change: 0.94% 13.71%
  Cycles are HURT.
  
  total spills in shared programs: 8870 -> 8869 (-0.01%)
  spills in affected programs: 19 -> 18 (-5.26%)
  helped: 1
  HURT: 0
  
  total fills in shared programs: 21904 -> 21901 (-0.01%)
  fills in affected programs: 81 -> 78 (-3.70%)
  helped: 1
  HURT: 0
  
  LOST:   0
  GAINED: 1
  
  ** On Broadwell, a shader was hurt for spills / fills instead of
     helped.
  
  No changes on any earlier platforms.
  
  (cherry picked from commit ef2e235252ea3dbadad79bb48c760bb6c376b97c)
  

• 6aa7a103
  by Ian Romanick at 2019-09-04T18:56:54Z

  nir/range-analysis: Fix incorrect fadd range result for (ne_zero, ne_zero)
  
  Found by inspection.  I tried really, really hard to make a test case
  that would trigger this problem, but I was unsuccesful.  It's very hard
  to get an instruction to produce a ne_zero result without ne_zero
  sources.  The most plausible way is using bcsel.  That proves
  problematic because bcsel interprets its sources as integers, so it
  cannot currently be used to "clean" values for floating point
  instructions.
  
  No shader-db changes on any Intel platform.
  
  Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
  Fixes: 405de7ccb6c ("nir/range-analysis: Rudimentary value range analysis pass")
  (cherry picked from commit 0b4782fccd22b0a01ded1e4cbfe06821bdf19d05)
  

• 6934bc4f
  by Ian Romanick at 2019-09-04T18:56:59Z

  nir/range-analysis: Handle constants in nir_op_mov just like nir_op_bcsel
  
  I discovered this while looking at a shader that was hurt by some other
  work I'm doing.  When I examined the changes, I was confused that one
  instance of a comparison that was used in a discard_if was (incorrectly)
  eliminated, while another instance used by a bcsel was (correctly) not
  eliminated.  I had to use NIR_PRINT=true to see exactly where things
  when wrong.
  
  A bunch of shaders in Goat Simulator, Dungeon Defenders, Sanctum 2, and
  Strike Suit Zero were impacted.
  
  Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
  Fixes: 405de7ccb6c ("nir/range-analysis: Rudimentary value range analysis pass")
  
  All Intel platforms had similar results. (Ice Lake shown)
  total instructions in shared programs: 16280659 -> 16281075 (<.01%)
  instructions in affected programs: 21042 -> 21458 (1.98%)
  helped: 0
  HURT: 136
  HURT stats (abs)   min: 1 max: 9 x̄: 3.06 x̃: 3
  HURT stats (rel)   min: 1.16% max: 6.12% x̄: 2.23% x̃: 2.03%
  95% mean confidence interval for instructions value: 2.93 3.19
  95% mean confidence interval for instructions %-change: 2.08% 2.37%
  Instructions are HURT.
  
  total cycles in shared programs: 367168270 -> 367170313 (<.01%)
  cycles in affected programs: 172020 -> 174063 (1.19%)
  helped: 14
  HURT: 111
  helped stats (abs) min: 2 max: 80 x̄: 21.21 x̃: 9
  helped stats (rel) min: 0.10% max: 4.47% x̄: 1.35% x̃: 0.79%
  HURT stats (abs)   min: 2 max: 584 x̄: 21.08 x̃: 5
  HURT stats (rel)   min: 0.12% max: 17.28% x̄: 1.55% x̃: 0.40%
  95% mean confidence interval for cycles value: 5.41 27.28
  95% mean confidence interval for cycles %-change: 0.64% 1.81%
  Cycles are HURT.
  
  (cherry picked from commit 7dba7df5e577b94e009848a2ca3e0b0a41629fe9)
  

• ec74c76a
  by Thong Thai at 2019-09-04T18:57:03Z

  Revert "radeonsi: don't emit PKT3_CONTEXT_CONTROL on amdgpu"
  
  This reverts commit 5a2e65be89d97ed5d7263f0296ea69ae8517187b.
  
  Even though CONTEXT_CONTROL is emitted by the kernel, CONTEXT_CONTROL
  still needs to be emitted by the UMD, or else the driver will hang
  
  Cc: 19.2 <mesa-stable@lists.freedesktop.org>
  Signed-off-by: Thong Thai <thong.thai@amd.com>
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit 2a3a5604076e94445079a0b25aa108ee99b5fcba)
  

• efa4aee9
  by Pierre-Eric Pelloux-Prayer at 2019-09-04T18:57:07Z

  glsl: replace 'x + (-x)' with constant 0
  
  This fixes a hang in shadertoy for radeonsi where a buffer was initialized with:
  
     value -= value
  
  with value being undefined.
  In this case LLVM replace the operation with an assignment to NaN.
  
  Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org>
  Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111241
  Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  (cherry picked from commit 47cc660d9c19572e5ef2dce7c8ae1766a2ac9885)
  

• 7f9b4921
  by Dylan Baker at 2019-09-04T21:22:26Z

  bump version to 19.2-rc2
  

• dade3cd2
  by Timo Aaltonen at 2019-09-05T10:38:23Z

  Merge branch 'upstream-experimental' into debian-experimental
  

• cde5bebd
  by Timo Aaltonen at 2019-09-05T10:39:19Z

  bump the version
  

• a116cc1f
  by Vinson Lee at 2019-09-05T10:58:20Z

  swr: Fix build with llvm-9.0 again.
  
  Commit 6f7306c029a7 ("swr/rast: Refactor memory API between rasterizer
  core and swr") unintentionally removed changes for llvm-9.0.
  
  Fixes: 6f7306c029a7 ("swr/rast: Refactor memory API between rasterizer core and swr")
  Fixes: 5dd9ad157005 ("swr/rasterizer: Better implementation of scatter")
  Signed-off-by: Vinson Lee <vlee@freedesktop.org>
  Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
  (cherry picked from commit 3664a6600eb0efbb4606f0b59730df3088b3b490)
  (cherry picked from commit 529db83e7b467a952529c721b68bfb81ddabc72c)
  

• 2166565e
  by Timo Aaltonen at 2019-09-05T18:40:48Z

  control, rules: Drop libva-dev from build-depends, don't use dh_libva and drop pkg.mesa.nolibva build profile, libva2 transition is done.
  

30 changed files:

• VERSION
• debian/changelog
• debian/control
• debian/rules
• include/pci_ids/radeonsi_pci_ids.h
• src/amd/common/ac_llvm_build.c
• src/amd/common/sid.h
• src/amd/vulkan/radv_cmd_buffer.c
• src/amd/vulkan/radv_debug.h
• src/amd/vulkan/radv_device.c
• src/amd/vulkan/radv_pipeline.c
• src/amd/vulkan/radv_query.c
• src/amd/vulkan/radv_shader.c
• src/amd/vulkan/si_cmd_buffer.c
• src/compiler/glsl/opt_algebraic.cpp
• src/compiler/nir/nir_opt_algebraic.py
• src/compiler/nir/nir_opt_loop_unroll.c
• src/compiler/nir/nir_range_analysis.c
• src/egl/main/eglapi.c
• src/gallium/auxiliary/driver_ddebug/dd_screen.c
• src/gallium/auxiliary/driver_noop/noop_pipe.c
• src/gallium/auxiliary/driver_rbug/rbug_screen.c
• src/gallium/auxiliary/driver_trace/tr_screen.c
• src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
• src/gallium/auxiliary/util/u_screen.c
• src/gallium/auxiliary/vl/vl_compositor.c
• src/gallium/docs/source/screen.rst
• src/gallium/drivers/iris/Android.mk
• src/gallium/drivers/iris/Makefile.sources
• src/gallium/drivers/iris/iris_clear.c

The diff was not included because it is too large.

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