-
bc1503b1
by Juan A. Suarez Romero
at 2018-01-18T22:34:34+01:00
docs: add sha256 checksums for 17.3.3
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
694ed0d6
by Gert Wollny
at 2018-01-24T19:27:19+00:00
r600/shader: Initialize max_driver_temp_used correctly for the first time
Without this initialization the temp registers used in tgsi_declaration
may used random indices, and this may result in failing translation from TGSI
with an error message "GPR limit exceeded", because the random index is greater
then the allowed limit implying that the shader uses more temporary registers then
available.
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5d6470d26b267d522dd343740878bde46f21c446)
-
510f1b3c
by Grazvydas Ignotas
at 2018-01-24T19:27:19+00:00
st/va: release held locks in error paths
Found with the help of following Coccinelle semantic patch:
// <smpl>
@@
_expression_ E;
@@
\(pthread_mutex_lock\|mtx_lock\|simple_mtx_lock\)(E)
...
(
\(pthread_mutex_unlock\|mtx_unlock\|simple_mtx_unlock\)(E);
...
return ...;
|
+ maybe need_unlock(E);
return ...;
)
// </smpl>
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0ad73031ec2f9dee6d3ad20dd625b0134ea8ec8b)
-
e66bafa9
by Jason Ekstrand
at 2018-01-24T19:27:19+00:00
i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer
This makes sure we flush things out of other caches prior to using a
surface through the render cache. Currently, this is a no-op because GL
won't let you bind anything other than a color surface as color so it
should never end up in the depth cache. However, this does complete the
flush/add_bo pair for regular drawing which will be required for the
next commit.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 622786c20c6cd073071b00ddf6e50c447f8c5768)
-
6f5752db
by Jason Ekstrand
at 2018-01-24T20:11:50+00:00
i965: Add more precise cache tracking helpers
In theory, this will let us track the depth and render caches
separately. Right now, they're just wrappers around
brw_render_cache_set_*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 4a09070295294e9017fa686fc8e113989ef0f41b)
-
0bbd60f3
by Jason Ekstrand
at 2018-01-24T20:14:45+00:00
i965/blorp: Add more destination flushing
Right now we just always flush the destination for render and aren't
particularly careful about depth or stencil. Soon, flush_for_render
isn't going to do the same thing as flush_for_depth and we may be doing
a good deal less depth flushing so we should be a bit more precise.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d6d0ac95d5d77bd18b2064c3ed9aad70cf38cb6f)
-
6fce0e20
by Jason Ekstrand
at 2018-01-24T20:14:47+00:00
i965: Track the depth and render caches separately
Previously, we just had one hash set for tracking depth and render
caches called brw_context::render_cache. This is less than ideal
because the depth and render caches are separate and we can't track
moves between the depth and the render caches. This limitation led
to some unnecessary flushing around the depth cache. There are cases
(mostly with BLORP) where we can end up touching a depth or stencil
buffer through the render cache. To guard against this, blorp would
unconditionally do a render_cache_set_check_flush on it's destination
which meant that if you did any rendering (including a BLORP operation)
to a given surface and then used it as a blorp destination, you would
end up flushing it out of the render cache before rendering into it.
Things get worse when you dig into the depth/stencil state code for
regular GL draw calls. Because we may end up rendering to a depth
or stencil buffer via BLORP, we did a render_cache_set_check_flush on
all depth and stencil buffers in brw_emit_depthbuffer to ensure that
they got flushed out of the render cache prior to using them for depth
or stencil testing. However, because we also need to track dirtiness
for depth and stencil so that we can implement depth and stencil
texturing correctly, we were adding all depth and stencil buffers to the
render cache set in brw_postdraw_set_buffers_need_resolve. This meant
that, if anything caused 3DSTATE_DEPTH_BUFFER to get re-emitted
(currently _NEW_BUFFERS, BRW_NEW_BATCH, and BRW_NEW_BLORP), we would
almost always do a full pipeline stall and render/depth cache flush.
The root cause of both of these problems is that we can't tell the
difference between the render and depth caches in our tracking. This
commit splits our cache tracking into two sets, one for render and one
for depth, and properly handles transitioning between the two. We still
flush all the caches whenever anything needs to be flushed. The idea is
that if we're going to take the hit of a flush and stall, we may as well
flush everything in the hopes that we can avoid a flush by something
else later.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit fb0e9b5197cb65bde1e116d89acd5deb32f9132c)
-
d6bfb9c3
by Jason Ekstrand
at 2018-01-24T20:15:03+00:00
i965: Track format and aux usage in the render cache
This lets us perform render cache flushes whenever a surface goes from
being used with one aux+format to a different aux+format.
This is the "proper" fix for https://bugs.freedesktop.org/102435.
ee57b15ec764736e2d5360beaef9fb2045ed0f68 which was really just a partial
revert of 3e57e9494c2279580ad6a83ab8c065d01e7e634e was just a hack to
get rid of a hang in a bunch of Valve games. This solves the actual
problem responsible for the hang and lets us enable CCS_E once again.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d84275b884244a2fd3a6e67ceb2a5277e5edf89a)
-
0b31126b
by Jason Ekstrand
at 2018-01-24T20:18:47+00:00
Re-enable regular fast-clears (CCS_D) on gen9+
This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68, "i965:
Disable regular fast-clears (CCS_D) on gen9+". How taht we've fixed the
issue with too many different aux usages in the render cache, it should
be safe to re-enable CCS_D for sRGB.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104163
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f79bb2e651f329364dfb3db0aac4b72f91f130cc)
[Emil Velikov: resolve trivial conflicts - gen10 is missing in branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_meta_util.c
-
48db8ed8
by Jason Ekstrand
at 2018-01-24T20:20:15+00:00
i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage
This commit unifies the CCS_E and CCS_D cases. This should fix a couple
of subtle issues. One is that when you use INTEL_DEBUG=norbc to disable
CCS_E, we don't get the sRGB blending workaround. By unifying the code,
we give CCS_D that workaround as well.
The second issue fixed by this refactor is that the blending workaround
was appears to be enabled on all gens but really only applies on gen9.
Due to a happy accident in the way code was laid out, it was only
getting enabled on gen9: gen8 and earlier don't support non-zero-one
clear colors, and gen10 supports sRGB for CCS_E so it got caught in the
format_ccs_e_compat_with_miptree case. This refactor moves it above the
format_ccs_e_compat_with_miptree case so it's an explicit early exit and
makes it explicitly only on gen9.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 361e1df1edb23b08e36027136f1dc73f52dea536)
-
14ebd7ec
by Dave Airlie
at 2018-01-24T20:20:26+00:00
r600/sb: fix a bug emitting ar load from a constant.
Some tess shaders were doing MOVA_INT _, c0.x on cayman, and then
hitting an assert in sb_bc_finalize.cpp:translate_kcache.
This makes sure the toplevel kcache tracker gets updated,
and the clause gets fixed up.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 68b976bd91d1a23d2d04f383ab194980b5084970)
-
3cd9d65a
by Kenneth Graunke
at 2018-01-24T20:20:27+00:00
i965: Bind null render targets for shadow sampling + color.
Portal 2 appears to bind RGBA8888_UNORM textures to a sampler2DShadow,
and calls shadow2D() on it. This causes undefined behavior in OpenGL.
Unfortunately, our sampler appears to hang in this scenario, which is
not acceptable. Just give them a null surface instead, which returns
all zeroes.
Fixes GPU hangs in Portal 2 on Kabylake.
Huge thanks to Jason Ekstrand for noticing this crazy behavior while
sifting through crash dumps.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104487
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 3e18c53e59457f585de217208e1745f2683be0b9)
-
212a59e2
by Grazvydas Ignotas
at 2018-01-24T20:20:27+00:00
st/vdpau: release held lock in error path
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit e6abc613e2a78c01d1e79e4cd3be79e58d52eac2)
-
cf807eff
by Lucas Stach
at 2018-01-24T20:20:27+00:00
etnaviv: dirty TS state when framebuffer has changed
When switching between framebuffers with and without TS, the TS state
needs to be flushed to the command stream even if the derived state
isn't changed.
Fixes: 4ee7c2c2843c ("etnaviv: enable TS, but disable autodisable")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit 29a0ea699a4fcd837d0478ad23b50e3cb0431ee4)
-
acca16e3
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Fix ordering issue in meta memory allocation failure path.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit d956e0bdf53a9dd51d4a07d3cb58ee16e37a4ace)
-
87d254b8
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Fix memory allocation failure path in compute resolve init.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 71f0315a8861ac20cd9ed36d89eb9db60462931f)
-
f1c8bc6e
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Fix freeing meta state if the device pipeline cache fails to allocate.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit c685076ab0706309d7ba2012a7bc4e2c6637d402)
-
1663b7ed
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Fix fragment resolve init memory allocation failure paths.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 2c802ca66c480a1038e1fe52350e30a27658e78a)
-
43d8d133
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Fix bufimage failure deallocation.
The inidividual init parts don't clean up their own stuff on failure.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit fb0992e967e7f56604e1f5db8579ae6c2b8d0f2a)
-
635b9549
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Init variant entry with memset.
This gets memcpy'd and written driectly, and due to alignment, this
resulted in uninitialized gaps. This makes those gaps go away.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8b98929074f77156d8e1a10bc42b8eda0f9ce4ec)
-
17647d08
by Bas Nieuwenhuizen
at 2018-01-24T20:20:27+00:00
radv: Don't allow 3d or 1d depth/stencil textures.
addrlib asserts when that happens, and supporting it is not
required so lets not allow this for now.
It also assert on fmask, but we don't have the number of samples here.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4584c4ef049ac604ebbeab56992d569e4d1f8a46)
-
be2a7b6a
by Jason Ekstrand
at 2018-01-24T20:20:27+00:00
i965/miptree: Add an explicit tiling parameter to create_for_bo
Otherwise, create_for_bo will just grab the tiling from the BO which is
not what we want when using modifiers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0465dd13d26451e2a57684d1ca6329dfbdeac9f4)
-
9b2ac06c
by Jason Ekstrand
at 2018-01-24T20:20:27+00:00
i965/miptree: Use the tiling from the modifier instead of the BO
This fixes a bug where we were taking the tiling from the BO regardless
of what the modifier said. When we got images in from Vulkan where it
doesn't set the tiling on the BO, we would treat them as linear even
though the modifier expressly said to treat it as Y-tiled.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit ad424b2243023b0299de700fb2d220c2f7849ce6)
-
8ebfa265
by Jason Ekstrand
at 2018-01-24T20:33:00+00:00
i965/bufmgr: Add a create_from_prime_tiled function
This new function is an import and a set tiling in one go.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit b9e7b29705cb17ef7f88d346db823c9b99810249)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_bufmgr.c
-
623d8436
by Jason Ekstrand
at 2018-01-24T20:33:57+00:00
i965: Set tiling on BOs imported with modifiers
We need this to ensure that GTT maps work on buffers we get from Vulkan
on the off chance that someone does a readpixels or something. Soon, we
will be removing GTT maps from i965 entirely and this can be reverted.
None the less, it's needed for stable.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 50485723523d2948a44570ba110f02f726f86a54)
-
93ffa566
by Matthew Nicholls
at 2018-01-24T20:33:57+00:00
radv: restore previous stencil reference after depth-stencil clear
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alex Smith <asmith@feralinteractive.com>
(cherry picked from commit 005375717b18b2eb04bdc54a260b096cabab15d2)
-
473d665a
by Jose Fonseca
at 2018-01-24T21:06:26+00:00
svga: Prevent use after free.
Courtesy of clang static analyzer.
I was hunting for potential sources of memory corruption using Mesa with
a GL trace, and happened to find this (unrelated) issue.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit dcbb224c688bfdacb76107a9816647f64088e67e)
-
ad764e36
by Bas Nieuwenhuizen
at 2018-01-25T02:09:22+00:00
ac/nir: Use instance_rate_inputs per attribute, not per variable.
This did the wrong thing if we had e.g. an array for which only some
of the attributes use the instance index. Tripped up some new CTS
tests.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 5a4dc285002e1924dbc8c72d17481a3dbc4c0142)
Conflicts:
src/amd/common/ac_nir_to_llvm.c
-
ff063689
by Samuel Thibault
at 2018-01-25T02:13:07+00:00
glx: fix non-dri build
glXGetDriverConfig parameters do not provide a context to dynamically
check for the presence of the function, so the dispatcher directly calls
glXGetDriverConfig, but in non-dri builds dri_glx.c didn't provide
glXGetDriverConfig.
This change make it just return NULL in that case.
Fixes: 84f764a7591 "glxglvnddispatch: Add missing dispatch for GetDriverConfig
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 47ac11bcf8bd9e4525e0fb4308d0bca87a8900c6)
-
78e11656
by Timothy Arceri
at 2018-01-25T02:13:19+00:00
ac: fix buffer overflow bug in 64bit SSBO loads
Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit e2b9296146746635cd631c5212ae56f0cd270820)
-
a060dc27
by Dave Airlie
at 2018-01-25T02:24:37+00:00
ac/nir: account for view index in the user sgpr allocation.
The view index user sgpr wasn't being accounted for properly,
this refactors out the code to decide if it's required and then
uses that info to account for it.
Fixes: 180c1b924e (ac/nir: Add shader support for multiviews.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3153d742078d9842d867e8affddf0b157de762f0)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
-
a45a6ed8
by Timothy Arceri
at 2018-01-25T02:26:18+00:00
ac: fix visit_ssa_undef() for doubles
V2: use LLVMIntTypeInContext()
Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 3bccb5dba9415f98f7a3dbb7c43a5eace64b4ec6)
-
022cdd4e
by Bas Nieuwenhuizen
at 2018-01-25T02:26:30+00:00
ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit f4211e6f9314b225cdcdc799e0c123b3dceee9eb)
-
4a79113e
by Bas Nieuwenhuizen
at 2018-01-25T02:30:50+00:00
ac/nir: Fix vector extraction if source vector has >4 elements.
v2: Add forgotten argument and start offset.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 32170d87e3b7bee37234b44ff787ff60fcd3a9aa)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
-
558411c2
by Eric Engestrom
at 2018-01-25T02:46:25+00:00
radeon: remove left over dead code
Fixes: 4e0d99a63588c67a955f "r100: Use shared debug code"
Cc: Pauli Nieminen <suokkos@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit eee8dd7c3360ec0daf3d44168b6d1c32c52bf69b)
-
5e889ae2
by Samuel Pitoiset
at 2018-01-25T02:52:20+00:00
radv: create pipeline layout objects for all meta operations
They are dummy objects but the spec requires layout to not be
NULL, this just makes sure we are creating valid pipeline layout
objects. This will allow us to remove some useless checks.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 3595a116489d6f3b2f7fd2aa3eeff6376b82beb2)
-
1bd25a4d
by Dave Airlie
at 2018-01-25T02:52:34+00:00
radv: add fs_key meta format support to resolve passes.
Some of the hw resolve passes need the SPI color format setup
correctly.
This fixes lots of 16-bit and 32-bit format tests in
dEQP-VK.renderpass.suballocation.multisample*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 316d762186f0bfc225b82794fdae520275a448db)
-
c30a6252
by Dave Airlie
at 2018-01-25T02:55:57+00:00
radv: don't use hw resolve for integer image formats
>From reading AMDVLK it currently never uses hw resolve paths.
This patch takes from radeonsi which doesn't use hw resolve
for integer formats, and does the same for radv.
This fixes:
dEQP-VK.renderpass.suballocation.multisample*uint tests.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 2a04f5481d (radv/meta: select resolve paths)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4df414bbd2f1a44840c982198f4c8353f242ca15)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/vulkan/radv_meta_resolve.c
-
eaa3da41
by Dave Airlie
at 2018-01-25T02:57:56+00:00
radv: don't use hw resolves for r16g16 norm formats.
radeonsi has a workaround for this, but it uses a R16A16 format,
which vulkan doesn't have, we could probably come up with a work
around but for now just avoid hw resolves.
Fixes:
dEQP-VK.renderpass.suballocation.multisample.r16g16_*norm*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 2a04f5481d (radv/meta: select resolve paths)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit c727ea9370adc5362e00208b9f1481764b8ef215)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/vulkan/radv_meta_resolve.c
-
d20d97ec
by Emil Velikov
at 2018-01-25T05:08:57+00:00
cherry-ignore: i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext
stable: The commit addresses earlier commit 6d87500fe12 which did not
land in branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
b31e232b
by Emil Velikov
at 2018-01-25T05:09:01+00:00
cherry-ignore: swr: refactor swr_create_screen to allow for proper cleanup on error
stable: The commit depends on earlier commit a4be2bcee2 which did not
land in branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
c465067f
by Emil Velikov
at 2018-01-25T05:09:02+00:00
cherry-ignore: anv: add explicit 18.0 only nominations
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
1bfeb763
by Emil Velikov
at 2018-02-09T03:50:08+00:00
cherry-ignore: radv: fix sample_mask_in loading. (v3.1)
fixes: The commit requires earlier commit 49d035122ee which did not land
in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
339b43b0
by Indrajit Das
at 2018-02-09T03:50:09+00:00
st/omx_bellagio: Update default intra matrix per MPEG2 spec
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit e05d5b0cf31f3212ba1666a6baaae77bc30433a0)
-
08ad68ea
by Indrajit Das
at 2018-02-09T03:50:09+00:00
radeon/uvd: update quantiser matrices only when requested
Only upload them when the pointers are valid.
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 38dee62c9a0ced17fb1f25256f9da3b163a16f81)
-
e46597f2
by Indrajit Das
at 2018-02-09T03:50:09+00:00
radeon/vcn: update quantiser matrices only when requested
Only update them when the pointers are valid.
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit f5277e84925b69b0bf01340122684becd45c1f7d)
-
30a35f8d
by Indrajit Das
at 2018-02-09T03:50:09+00:00
st/va: clear pointers for mpeg2 quantiser matrices
This is to fix VA-API issues with GStreamer and MPEG2.
Since gstreamer does not pass quantiser matrices with each frame, invalid
pointers were being passed to the driver. This patch addresses the same.
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 338638a8afc9f330bacc1cdd7e6392a3ea9d828a)
-
2b6d2f6a
by Boyuan Zhang
at 2018-02-09T03:50:10+00:00
radeon/vcn: add and manage render picture list
Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.
During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.
As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit f2bfd1cbb7e72945ca192845a1ad28426c7aea89)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104745
-
36e1b57b
by Boyuan Zhang
at 2018-02-09T03:50:10+00:00
radeon/uvd: add and manage render picture list
Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.
During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.
As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 2ec48039b8aa1f6a5e16f3f12483b88981d0f5d3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104745
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/radeon/radeon_uvd.c
-
1d7d13ff
by Marek Olšák
at 2018-02-09T03:50:10+00:00
radeonsi: don't ignore pitch for imported textures
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 022c5b22fee5d92da67f48601ea80b1c810a829d)
[Emil Velikov: attribute for lack of slice_size_dw]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Conflicts:
src/gallium/drivers/radeon/r600_texture.c
-
0dd5120d
by Jason Ekstrand
at 2018-02-09T03:50:10+00:00
i965/miptree: Take an aux_usage in prepare/finish_render
Both callers of intel_miptree_prepare/finish_render have to call
intel_miptree_render_aux_usage anyway for other reasons. They may as
well pass the result in instead of us calling it again.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit dfe02179055b2504303e23988ab3d446b40de05a)
-
468a2b65
by Jason Ekstrand
at 2018-02-09T03:50:10+00:00
i965/miptree: Add an aux_disabled parameter to render_aux_usage
Only one of the callers of intel_miptree_render_aux_usage actually took
brw->draw_aux_buffer_disabled into account. This was causing us to
ignore draw_aux_buffer_disabled for the intel_miptree_prepare_render.
This isn't a problem because the draw_aux_buffer_disabled entry was set
during texture preparation and we already did the resolve at that time.
However, this also meant that the aux_usage we were passing to
brw_cache_flush_for_render and brw_render_cache_add_bo was wrong so our
automatic cache flushing around aux_usage changes wasn't happening.
This was causing GPU hangs in Oxenfree.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104711
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104411
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104383
Fixes: ea0d2e98ecb369ab84e78c84709c0930ea8c293a
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d38ec24f531fac0b53c406a09d17427309a3ffca)
-
4987b561
by Jason Ekstrand
at 2018-02-09T03:50:10+00:00
i965/surface_state: Drop brw_aux_surface_disabled
The only purpose of this function is to disable aux on texture surfaces
when the corresponding renderbuffer has aux disabled. However, the act
of disabling aux on the renderbuffer will cause it to be resolved and
intel_miptree_texture_aux_usage will already check the resolved status
of a texture and return ISL_AUX_USAGE_NONE for it. Even if we used CCS
for it, that wouldn't really be a problem because the CCS will be in the
pass-through state and so it would effectively be ignored.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 468ea3cc451f2c71e7d1be528090cb0334d500c2)
-
5ef3cadf
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: meson: multiple fixes
stable: The commits address the Meson build that is explicitly disabled
in branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
a78ff020
by Dave Airlie
at 2018-02-09T03:50:10+00:00
radv: move spi_baryc_cntl to pipeline
We need to enable the pos float location 2 mode anytime we have
persample not just when forced by the frag shader.
This fixes:
dEQP-VK.pipeline.multisample.min_sample_shading*
Fixes: 58c97a079 (radv: enable location at sample when persample is forced.)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 298554541da220ebdcd9aa9b9055ede2481d5817)
-
f23257b6
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: swr/rast: support llvm 3.9 type declarations
stable: The commit requires earlier commit 01ab218bbc which did not land
in branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
557f2cd4
by Chuck Atkins
at 2018-02-09T03:50:10+00:00
configure.ac: add missing llvm dependencies to .pc files
v2: Only add as dependencies for gallium-osmesa and gallium-xlib
CC: <mesa-stable@lists.freedesktop.org>
Signed-of-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 6ac5e851f1a0b83d84156bc79983fd9527d4c296)
-
a0943143
by Emil Velikov
at 2018-02-09T03:50:10+00:00
Revert "cherry-ignore: intel/fs: Use the original destination region for int MUL lowering"
This reverts commit 7295b97d61104e971aa925c2370e3f3cbb23a408.
Originally the nomination was causing a regression. With that addressed,
we can pick it up alongside it's fix.
-
0bc9182f
by Jason Ekstrand
at 2018-02-09T03:50:10+00:00
intel/fs: Use the original destination region for int MUL lowering
Some hardware (CHV, BXT) have special restrictions on register regions
when doing integer multiplication. We want to respect those when we
lower to DxW multiplication.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 18fde36ced4279f2577097a1a7d31b55f2f5f141)
Squashed with:
i965/fs: Reset the register file to VGRF in lower_integer_multiplication
18fde36ced4279f2577097a1a7d31b55f2f5f141 changed the way temporary
registers were allocated in lower_integer_multiplication so that we
allocate regs_written(inst) space and keep the stride of the original
destination register. This was to ensure that any MUL which originally
followed the CHV/BXT integer multiply regioning restrictions would
continue to follow those restrictions even after lowering. This works
fine except that I forgot to reset the register file to VGRF so, even
though they were assigned a number from alloc.allocate(), they had the
wrong register file. This caused some GLES 3.0 CTS tests to start
failing on Sandy Bridge due to attempted reads from the MRF:
ES3-CTS.functional.shaders.precision.int.highp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.int.mediump_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.int.lowp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.highp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.mediump_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.lowp_mul_fragment.snbm64
This commit remedies this problem by, instead of copying inst->dst and
overwriting nr, just make a new register and set the region to match
inst->dst.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103626
Fixes: 18fde36ced4279f2577097a1a7d31b55f2f5f141
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit db682b8f0eafd3b9d58e736e9e2f520943a89942)
-
ae5e793f
by Jason Ekstrand
at 2018-02-09T03:50:10+00:00
anv/pipeline: Don't look at blend state unless we have an attachment
Without this, we may end up dereferencing blend before we check for
binding->index != UINT32_MAX. However, Vulkan allows the blend state to
be NULL so long as you don't have any color attachments. This fixes a
segfault when running The Talos Principal.
Fixes: 12f4e00b69e724a23504b7bd3958fb75dc462950
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit c8949e24984266cca3593291c30ea199baef5358)
-
7e7b4c2c
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: ac/nir: set amdgpu.uniform and invariant.load for UBOs
stable: The commit requires earlier commit w41c36c45 which did not land
in branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
62e0a889
by Eleni Maria Stea
at 2018-02-09T03:50:10+00:00
mesa: Fix function pointers initialization in status tracker
We assigned the function that gets the device uuid to the GetDriverUuid
function pointer and the function that gets the driver uuid to the
GetDeviceUuid function pointer inside the state tracker. Exchanged the
pointers.
cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 8096b558a7d769b20b1545b83399d67b8a3df94a)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collaboral.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Conflicts:
src/mesa/state_tracker/st_context.c
-
eaa9449c
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: add gen10 fixes
Initial gen10 support landed in the 18.0 series.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
e1ab1de6
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: add r600/amdgpu 18.0 nominations
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
56427ff0
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: add i965 shader cache fixes
The feature is available in the 18.0 branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
9161ac5c
by Emil Velikov
at 2018-02-09T03:50:10+00:00
cherry-ignore: nir: mark unused space in packed_tex_data
stable: The commit covers nir serialise, which did not land in branch
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
b75f12a2
by Dave Airlie
at 2018-02-09T03:50:10+00:00
r600/sb: insert the else clause when we might depart from a loop
If there is a break inside the else clause and this means we
are breaking from a loop, the loop finalise will want to insert
the LOOP_BREAK/CONTINUE instruction, however if we don't emit
the else there is no where for these to end up, so they will end
up in the wrong place.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101442
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8d633f067b8a3d74e3f39faea0773a229d4b93b3)
-
6a7e3a15
by Jason Ekstrand
at 2018-02-09T03:50:11+00:00
anv/cmd_buffer: Re-emit the pipeline at every subpass
If we ever hit this edge-case, it can theoretically cause problem for
CNL because we could end up changing render targets without re-emitting
3DSTATE_MULTISAMPLE which is part of the pipeline. Just get rid of the
edge case.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 97938dac36e2875001ba24a7968e4cd8e2271321)
-
ac087eb4
by Lucas Stach
at 2018-02-09T03:50:11+00:00
renderonly: fix dumb BO allocation for non 32bpp formats
Take into account the resource format, instead of applying a hardcoded
32bpp. This not only over-allocates 16bpp formats, but also results in
a wrong stride being filled into the handle.
Fixes: 848b49b288f ("gallium: add renderonly library")
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 0c71a19fe4368beaaf7ac676403b3079ad658890)
-
87ffdbae
by Jason Ekstrand
at 2018-02-09T04:20:27+00:00
anv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/intel/vulkan/anv_device.c
-
2b9e16d1
by Emil Velikov
at 2018-02-09T04:21:24+00:00
radv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
[Emil Velikov: port from equivalent ANV commit]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
0d3a990c
by Emil Velikov
at 2018-02-09T04:22:17+00:00
cherry-ignore: radv: Don't expose VK_KHX_multiview on android.
stable: The KHX extension is disabled all together in the stable
branches.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
caad5571
by Jason Ekstrand
at 2018-02-09T04:22:54+00:00
i965: Call prepare_external after implicit window-system MSAA resolves
This fixes some rendering corruption in a couple of Android apps that
use window-system MSAA.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104741
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 2f7205be47bbb730cdfa0a037224b9ebd5224fd1)
-
47542b1f
by Emil Velikov
at 2018-02-09T04:22:54+00:00
configure.ac: correct driglx-direct help text
The default was toggled a while back, but the text wasn't updated.
Fixes: bd526ec9e1b ("configure: Always default to
--enable-driglx-direct")
Cc: Jon TURNEY <jon.turney@dronecode.org.uk>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 6aeef5464497a2dfd2eb63c7e4aa3349c7794eae)
-
5ef9c58f
by Dave Airlie
at 2018-02-09T04:22:54+00:00
radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1)
This seems to be broken, at least the cts tests fail.
This fixes:
dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_4
dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_8
2 samples seems to pass fine, amdvlk doesn't appear to enable TC for
possibly some other reasons here.
This is most likely a hack.
v1.1: add a bit of explaination text. (Samuel)
Fixes: ad3d98da9 (radv: enable tc compatible htile for d32s8 also.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit f4c534ef68a479055190f8ec8d551be0f56ef361)
-
d2258c55
by Maxin B. John
at 2018-02-09T04:22:54+00:00
anv_icd.py: improve reproducible builds
Sort the output to ensure build reproducibility
Signed-off-by: Maxin B. John <maxin.john@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Fixes: 0ab04ba979b ("anv: Use python to generate ICD json files")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 8116b9170bc36bb15512f97a7680ad97bddd56a8)
-
e27f0661
by Emil Velikov
at 2018-02-09T04:23:16+00:00
cherry-ignore: add meson fix
Meson is disabled in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
64ab6760
by Dave Airlie
at 2018-02-09T04:23:17+00:00
radv/gfx9: fix block compression texture views. (v2)
This ports a fix from amdvlk, to fix the sizing for mip levels
when block compressed images are viewed using uncompressed views.
My original fix didn't power the clamping, but it looks like
the clamping is required to stop the sizing going too large.
Fixes:
dEQP-VK.image.texel_view_compatible.graphic.extended*bc*
Doesn't crash DOW3 anymore.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit f6cc15dccd54ff70be987457af790cac1c8fe5bb)
-
da327c6c
by Dave Airlie
at 2018-02-09T04:23:17+00:00
virgl: also remove dimension on indirect.
This fixes some dEQP tests that generated bad shaders.
Fixes: b6f6ead19 (virgl: drop const dimensions on first block.)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 49c61d8b841538e09b8c2b2d2f409147fd7b549a)
-
69beac3f
by Matthew Nicholls
at 2018-02-09T04:23:17+00:00
radv: remove predication on cache flushes
This can lead to a situation where cache flushes could get conditionally
disabled while still clearing the flush_bits, and thus flushes due to
application pipeline barriers may never get executed.
Fixes: a6c2001ace (radv: add support for cmd predication.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ef272b161e05e8216f2d1f4df5023f3aed0ae4fa)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
-
790cc8ab
by Michel Dänzer
at 2018-02-09T04:23:17+00:00
winsys/radeon: Compute is_displayable in surf_drm_to_winsys
It was always 0, breaking (at least) DRI3 with Xwayland.
Bugzilla: https://bugs.freedesktop.org/104306
Fixes: 5f2073be3282 ("ac/surface: add ac_surface::is_displayable")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 1cf1bf32eff5ffca0b928c0884b0e792207b61b7)
-
833808f0
by Andres Gomez
at 2018-02-09T04:23:17+00:00
i965: perform 2 uploads with dual slot *64*PASSTHRU formats on gen<8
The emission of vertex attributes corresponding to dvec3 and dvec4
vertex shader input variables was not correct when the <size> passed
to the VertexAttribL* commands was <= 2.
In 61a8a55f557 ("i965/gen8: Fix vertex attrib upload for dvec3/4
shader inputs"), for gen8+ we needed to determine if the attrib was
dual slot to emit 128 or 256-bit, independently of the VAO size.
Similarly, for gen < 8 we also need to determine whether the attrib is
dual slot to force the emission of 256-bits through 2 uploads.
Additionally, we make use of the ISL_FORMAT_R32_FLOAT format in this
second upload to fill these unspecified components with zeros, as we
also do for gen8+.
Fixes the following test on Haswell:
KHR-GL46.vertex_attrib_binding.basic-inputL-case1
v2: Added more inline comments to explain why we are using
ISL_FORMAT_R32_FLOAT and its consequences, as requested by
Alejandro and Antía.
Fixes: 75968a668e4 ("i965/gen7: expose OpenGL 4.2 on Haswell when
supported")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103006
Cc: Alejandro Piñeiro <apinheiro@igalia.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: Antia Puentes <apuentes@igalia.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 5a7aba2e0a7fb3414a94d04d5970a2ed10c1f63e)
-
5f862311
by Kenneth Graunke
at 2018-02-09T04:23:17+00:00
i965: Bump official kernel requirement to Linux v3.9.
In commit 3f353342a6b6744773c26ed66b12afed42bd57af (present in 17.3.0)
we started unconditionally using I915_EXEC_NO_RELOC, which was
introduced in Linux v3.9. ChromeOS kernel 3.8 has backported this,
so it should work too.
Running on older kernels would likely result in every single batch
being rejected by the kernel, which is pretty catastrophic. Yet, it
appears that nobody noticed. So, let's just bump the official
requirement and move forward ever so slowly.
Fixes: 3f353342a6b ("i965: Use I915_EXEC_NO_RELOC")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit c3cd2aac279908a2de755d9454f293761d7b8d5a)
-
9f6e05d1
by Igor Gnatenko
at 2018-02-09T04:23:17+00:00
link mesautil with pthreads
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_setname':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:66: undefined reference to `pthread_setname_np'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_join':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:336: undefined reference to `pthread_join'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:48: undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:296: undefined reference to `pthread_create'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask'
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `call_once':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:96: undefined reference to `pthread_once'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_get_time_nano':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:84: undefined reference to `pthread_getcpuclockid'
collect2: error: ld returned 1 exit status
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Igor Gnatenko <ignatenko@redhat.com>
(cherry picked from commit 23ce168048698eeea3df6bb8c9de5be3ca4784cd)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104818
-
e55ca676
by Jon Turney
at 2018-02-09T04:23:17+00:00
configure: Default to gbm=no on osx
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 7ad7a07c88b1b1c697132e8f990c0d9530fdf827)
-
15beac3a
by Jon Turney
at 2018-02-09T04:23:18+00:00
glx/apple: include util/debug.h for env_var_as_boolean prototype
mesa/src/glx/glxcmds.c:1295:21: error: implicit declaration of function 'env_var_as_boolean' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
mesa/src/glx/apple/apple_visual.c:85:28: error: implicit declaration of function 'env_var_as_boolean' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b37b7b42dcc33d636c3db0558d032d7d95664c56)
-
70604e88
by Jon Turney
at 2018-02-09T04:23:18+00:00
glx/apple: locate dispatch table functions to wrap by name
Avoid reaching into the dispatch table internals (and thus having to deal
with the complexities of remap etc.) by identifying functions to wrap by
name.
See:
https://lists.freedesktop.org/archives/mesa-dev/2015-June/086721.html et seq.
https://bugs.freedesktop.org/show_bug.cgi?id=90311
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit d3540b405b975450b9c2f9d8eb273be062cbf73a)
-
1bf16e4f
by Roland Scheidegger
at 2018-02-09T04:23:18+00:00
r600: don't do stack workarounds for hemlock
By the looks of it it seems hemlock is treated separately to cypress, but
certainly it won't need the stack workarounds cedar/redwood (and
seemingly every other eg chip except cypress/juniper) need.
(Discovered by accident.)
Acked-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c2f0e0885776f3f0a18b9db08149564d4b98e5b7)
-
5d961e16
by Emil Velikov
at 2018-02-09T04:23:18+00:00
cherry-ignore: add a few more meson fixes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
5f2d38cc
by Emil Velikov
at 2018-02-15T11:02:49+00:00
Update version to 17.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
2f9820c5
by Emil Velikov
at 2018-02-15T11:09:05+00:00
docs: add release notes for 17.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
26c84b8a
by Emil Velikov
at 2018-02-15T11:28:00+00:00
docs: add sha256 checksums for 17.3.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
4be67bbe
by Andreas Boll
at 2018-02-16T11:04:59+01:00
Merge tag 'mesa-17.3.4' into debian-unstable
mesa-17.3.4
-
22a37ff2
by Andreas Boll
at 2018-02-16T11:05:22+01:00
Bump changelog
-
313d9c10
by Andreas Boll
at 2018-02-16T11:22:02+01:00
Close bug #888633
-
cccf23e8
by Andreas Boll
at 2018-02-16T11:56:49+01:00
Upload to unstable.
-
de93e457
by James Legg
at 2018-02-19T21:53:44+00:00
ac/nir: Fix conflict resolution typo in handle_vs_input_decl
Fixes ad764e365beb8a119369b97f22225cb95fc7ea8c:
"ac/nir: Use instance_rate_inputs per attribute, not per variable".
CC: <mesa-stable@lists.freedesktop.org>
CC: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
-
ea8ad9af
by Emil Velikov
at 2018-02-19T21:55:11+00:00
Update version to 17.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
2529d771
by Emil Velikov
at 2018-02-19T22:01:35+00:00
docs: add release notes for 17.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
164a9931
by Emil Velikov
at 2018-02-19T22:07:23+00:00
docs: add sha256 checksums for 17.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
7ced8b69
by Andreas Boll
at 2018-02-20T11:46:45+01:00
Merge tag 'mesa-17.3.5' into debian-unstable
mesa-17.3.5
-
eae57ab7
by Andreas Boll
at 2018-02-20T11:47:15+01:00
Bump changelog
-
32ad1a5a
by Andreas Boll
at 2018-02-20T12:16:47+01:00
Upload to unstable.
-
2475b3a5
by Kenneth Graunke
at 2018-02-26T23:59:14+00:00
i965: Don't disable CCS for RT dependencies when dispatching compute.
Compute shaders don't have access to the framebuffer, so there's no
point in worrying whether a texture is bound as a render target.
This saves a bunch of resolves in GFXBench4 Manhattan 3.1, but doesn't
seem to impact performance at all, at least on Apollolake.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 583ce96c9429e23c33daeb7025210ef73ae51688)
-
d654c58c
by Jason Ekstrand
at 2018-02-27T00:00:21+00:00
i965/draw: Do resolves properly for textures used by TXF
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 96aa5587155e7de87e80d617725cc66f6807c5d1)
-
dda6a26b
by Topi Pohjolainen
at 2018-02-27T00:01:24+00:00
i965: Don't try to disable render aux buffers for compute
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104546
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit ec4bb693a0175744465f272a8bcea2db043ba1bc)
-
b626f342
by Jason Ekstrand
at 2018-02-27T00:03:34+00:00
i965: Replace draw_aux_buffer_disabled with draw_aux_usage
Instead of keeping an array of booleans, we now hang onto an array of
isl_aux_usage enums. This means that the thing we are passing from
brw_draw.c to surface state setup is the thing that surface state setup
actually needs instead of an input to compute what it needs.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit e52a9f18d69c94b7cb7f81361cdb9e2582c3d742)
-
c0abad57
by Jason Ekstrand
at 2018-02-27T00:04:30+00:00
i965/draw: Set NEW_AUX_STATE when draw aux changes
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104411
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104383
Fixes: ea0d2e98ecb369ab84e78c84709c0930ea8c293a
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 20f70ae3858bc213e052a8434f0e637eb36203c4)
-
a399c7fa
by Jason Ekstrand
at 2018-02-27T00:09:25+00:00
i965: Stop disabling aux during texture preparation
Previously, we were handling self-dependencies by marking the render
buffer and then passing disable_aux=true to prepare_texture so that it
would do a resolve. This works but ends us up doing to much resolving
in some cases. Specifically, if we're doing something such as mipmap
generation, this would cause us to resolve all levels of the texture if
even one of them is overlapping.
Instead, this commit makes us wait until we process the framebuffer to
do these resolves and we only resolve the slices needed for rendering.
Doing this resolve puts them into the pass-through state so, even if we
do texture using CCS_E, the CCS data will effectively be ignored and the
real surface contents read.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit df13588d2176dcf4800a882d926f389667772b46)
-
c17516c3
by Emil Velikov
at 2018-02-27T00:13:31+00:00
Update version to 17.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
b3e5a3f3
by Emil Velikov
at 2018-02-27T00:18:33+00:00
docs: add release notes for 17.3.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
-
d825b166
by Andreas Boll
at 2018-02-27T09:11:25+01:00
Merge tag 'mesa-17.3.6' into debian-unstable
mesa-17.3.6
-
150607fe
by Andreas Boll
at 2018-02-27T09:11:45+01:00
Bump changelog
-
ab159b3d
by Andreas Boll
at 2018-02-27T09:17:15+01:00
Close bug #890866
-
7e0eb411
by Andreas Boll
at 2018-02-27T09:42:18+01:00
Upload to unstable.
-
5b8018f9
by Jérémy Viès
at 2018-03-02T10:51:02+02:00
Backport to stretch.
-
e177911d
by Andreas Boll
at 2018-03-02T10:51:02+02:00
Bump vulkan dependency to use vulkan from backports.
-
6366cad1
by Timo Aaltonen
at 2018-03-02T11:24:44+02:00
update changelog, release to stretch-backports