-
69ef6e4a
by Juan A. Suarez Romero
at 2018-05-17T18:40:11+00:00
docs: add sha256 checksums for 18.0.4
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
0f7b29aa
by Samuel Pitoiset
at 2018-05-22T13:03:34+02:00
spirv: fix visiting inner loops with same break/continue block
We should stop walking through the CFG when the inner loop's
break block ends up as the same block as the outer loop's
continue block because we are already going to visit it.
This fixes the following assertion which ends up by crashing
in RADV or ANV:
SPIR-V parsing FAILED:
In file ../src/compiler/spirv/vtn_cfg.c:381
block->node.link.next == NULL
0 bytes into the SPIR-V binary
This also fixes a crash with a camera shader from SteamVR.
v2: make use of vtn_get_branch_type() and add an assertion
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 6bde8c560877512852ff49fafa296eb71a5ec14b)
-
712456cb
by Jan Vesely
at 2018-05-22T13:03:34+02:00
eg/compute: Use reference counting to handle compute memory pool.
Use pipe_reference to release old RAT surfaces.
RAT surface adds a reference to pool bo, so use reference counting for pool->bo
as well.
v2: Use the same pattern for both defrag paths
Drop confusing comment
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit f3521ce2c440bd50020a3ff81e6d9fa17c01009c)
-
f084db88
by Stuart Young
at 2018-05-22T13:03:34+02:00
etnaviv: Fix missing rnndb file in tarballs
Seems that when the rnndb files for etniviv were updated/included back
in Nov 2017, hw/texdesc_3d.xml.h was missed from Makefile.sources and
meson.build. This was all during the conversion to meson, so it apears
to have slipped through the cracks. As such, this file has been missing
from the official tarballs since inclusion in Mesa, so the git trees
and tarballs differ.
Found due to lintian errors in the Debian packages.
Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit f806cc9eb6be1a84a9987b142e7fce1ec2cb7973)
-
544a3838
by Juan A. Suarez Romero
at 2018-05-22T13:03:34+02:00
cherry-ignore: i965/miptree: Fix handling of uninitialized MCS buffers
stable: The commit requires earlier commit af4e9295fe which did not land
in branch.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
3b7134c5
by Nanley Chery
at 2018-05-22T13:03:34+02:00
i965/miptree: Zero-initialize CCS_D buffers
Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base slice. Here's a specific example:
1) Fast clear level 0
* Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
* Level 0 transitions to the CLEAR state.
2) Render to level 1
* Level 1 may have a 2-bit pattern of 2's.
* Rendering with a 2 in the CCS is undefined.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 8a9491058da72ee2df75da25bb147010a451fb68)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
-
6ce8a775
by Bas Nieuwenhuizen
at 2018-05-22T13:03:34+02:00
amd/addrlib: Use defines in autotools build.
Otherwise stuff like NDEBUG would not be passed through.
CC: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106479
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 62e0e089d710835d9f79138377bcc37147f75ebd)
-
e7b50640
by Juan A. Suarez Romero
at 2018-05-22T13:03:34+02:00
cherry-ignore: add explicit 18.1 only nominations
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
5cef37e9
by Bas Nieuwenhuizen
at 2018-05-22T13:03:34+02:00
radv: Fix SRGB compute copies.
SRGB stores are broken. We had compensation code in the
resolve path but none in the copy path. Since we don't
want any conversion and it does not matter for DCC,
just make everything UNORM instead.
This happened to cause wrong colors for the PRIME path, as
that uses image->buffer copies which always use the compute
path.
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106587
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit a63a0960e3ebf049e593f51ce1e02dc84254f9c4)
-
5443d858
by Juan A. Suarez Romero
at 2018-05-22T13:03:34+02:00
cherry-ignore: mesa/st: handle vert_attrib_mask in nir case too
fixes: The commit fixes earlier commits 19a91841c3 and 9987a072cb which
did not land in branch.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
620be4d4
by Timothy Arceri
at 2018-05-22T13:03:34+02:00
mesa: add glUniform*ui{v} support to display lists
Fixes: a017c7ecb7ae "mesa: display list support for uint uniforms"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78097
(cherry picked from commit f71714022b2cd26bb1892e6a7f3d7308515f210e)
-
f844591e
by Anuj Phogat
at 2018-05-22T13:03:34+02:00
i965/glk: Add l3 banks count for 2x6 configuration
2x6 configuration with pci-id 0x3185 has same number of
banks (2) as 3x6 configuration (pci-id 0x3184).
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+"
Cc: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 0748383a6014886ef0bf7bda16fd0efef39c405d)
-
96b1ac39
by Samuel Pitoiset
at 2018-05-22T13:03:34+02:00
radv: fix centroid interpolation
It's legal to set the centroid and sample interpolation modes
when MSAA disabled. So, we have to initialize the centroid
inputs because the hardware doesn't.
This fixes rendering issues with DXVK and The Witness, World of
Warcraft, Trackmania and probably more games.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 73df16dcee79e2281c8d8a830dbbe6655359c82d)
[Juan A. Suarez: apply change in src/amd/common/ac_nir_to_llvm.c]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Conflicts:
src/amd/vulkan/radv_nir_to_llvm.c
-
b582b8fc
by Michel Dänzer
at 2018-05-23T16:28:02+02:00
dri3: Stricter SBC wraparound handling
Prevents corrupting the upper 32 bits of draw->recv_sbc when
draw->send_sbc resets to 0 (which currently happens when the window is
unbound from a context and bound to one again), which in turn caused
loader_dri3_swap_buffers_msc to calculate target_msc with corrupted
upper 32 bits. This resulted in hangs with the Xorg modesetting driver
as of xserver 1.20 (older versions and other drivers ignored the upper
32 bits of the target MSC, which is why this wasn't noticed earlier).
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/106351
Tested-by: Mike Lothian <mike@fireburn.co.uk>
(cherry picked from commit fe2edb25dd5628c395a65b60998f11e839d2b458)
[Juan A. Suarez: resolve trivial conflicts]
Conflicts:
src/loader/loader_dri3_helper.c
-
6a0c2860
by Dave Airlie
at 2018-05-23T16:28:02+02:00
tgsi/scan: add hw atomic to the list of memory accessing files
This fixes 4 out of 5 cases in:
arb_framebuffer_no_attachments-atomic on cayman.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f2f464de576187891eeadb3e7fadf9ddbf322cba)
-
a93a86a4
by Jason Ekstrand
at 2018-05-23T16:28:02+02:00
intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
(cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502)
-
8d5f09e8
by Francisco Jerez
at 2018-05-24T10:35:26+00:00
Revert "mesa: simplify _mesa_is_image_unit_valid for buffers"
This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145. It was
preventing the image format validation from being done on buffer
textures, which is required to ensure that the application doesn't
attempt to bind a buffer texture with an internal format incompatible
with the image unit format (e.g. of different texel size), which is
not allowed by the spec (it's not allowed for *any* texture target,
whether or not there is spec wording restricting this behavior
specifically for buffer textures) and will cause the driver to
calculate texel bounds incorrectly and potentially crash instead of
the expected behavior.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106465
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit 5a6814780322988a7adee525899bca8a83907ab7)
-
03eaee15
by Francisco Jerez
at 2018-05-24T10:35:26+00:00
i965: Move buffer texture size calculation into a common helper function.
The buffer texture size calculations (should be easy enough, right?)
are repeated in three different places, each of them subtly broken in
a different way. E.g. the image load/store path was never fixed to
clamp to MaxTextureBufferSize, and none of them are taking into
account the buffer offset correctly. It's easier to fix it all in one
place.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106481
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit 156d2c6e621d836c4d45c636b87669e1de3d4464)
-
86e749a9
by Francisco Jerez
at 2018-05-24T10:35:26+00:00
i965: Handle non-zero texture buffer offsets in buffer object range calculation.
Otherwise the specified surface state will allow the GPU to access
memory up to BufferOffset bytes past the end of the buffer. Found by
inspection.
v2: Protect against out-of-range BufferOffset (Nanley).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit e989acb03ba802737f762627dd16ac1d0b9f0d13)
-
42fa7cf2
by Francisco Jerez
at 2018-05-24T10:35:26+00:00
i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.
Instead of directly using intel_obj->buffer. Among other things
intel_bufferobj_buffer() will update intel_buffer_object::
gpu_active_start/end, which are used by glBufferSubData() to decide
which path to take. Fixes a failure in the Piglit
ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests,
which could be reproduced with a non-standard glGetTexSubImage
implementation (see bug report).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351
Reported-by: Nanley Chery <nanleychery@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit 936cd3c87a212c28fe89a5c059fc4febd8b52ab7)
-
1939affe
by Jose Dapena Paz
at 2018-05-25T09:59:18+02:00
mesa: do not leak ctx->Shader.ReferencedProgram references
When glUseProgram is used, references to the included shaders are
added in ctx->Shader.ReferencedProgram. But those references are not
decreased when the shader data is deallocated. Thus, those shaders
are leaked.
Explicitely remove the pending references to these shaders.
Fixes: e6506b3cd23 ("mesa: retain gl_shader_programs after glDeleteProgram if they are in use")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 6c61c31dc2fe52ad8a56ebe0b3aa10c223b635ba)
-
8cf02769
by Marek Olšák
at 2018-05-28T10:39:48+02:00
st/mesa: simplify lastLevel determination in st_finalize_texture
This fixes shader images where we always bind stObj->pt and not individual
gl_texture_images.
Roughly based on i965 commit 845ad2667ab2466752f06ea30bdb9c837116c308
which does a similar thing but for a different reason.
This fixes GL CTS assertion failures introduced by Ilia.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit a4ba7cd6a2fc2718c3b4f9107d676ad1bfd02bf1)
-
38aeeee5
by Marek Olšák
at 2018-05-28T10:39:48+02:00
radeonsi: fix incorrect parentheses around VS-PS varying elimination
I don't know if it caused issues.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 92ea9329e5eacf9a44ed30b3d72038a411eb771a)
-
aac580f7
by Jason Ekstrand
at 2018-05-28T10:39:48+02:00
intel/blorp: Support blits and clears on surfaces with offsets
For certain EGLImage cases, we represent a single slice or LOD of an
image with a byte offset to a tile and X/Y intratile offsets to the
given slice. Most of i965 is fine with this but it breaks blorp. This
is a terrible way to represent slices of a surface in EGL and we should
stop some day but that's a very scary and thorny path. This gets blorp
to start working with those surfaces and fixes some dEQP EGL test bugs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit ae514ca695a599cdd0b7c22f48fd4d721671b0cb)
-
714dabe3
by Juan A. Suarez Romero
at 2018-05-30T10:06:43+02:00
cherry-ignore: Tegra is not supported
stable: Tegra support was not added in the current branch.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
81bd117b
by Marek Olšák
at 2018-05-30T10:06:43+02:00
mesa: handle GL_UNSIGNED_INT64_ARB properly (v2)
Bindless texture handles can be passed via vertex attribs using this type.
This fixes a bunch of bindless piglit tests on radeonsi.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit a8e141387686cdf44b5868031283267acb99eba7)
[Juan A. Suarez: resolve trivial conflict]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Conflicts:
src/mesa/vbo/vbo_private.h
-
dfa3a7ee
by Juan A. Suarez Romero
at 2018-05-30T10:06:43+02:00
cherry-ignore: st/mesa: fix assertion failures with GL_UNSIGNED_INT64_ARB (v2)
stable: The commit requires earlier commit 19a91841c3 which did not land in branch.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
7c644f48
by Juan A. Suarez Romero
at 2018-05-30T10:06:43+02:00
cherry-ignore: nv30: ensure that displayable formats are marked accordingly
stable: Explicit 18.1 only nomination.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
3f4da760
by Juan A. Suarez Romero
at 2018-06-03T09:20:57+00:00
Update version to 18.0.5
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
ca0037aa
by Juan A. Suarez Romero
at 2018-06-03T09:26:20+00:00
docs: add release notes for 18.0.5
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
-
a52e5b98
by Emilio Pozuelo Monfort
at 2018-06-03T19:25:40+02:00
Merge branch 'upstream-unstable' into debian-unstable
-
8f6feea4
by Emilio Pozuelo Monfort
at 2018-06-03T19:31:15+02:00
New upstream release