mesa: Changes to 'upstream-experimental'
VERSION | 2
include/GLES/gl.h | 15 ++++-
include/GLES/glext.h | 3 -
src/amd/common/ac_llvm_build.c | 57 ++++++++++++++------
src/amd/common/ac_llvm_build.h | 1
src/amd/common/ac_nir_to_llvm.c | 38 ++++++++-----
src/amd/common/ac_nir_to_llvm.h | 1
src/amd/vulkan/radv_device.c | 6 +-
src/amd/vulkan/radv_meta_blit.c | 2
src/amd/vulkan/radv_meta_blit2d.c | 2
src/amd/vulkan/radv_meta_clear.c | 2
src/amd/vulkan/radv_meta_resolve_fs.c | 2
src/amd/vulkan/radv_pipeline.c | 37 +++++++++---
src/amd/vulkan/radv_private.h | 2
src/compiler/nir/nir_opt_algebraic.py | 4 -
src/compiler/spirv/spirv_to_nir.c | 2
src/gallium/drivers/radeon/r600_query.c | 3 -
src/gallium/drivers/radeonsi/si_shader.c | 16 -----
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 2
src/gallium/drivers/swr/SConscript | 2
src/gallium/state_trackers/dri/dri_screen.c | 12 ++++
src/gallium/state_trackers/osmesa/osmesa.c | 11 +++
src/intel/compiler/brw_vec4_gs_visitor.cpp | 1
src/intel/vulkan/anv_device.c | 4 -
src/loader/loader_dri3_helper.c | 18 ++++++
src/loader/loader_dri3_helper.h | 3 +
src/mesa/drivers/dri/i965/intel_blit.c | 5 -
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 2
src/mesa/main/uniform_query.cpp | 3 -
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 56 ++++++++++---------
src/mesa/state_tracker/st_manager.c | 2
31 files changed, 212 insertions(+), 104 deletions(-)
New commits:
commit 29df4deef2743f0474902a4e467bac76b5403adf
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Aug 7 12:45:40 2017 +0100
Update version to 17.2.0-rc3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index f309d4a..fd4078e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.2.0-rc2
+17.2.0-rc3
commit e4371d14f17049e4878966de60cfb88e8cd137cb
Author: Jason Ekstrand <jason@jlekstrand.net>
Date: Mon Jul 31 11:27:23 2017 -0700
anv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c72a100..f69ebfc 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -496,10 +496,6 @@ static const VkExtensionProperties device_extensions[] = {
.extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
.specVersion = 1,
},
- {
- .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
- .specVersion = 1,
- },
};
static void *
commit 0b2c034f6457ef62cc20d308a91620116cdc057d
Author: Tomasz Figa <tfiga@chromium.org>
Date: Sun Jul 30 00:02:46 2017 +0900
st/dri: enable 32-bit RGBX/RGBA formats only on Android
X/GLX can't handle them. This removes almost 500 GLX visuals that were
incorrectly exposed.
This is a less invasive version of Marek's .getCapability series.
Note: the patch is not applicable for master, but only for the 17.2
branch.
Suggested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
CC: <mesa-stable@lists.freedesktop.org>
Fixes: f33d8af7aa354d "st/dri: add 32-bit RGBX/RGBA formats"
[Emil Velikov: commit message polish]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/gallium/state_trackers/dri/dri_screen.c b/src/gallium/state_trackers/dri/dri_screen.c
index 59a850b..6bd4790 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -133,6 +133,11 @@ dri_fill_in_modes(struct dri_screen *screen)
MESA_FORMAT_B8G8R8A8_SRGB,
MESA_FORMAT_B8G8R8X8_SRGB,
MESA_FORMAT_B5G6R5_UNORM,
+#ifdef ANDROID
+ /*
+ * To reduce the risk of breaking non-Android users in stable release
+ * let's keep these for Android alone until this is handled properly.
+ */
/* The 32-bit RGBA format must not precede the 32-bit BGRA format.
* Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
@@ -154,6 +159,7 @@ dri_fill_in_modes(struct dri_screen *screen)
/* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
MESA_FORMAT_R8G8B8X8_UNORM,
+#endif
};
static const enum pipe_format pipe_formats[] = {
PIPE_FORMAT_BGRA8888_UNORM,
@@ -161,8 +167,14 @@ dri_fill_in_modes(struct dri_screen *screen)
PIPE_FORMAT_BGRA8888_SRGB,
PIPE_FORMAT_BGRX8888_SRGB,
PIPE_FORMAT_B5G6R5_UNORM,
+#ifdef ANDROID
+ /*
+ * To reduce the risk of breaking non-Android users in stable release
+ * let's keep these for Android alone until this is handled properly.
+ */
PIPE_FORMAT_RGBA8888_UNORM,
PIPE_FORMAT_RGBX8888_UNORM,
+#endif
};
mesa_format format;
__DRIconfig **configs = NULL;
commit f4e163094d9e4a0515adc695553d8af34be379fd
Author: Tim Rowley <timothy.o.rowley@intel.com>
Date: Mon Jul 31 16:59:06 2017 -0500
swr/rast: fix scons gen_knobs.h dependency
Copy/paste error was duplicating a gen_knobs.cpp rule.
Fixes: 5079c277b57 ("swr: [scons] Fix windows build")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit e4a6ae06cf01a21d7fe32e3ff2fc441102d68f82)
diff --git a/src/gallium/drivers/swr/SConscript b/src/gallium/drivers/swr/SConscript
index a32807d..c578d7a 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -53,7 +53,7 @@ env.CodeGenerate(
source = '',
command = python_cmd + ' $SCRIPT --output $TARGET --gen_h'
)
-Depends('rasterizer/codegen/gen_knobs.cpp',
+Depends('rasterizer/codegen/gen_knobs.h',
swrroot + 'rasterizer/codegen/templates/gen_knobs.cpp')
env.CodeGenerate(
commit 4a181e6244db1ac4ad1a098f485bdfc151db5325
Author: Timothy Arceri <tarceri@itsqueeze.com>
Date: Mon Jul 31 22:48:27 2017 +1000
mesa/st: fix conditional jump depends on uninitialised value
Reported by valgrind at:
glsl_to_tgsi_visitor::visit(ir_expression*) (st_glsl_to_tgsi.cpp:1560)
When compiling the Deus Ex shaders.
Fixes: 28a5e7104 ("st/glsl_to_tgsi: handle precise modifier")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 06237fc9e15e6274c24f89985a224135a617a491)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index d496fff..93b1eee 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4646,6 +4646,7 @@ glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
mem_ctx = ralloc_context(NULL);
ctx = NULL;
prog = NULL;
+ precise = 0;
shader_program = NULL;
shader = NULL;
options = NULL;
commit 8ef9fe7229d44ce222d77029e02326c92f068f55
Author: Scott D Phillips <scott.d.phillips@intel.com>
Date: Fri Jun 30 13:49:53 2017 -0700
gles: Restore some lost typedefs
GLES/gl.h has historically provided some typedefs that are not
used in the API itself. Restore these typedefs that were lost to
avoid breaking applications.
These seem to be the only typedefs removed in the update.
Fixes: 7fd0817 "Update Khronos-supplied headers"
[Eric: added a big warning to revert this patch when pulling the updated header]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 3db05ed1d10738d0c2f14cb692d5d618c5872dcd)
diff --git a/include/GLES/gl.h b/include/GLES/gl.h
index 056edb3..44dcddc 100644
--- a/include/GLES/gl.h
+++ b/include/GLES/gl.h
@@ -50,9 +50,22 @@ extern "C" {
#ifndef GL_VERSION_ES_CM_1_0
#define GL_VERSION_ES_CM_1_0 1
+
+/*
+ * XXX: Temporary fix; needs to be reverted as part of the next
+ * header update.
+ * For more details:
+ * https://github.com/KhronosGroup/OpenGL-Registry/pull/76
+ * https://lists.freedesktop.org/archives/mesa-dev/2017-June/161647.html
+ */
+#include <KHR/khrplatform.h>
+typedef khronos_int8_t GLbyte;
+typedef khronos_float_t GLclampf;
+typedef short GLshort;
+typedef unsigned short GLushort;
+
typedef void GLvoid;
typedef unsigned int GLenum;
-#include <KHR/khrplatform.h>
typedef khronos_float_t GLfloat;
typedef khronos_int32_t GLfixed;
typedef unsigned int GLuint;
diff --git a/include/GLES/glext.h b/include/GLES/glext.h
index 1012a7e..6ea91a1 100644
--- a/include/GLES/glext.h
+++ b/include/GLES/glext.h
@@ -104,7 +104,6 @@ GL_API void GL_APIENTRY glBlendEquationOES (GLenum mode);
#ifndef GL_OES_byte_coordinates
#define GL_OES_byte_coordinates 1
-typedef khronos_int8_t GLbyte;
#endif /* GL_OES_byte_coordinates */
#ifndef GL_OES_compressed_ETC1_RGB8_sub_texture
@@ -128,7 +127,6 @@ typedef khronos_int8_t GLbyte;
#ifndef GL_OES_draw_texture
#define GL_OES_draw_texture 1
-typedef short GLshort;
#define GL_TEXTURE_CROP_RECT_OES 0x8B9D
typedef void (GL_APIENTRYP PFNGLDRAWTEXSOESPROC) (GLshort x, GLshort y, GLshort z, GLshort width, GLshort height);
typedef void (GL_APIENTRYP PFNGLDRAWTEXIOESPROC) (GLint x, GLint y, GLint z, GLint width, GLint height);
@@ -409,7 +407,6 @@ GL_API GLbitfield GL_APIENTRY glQueryMatrixxOES (GLfixed *mantissa, GLint *expon
#ifndef GL_OES_single_precision
#define GL_OES_single_precision 1
-typedef khronos_float_t GLclampf;
typedef void (GL_APIENTRYP PFNGLCLEARDEPTHFOESPROC) (GLclampf depth);
typedef void (GL_APIENTRYP PFNGLCLIPPLANEFOESPROC) (GLenum plane, const GLfloat *equation);
typedef void (GL_APIENTRYP PFNGLDEPTHRANGEFOESPROC) (GLclampf n, GLclampf f);
commit 4f872e62c2dbd4ad522f87c858393ccaa507ca8e
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Jul 31 08:37:10 2017 +0100
Revert "st_glsl_to_tgsi: rewrite rename registers to use array fully."
This reverts commit 3008161d28e38336ba39aba4769a2deaf9732f55,
which caused a regression for VMWare.
The initial code had some recursion in it, that I removed by accident
trying to add back the recursion broke lots of things, take the high
road and revert for now.
Fixes: 3008161d (st_glsl_to_tgsi: rewrite rename registers to use array fully.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b8bea9a0506cc312f4b32762d73598a8a220cf08)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3983fe7..d496fff 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -399,7 +399,7 @@ find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
}
struct rename_reg_pair {
- bool valid;
+ int old_reg;
int new_reg;
};
@@ -568,7 +568,7 @@ public:
void simplify_cmp(void);
- void rename_temp_registers(struct rename_reg_pair *renames);
+ void rename_temp_registers(int num_renames, struct rename_reg_pair *renames);
void get_first_temp_read(int *first_reads);
void get_first_temp_write(int *first_writes);
void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
@@ -4835,37 +4835,36 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
/* Replaces all references to a temporary register index with another index. */
void
-glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
+glsl_to_tgsi_visitor::rename_temp_registers(int num_renames, struct rename_reg_pair *renames)
{
foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
unsigned j;
+ int k;
for (j = 0; j < num_inst_src_regs(inst); j++) {
- if (inst->src[j].file == PROGRAM_TEMPORARY) {
- int old_idx = inst->src[j].index;
- if (renames[old_idx].valid)
- inst->src[j].index = renames[old_idx].new_reg;
- }
+ if (inst->src[j].file == PROGRAM_TEMPORARY)
+ for (k = 0; k < num_renames; k++)
+ if (inst->src[j].index == renames[k].old_reg)
+ inst->src[j].index = renames[k].new_reg;
}
for (j = 0; j < inst->tex_offset_num_offset; j++) {
- if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
- int old_idx = inst->tex_offsets[j].index;
- if (renames[old_idx].valid)
- inst->tex_offsets[j].index = renames[old_idx].new_reg;
- }
+ if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
+ for (k = 0; k < num_renames; k++)
+ if (inst->tex_offsets[j].index == renames[k].old_reg)
+ inst->tex_offsets[j].index = renames[k].new_reg;
}
if (inst->resource.file == PROGRAM_TEMPORARY) {
- int old_idx = inst->resource.index;
- if (renames[old_idx].valid)
- inst->resource.index = renames[old_idx].new_reg;
+ for (k = 0; k < num_renames; k++)
+ if (inst->resource.index == renames[k].old_reg)
+ inst->resource.index = renames[k].new_reg;
}
for (j = 0; j < num_inst_dst_regs(inst); j++) {
- if (inst->dst[j].file == PROGRAM_TEMPORARY) {
- int old_idx = inst->dst[j].index;
- if (renames[old_idx].valid)
- inst->dst[j].index = renames[old_idx].new_reg;}
+ if (inst->dst[j].file == PROGRAM_TEMPORARY)
+ for (k = 0; k < num_renames; k++)
+ if (inst->dst[j].index == renames[k].old_reg)
+ inst->dst[j].index = renames[k].new_reg;
}
}
}
@@ -5446,6 +5445,7 @@ glsl_to_tgsi_visitor::merge_registers(void)
int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
int i, j;
+ int num_renames = 0;
/* Read the indices of the last read and first write to each temp register
* into an array so that we don't have to traverse the instruction list as
@@ -5472,8 +5472,9 @@ glsl_to_tgsi_visitor::merge_registers(void)
* as the register at index j. */
if (first_writes[i] <= first_writes[j] &&
last_reads[i] <= first_writes[j]) {
- renames[j].new_reg = i;
- renames[j].valid = true;
+ renames[num_renames].old_reg = j;
+ renames[num_renames].new_reg = i;
+ num_renames++;
/* Update the first_writes and last_reads arrays with the new
* values for the merged register index, and mark the newly unused
@@ -5486,7 +5487,7 @@ glsl_to_tgsi_visitor::merge_registers(void)
}
}
- rename_temp_registers(renames);
+ rename_temp_registers(num_renames, renames);
ralloc_free(renames);
ralloc_free(last_reads);
ralloc_free(first_writes);
@@ -5501,6 +5502,7 @@ glsl_to_tgsi_visitor::renumber_registers(void)
int new_index = 0;
int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
+ int num_renames = 0;
for (i = 0; i < this->next_temp; i++) {
first_writes[i] = -1;
@@ -5510,13 +5512,14 @@ glsl_to_tgsi_visitor::renumber_registers(void)
for (i = 0; i < this->next_temp; i++) {
if (first_writes[i] < 0) continue;
if (i != new_index) {
- renames[i].new_reg = new_index;
- renames[i].valid = true;
+ renames[num_renames].old_reg = i;
+ renames[num_renames].new_reg = new_index;
+ num_renames++;
}
new_index++;
}
- rename_temp_registers(renames);
+ rename_temp_registers(num_renames, renames);
this->next_temp = new_index;
ralloc_free(renames);
ralloc_free(first_writes);
commit c5fac38cedfb919d6dfa3e0760b2a6d4384db72a
Author: Dave Airlie <airlied@redhat.com>
Date: Thu Jul 27 21:52:20 2017 +0100
radv: handle 10-bit format clamping workaround.
This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.*
for a2r10g10b10 formats as destination on SI/CIK hardware.
This adds support to the meta program for emitting 10-bit
outputs, and adds 10-bit support to the fragment shader key.
It also only does the int8/10 on SI/CIK.
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit df61a05019d5c7479d4b29d251af4231f125e61c)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1a04af3..540976d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5185,6 +5185,7 @@ si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
unsigned index = target - V_008DFC_SQ_EXP_MRT;
unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
+ bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
switch(col_format) {
case V_028714_SPI_SHADER_ZERO:
@@ -5262,11 +5263,13 @@ si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
break;
case V_028714_SPI_SHADER_UINT16_ABGR: {
- LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
+ LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
+ is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
+ LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
for (unsigned chan = 0; chan < 4; chan++) {
val[chan] = to_integer(&ctx->ac, values[chan]);
- val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
+ val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
}
args->compr = 1;
@@ -5276,14 +5279,18 @@ si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
}
case V_028714_SPI_SHADER_SINT16_ABGR: {
- LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
- LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
+ LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
+ is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
+ LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
+ is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
+ LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->i32one;
+ LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
/* Clamp. */
for (unsigned chan = 0; chan < 4; chan++) {
val[chan] = to_integer(&ctx->ac, values[chan]);
- val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
- val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
+ val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
+ val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
}
args->compr = 1;
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 54d5489..af93a1c 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -57,6 +57,7 @@ struct ac_tcs_variant_key {
struct ac_fs_variant_key {
uint32_t col_format;
uint32_t is_int8;
+ uint32_t is_int10;
};
union ac_shader_variant_key {
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 718e9c5..3510e87 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -695,6 +695,8 @@ static VkFormat pipeline_formats[] = {
VK_FORMAT_R8G8B8A8_UNORM,
VK_FORMAT_R8G8B8A8_UINT,
VK_FORMAT_R8G8B8A8_SINT,
+ VK_FORMAT_A2R10G10B10_UINT_PACK32,
+ VK_FORMAT_A2R10G10B10_SINT_PACK32,
VK_FORMAT_R16G16B16A16_UNORM,
VK_FORMAT_R16G16B16A16_SNORM,
VK_FORMAT_R16G16B16A16_UINT,
diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c
index 2f18350..79e76be 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -1134,6 +1134,8 @@ static VkFormat pipeline_formats[] = {
VK_FORMAT_R8G8B8A8_UNORM,
VK_FORMAT_R8G8B8A8_UINT,
VK_FORMAT_R8G8B8A8_SINT,
+ VK_FORMAT_A2R10G10B10_UINT_PACK32,
+ VK_FORMAT_A2R10G10B10_SINT_PACK32,
VK_FORMAT_R16G16B16A16_UNORM,
VK_FORMAT_R16G16B16A16_SNORM,
VK_FORMAT_R16G16B16A16_UINT,
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index d007f97..e3d823f 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -754,6 +754,8 @@ static VkFormat pipeline_formats[] = {
VK_FORMAT_R8G8B8A8_UNORM,
VK_FORMAT_R8G8B8A8_UINT,
VK_FORMAT_R8G8B8A8_SINT,
+ VK_FORMAT_A2R10G10B10_UINT_PACK32,
+ VK_FORMAT_A2R10G10B10_SINT_PACK32,
VK_FORMAT_R16G16B16A16_UNORM,
VK_FORMAT_R16G16B16A16_SNORM,
VK_FORMAT_R16G16B16A16_UINT,
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index 65c5075..a90678a 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -160,6 +160,8 @@ static VkFormat pipeline_formats[] = {
VK_FORMAT_R8G8B8A8_UNORM,
VK_FORMAT_R8G8B8A8_UINT,
VK_FORMAT_R8G8B8A8_SINT,
+ VK_FORMAT_A2R10G10B10_UINT_PACK32,
+ VK_FORMAT_A2R10G10B10_SINT_PACK32,
VK_FORMAT_R16G16B16A16_UNORM,
VK_FORMAT_R16G16B16A16_SNORM,
VK_FORMAT_R16G16B16A16_UINT,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 496c06a..1fd1786 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1067,20 +1067,37 @@ format_is_int8(VkFormat format)
desc->channel[channel].size == 8;
}
+static bool
+format_is_int10(VkFormat format)
+{
+ const struct vk_format_description *desc = vk_format_description(format);
+
+ if (desc->nr_channels != 4)
+ return false;
+ for (unsigned i = 0; i < 4; i++) {
+ if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
+ return true;
+ }
+ return false;
+}
+
unsigned radv_format_meta_fs_key(VkFormat format)
{
unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
bool is_int8 = format_is_int8(format);
+ bool is_int10 = format_is_int10(format);
- return col_format + (is_int8 ? 3 : 0);
+ return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
}
-static unsigned
-radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
+static void
+radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
+ unsigned *is_int8, unsigned *is_int10)
{
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
- unsigned is_int8 = 0;
+ *is_int8 = 0;
+ *is_int10 = 0;
for (unsigned i = 0; i < subpass->color_count; ++i) {
struct radv_render_pass_attachment *attachment;
@@ -1091,10 +1108,10 @@ radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
attachment = pass->attachments + subpass->color_attachments[i].attachment;
if (format_is_int8(attachment->format))
- is_int8 |= 1 << i;
+ *is_int8 |= 1 << i;
+ if (format_is_int10(attachment->format))
+ *is_int10 |= 1 << i;
}
-
- return is_int8;
}
static void
@@ -2053,9 +2070,11 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
}
if (modules[MESA_SHADER_FRAGMENT]) {
- union ac_shader_variant_key key;
+ union ac_shader_variant_key key = {0};
key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
- key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
+
+ if (pipeline->device->physical_device->rad_info.chip_class < VI)
+ radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 8cd5ec0..6ccce8e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -84,7 +84,7 @@ typedef uint32_t xcb_window_t;
#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_BUFFERS 16
#define MAX_SAMPLES_LOG2 4
-#define NUM_META_FS_KEYS 11
+#define NUM_META_FS_KEYS 13
#define RADV_MAX_DRM_DEVICES 8
#define NUM_DEPTH_CLEAR_PIPELINES 3
commit 579ecfd91e3c3320e17c8a2709bdc35d813bb61f
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Jul 30 23:26:11 2017 +0200
radv: Don't underflow non-visible VRAM size.
In some APU situations the reported visible size can be larger than
VRAM size. This properly clamps the value.
Surprisingly both CTS and spec seem to allow a heap type with size 0,
so this seemed like the easiest option to me.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes: 4ae84efbc5c "radv: Use enum for memory heaps."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 8229706ad86b27ed571f17872006a488fcd35378)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 0de7b8b..7cf4b12 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -928,15 +928,17 @@ void radv_GetPhysicalDeviceMemoryProperties(
};
STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
+ uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
+ physical_device->rad_info.vram_vis_size);
pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
.size = physical_device->rad_info.vram_size -
- physical_device->rad_info.vram_vis_size,
+ visible_vram_size,
.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
};
pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
- .size = physical_device->rad_info.vram_vis_size,
+ .size = visible_vram_size,
.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
};
pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
commit 6b279b32718cc6e0397a368269d3ad52fd685aad
Author: Bruce Cherniak <bruce.cherniak@intel.com>
Date: Wed Aug 2 18:14:19 2017 -0500
st/osmesa: add osmesa framebuffer iface hash table per st manager
Commit bbc29393d3 didn't include osmesa state_tracker. This patch adds
necessary initialization.
Fixes crash in OSMesa initialization.
Created-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 9966c85e01a4344d2a6bb76e432e0bed70d52ff6)
diff --git a/src/gallium/state_trackers/osmesa/osmesa.c b/src/gallium/state_trackers/osmesa/osmesa.c
index 18f1b88..751d255 100644
--- a/src/gallium/state_trackers/osmesa/osmesa.c
+++ b/src/gallium/state_trackers/osmesa/osmesa.c
@@ -439,6 +439,7 @@ osmesa_st_framebuffer_validate(struct st_context_iface *stctx,
return TRUE;
}
+static uint32_t osmesa_fb_ID = 0;
static struct st_framebuffer_iface *
osmesa_create_st_framebuffer(void)
@@ -448,6 +449,8 @@ osmesa_create_st_framebuffer(void)
stfbi->flush_front = osmesa_st_framebuffer_flush_front;
stfbi->validate = osmesa_st_framebuffer_validate;
p_atomic_set(&stfbi->stamp, 1);
+ stfbi->ID = p_atomic_inc_return(&osmesa_fb_ID);
+ stfbi->state_manager = get_st_manager();
}
return stfbi;
}
@@ -508,6 +511,14 @@ osmesa_find_buffer(enum pipe_format color_format,
static void
osmesa_destroy_buffer(struct osmesa_buffer *osbuffer)
{
+ struct st_api *stapi = get_st_api();
+
+ /*
+ * Notify the state manager that the associated framebuffer interface
+ * is no longer valid.
+ */
+ stapi->destroy_drawable(stapi, osbuffer->stfb);
+
FREE(osbuffer->stfb);
FREE(osbuffer);
}
commit 6efb8d79a9aa33c6b2ac61c1544ef1a9e12f3d8b
Author: Dave Airlie <airlied@gmail.com>
Date: Thu Aug 3 13:48:40 2017 +1000
intel/vec4/gs: reset nr_pull_param if DUAL_INSTANCED compile failed.
If dual object compile fails (as seems to happen with virgl a
fair bit, and does piglit even have any tests for it?), we end up
not restarting the pull params, so we call
vec4_visitor::move_uniform_array_access_to_pull_constant
a second time and it runs over the ends of the alloc.
Fixes: tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test
running inside virgl on ivybridge.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 271fa3a684ef0eefe99087c13d1abb099784163f)
diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp
index ca59927..a8e445c 100644
--- a/src/intel/compiler/brw_vec4_gs_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp
@@ -912,6 +912,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
memcpy(prog_data->base.base.param, param,
sizeof(gl_constant_value*) * param_count);
prog_data->base.base.nr_params = param_count;
+ prog_data->base.base.nr_pull_params = 0;
ralloc_free(param);
}
}
commit 795b712bd7f455fddd8779ac75f038392cec510c
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Jul 31 10:56:15 2017 +0100
i965/blit: Remember to include miptree buffer offset in relocs
Remember to add the offset to the start of the buffer in the relocation
or else we write 0xff into random bytes elsewhere.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit fb63c43fd1b7adb5cb4f34e7616e7d564ca178e5)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index b1db7aa..a9cdf48 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -830,11 +830,11 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
if (brw->gen >= 8) {
OUT_RELOC64(mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ mt->offset + offset);
} else {
OUT_RELOC(mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ mt->offset + offset);
}
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index aeea3c8..8d467ad 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -294,7 +294,7 @@ do_blit_bitmap( struct gl_context *ctx,
color,
irb->mt->surf.row_pitch,
irb->mt->bo,
- 0,
+ irb->mt->offset,
irb->mt->surf.tiling,
dstx + px,
dsty + py,
commit 43a2b178c294b054c932687bdc0b5bb8303529a9
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon Jul 31 22:04:25 2017 -0700
i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index eca8736..b1db7aa 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -187,7 +187,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
* The offsets we get from ISL in the tiled case are already aligned.
* In the linear case, we need to do some of our own aligning.
*/
- assert(mt->surf.row_pitch % 64 == 0);
uint32_t delta = *base_address_offset & 63;
assert(delta % mt->cpp == 0);
*base_address_offset -= delta;
commit d5def4f5a97d3ebdc5f1d34f8c03259510229a53
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed Jul 12 11:36:29 2017 -0700
spirv: Fix SpvImageFormatR16ui
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.1 17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 95c6a97464e7baaca6e09f829da0be5ac8c50297)
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 4b9c121..7b34dad 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -721,7 +721,7 @@ translate_image_format(SpvImageFormat format)
case SpvImageFormatRg32ui: return 0x823C; /* GL_RG32UI */
case SpvImageFormatRg16ui: return 0x823A; /* GL_RG16UI */
case SpvImageFormatRg8ui: return 0x8238; /* GL_RG8UI */
- case SpvImageFormatR16ui: return 0x823A; /* GL_RG16UI */
+ case SpvImageFormatR16ui: return 0x8234; /* GL_R16UI */
case SpvImageFormatR8ui: return 0x8232; /* GL_R8UI */
default:
assert(!"Invalid image format");
commit f2a60ff20a8248aa5d8d5949e8f433c97b3a3506
Author: Thomas Hellstrom <thellstrom@vmware.com>
Date: Thu Jun 22 09:24:34 2017 +0200
dri3: Wait for all pending swapbuffers to be scheduled before touching the front
This implements a wait for glXWaitGL, glXCopySubBuffer, dri flush_front and
creation of fake front until all pending SwapBuffers have been committed to
hardware. Among other things this fixes piglit glx-copy-sub-buffers on dri3.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 185ef06fd2db782d9d3d6046580f7cece02c4797)
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 1c93e7a..c2ae895 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -504,6 +504,7 @@ loader_dri3_copy_sub_buffer(struct loader_dri3_drawable *draw,
x, y, width, height, __BLIT_FLAG_FLUSH);
}
+ loader_dri3_swapbuffer_barrier(draw);
dri3_fence_reset(draw->conn, back);
dri3_copy_area(draw->conn,
dri3_back_buffer(draw)->pixmap,
@@ -595,6 +596,7 @@ loader_dri3_wait_gl(struct loader_dri3_drawable *draw)
front->height,
0, 0, front->width,
front->height, __BLIT_FLAG_FLUSH);
+ loader_dri3_swapbuffer_barrier(draw);
loader_dri3_copy_drawable(draw, draw->drawable, front->pixmap);
}
@@ -1258,6 +1260,7 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
}
break;
case loader_dri3_buffer_front:
+ loader_dri3_swapbuffer_barrier(draw);
dri3_fence_reset(draw->conn, new_buffer);
dri3_copy_area(draw->conn,
draw->drawable,
@@ -1431,3 +1434,18 @@ loader_dri3_update_drawable_geometry(struct loader_dri3_drawable *draw)
free(geom_reply);
}
}
+
+
+/**
+ * Make sure the server has flushed all pending swap buffers to hardware
+ * for this drawable. Ideally we'd want to send an X protocol request to
+ * have the server block our connection until the swaps are complete. That
+ * would avoid the potential round-trip here.
+ */
+void
+loader_dri3_swapbuffer_barrier(struct loader_dri3_drawable *draw)
+{
+ int64_t ust, msc, sbc;
+
+ (void) loader_dri3_wait_for_sbc(draw, 0, &ust, &msc, &sbc);
+}
diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
index a865e46..659b63a 100644
--- a/src/loader/loader_dri3_helper.h
+++ b/src/loader/loader_dri3_helper.h
@@ -241,4 +241,7 @@ loader_dri3_get_buffers(__DRIdrawable *driDrawable,
void
loader_dri3_update_drawable_geometry(struct loader_dri3_drawable *draw);
+
+void
+loader_dri3_swapbuffer_barrier(struct loader_dri3_drawable *draw);
#endif
commit 3c8673d42035e79da6879f7204d48abecb4b67ff
Author: Nicolai Hähnle <nicolai.haehnle@amd.com>
Date: Thu Jul 27 14:06:59 2017 +0200
gallium/radeon: fix ARB_query_buffer_object conversion to boolean
The issue here is that the immediate is treated as a 64-bit value,
and fetching it does not work reliably with swizzles that are different
from xy and zw.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit da83687c4ba7e9022f6f14176393a9e3c6391ed5)
diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index db70878..28c896a 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -1373,6 +1373,7 @@ static void r600_create_query_result_shader(struct r600_common_context *rctx)
"IMM[1] UINT32 {1, 2, 4, 8}\n"
"IMM[2] UINT32 {16, 32, 64, 128}\n"
"IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
+ "IMM[4] UINT32 {0, 0, 0, 0}\n"
"AND TEMP[5], CONST[0].wwww, IMM[2].xxxx\n"
"UIF TEMP[5]\n"
@@ -1472,7 +1473,7 @@ static void r600_create_query_result_shader(struct r600_common_context *rctx)
/* Convert to boolean */
"AND TEMP[4], CONST[0].wwww, IMM[1].wwww\n"
"UIF TEMP[4]\n"
- "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[0].xxxx\n"
+ "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
"AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
"MOV TEMP[0].y, IMM[0].xxxx\n"
"ENDIF\n"
commit 381ccaa1cbff41a8626f0bf3ac5fe90500598226
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Aug 1 05:10:49 2017 +0100
radeon/ac: use ds_swizzle for derivs on si/cik.
This looks like it's supported since llvm 3.9 at least,
so switch over radeonsi and radv to using it, -pro also
uses this. We can now drop creating lds for these operations
as the ds_swizzle operation doesn't actually write to lds at all.
Acked-by: Marek Olšák <marek.olsak@amd.com>
(stable requested due to fixing radv CIK conformance tests)
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