mesa: Changes to 'upstream-unstable'
VERSION | 2
bin/.cherry-ignore | 7
bin/get-pick-list.sh | 2
configure.ac | 15
docs/relnotes/13.0.5.html | 3
docs/relnotes/13.0.6.html | 286 ++++++++++
src/amd/common/ac_nir_to_llvm.c | 28
src/amd/vulkan/radv_cmd_buffer.c | 10
src/amd/vulkan/radv_descriptor_set.c | 7
src/amd/vulkan/radv_device.c | 2
src/amd/vulkan/radv_formats.c | 3
src/amd/vulkan/radv_image.c | 6
src/amd/vulkan/radv_meta_blit2d.c | 7
src/amd/vulkan/radv_meta_buffer.c | 2
src/amd/vulkan/radv_private.h | 1
src/amd/vulkan/radv_query.c | 72 +-
src/amd/vulkan/si_cmd_buffer.c | 3
src/compiler/glsl/ast_to_hir.cpp | 17
src/compiler/glsl/builtin_functions.cpp | 18
src/compiler/glsl/ir_optimization.h | 4
src/compiler/glsl/link_uniforms.cpp | 2
src/compiler/glsl/lower_instructions.cpp | 19
src/compiler/spirv/vtn_variables.c | 3
src/egl/drivers/dri2/egl_dri2.c | 14
src/egl/drivers/dri2/platform_x11_dri3.c | 20
src/gallium/auxiliary/gallivm/lp_bld_init.c | 5
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 41 +
src/gallium/auxiliary/tgsi/tgsi_sanity.c | 8
src/gallium/auxiliary/util/u_index_modify.c | 87 ---
src/gallium/auxiliary/util/u_index_modify.h | 26
src/gallium/auxiliary/util/u_queue.c | 79 ++
src/gallium/auxiliary/util/u_queue.h | 4
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 51 -
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 12
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 5
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 4
src/gallium/drivers/r300/r300_render_translate.c | 4
src/gallium/drivers/r300/r300_texture.c | 5
src/gallium/drivers/r600/r600_state_common.c | 2
src/gallium/drivers/radeon/r600_pipe_common.h | 1
src/gallium/drivers/radeonsi/si_descriptors.c | 14
src/gallium/drivers/radeonsi/si_pipe.h | 3
src/gallium/drivers/radeonsi/si_shader.c | 35 -
src/gallium/drivers/radeonsi/si_shader.h | 1
src/gallium/drivers/radeonsi/si_state.c | 35 -
src/gallium/drivers/radeonsi/si_state_draw.c | 66 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 12
src/gallium/drivers/swr/rasterizer/core/threads.cpp | 9
src/gallium/drivers/swr/swr_query.cpp | 7
src/gallium/drivers/swr/swr_query.h | 2
src/gallium/state_trackers/clover/Makefile.am | 3
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 17
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 6
src/glx/dri3_glx.c | 10
src/glx/glxcmds.c | 18
src/intel/blorp/blorp_clear.c | 48 +
src/intel/blorp/blorp_genX_exec.h | 21
src/intel/genxml/gen6.xml | 2
src/intel/genxml/gen7.xml | 2
src/intel/genxml/gen75.xml | 2
src/intel/vulkan/anv_device.c | 24
src/intel/vulkan/anv_private.h | 13
src/intel/vulkan/anv_query.c | 25
src/intel/vulkan/anv_wsi.c | 23
src/intel/vulkan/genX_blorp_exec.c | 11
src/intel/vulkan/genX_cmd_buffer.c | 30 +
src/loader/loader_dri3_helper.c | 23
src/loader/loader_dri3_helper.h | 2
src/mapi/glapi/gen/gl_API.xml | 2
src/mesa/drivers/dri/common/dri_util.c | 12
src/mesa/drivers/dri/i965/brw_context.c | 3
src/mesa/drivers/dri/i965/brw_defines.h | 6
src/mesa/drivers/dri/i965/brw_fs.cpp | 47 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 76 --
src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 5
src/mesa/drivers/dri/i965/brw_state.h | 7
src/mesa/drivers/dri/i965/brw_state_upload.c | 3
src/mesa/drivers/dri/i965/gen6_viewport_state.c | 150 +++--
src/mesa/drivers/dri/i965/gen7_viewport_state.c | 39 -
src/mesa/drivers/dri/i965/gen8_depth_state.c | 12
src/mesa/drivers/dri/i965/gen8_viewport_state.c | 48 -
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 8
src/mesa/drivers/dri/i965/intel_blit.c | 10
src/mesa/drivers/dri/i965/intel_screen.c | 1
src/mesa/main/api_validate.c | 45 -
src/mesa/main/attrib.c | 3
src/mesa/main/extensions_table.h | 2
src/mesa/state_tracker/st_atom.c | 10
src/mesa/state_tracker/st_atom_sampler.c | 2
src/mesa/state_tracker/st_cb_readpixels.c | 13
src/mesa/state_tracker/st_cb_texture.c | 6
src/mesa/state_tracker/st_context.c | 13
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 11
src/util/ralloc.c | 15
src/vulkan/wsi/wsi_common_x11.c | 51 +
98 files changed, 1392 insertions(+), 569 deletions(-)
New commits:
commit fcef88d13a9ebdcadc6a878e9284c55651785301
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Mar 20 11:42:19 2017 +0000
docs: add release notes for 13.0.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/13.0.6.html b/docs/relnotes/13.0.6.html
new file mode 100644
index 0000000..13464dd
--- /dev/null
+++ b/docs/relnotes/13.0.6.html
@@ -0,0 +1,286 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 13.0.6 Release Notes / March 20, 2017</h1>
+
+<p>
+Mesa 13.0.6 is a bug fix release which fixes bugs found since the 13.0.5 release.
+</p>
+<p>
+Mesa 13.0.6 implements the OpenGL 4.4 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.4. OpenGL
+4.4 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68504";>Bug 68504</a> - 9.2-rc1 workaround for clover build failure on ppc/altivec: cannot convert 'bool' to '__vector(4) __bool int' in return</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97102";>Bug 97102</a> - [dri][swr] stack overflow / infinite loop with GALLIUM_DRIVER=swr</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=98869";>Bug 98869</a> - Electronic Super Joy graphic artefacts (regression,bisected)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99401";>Bug 99401</a> - [g33] regression: piglit.spec.!opengl 1_0.gl-1_0-beginend-coverage</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99456";>Bug 99456</a> - Firefox crashing when opening about:support with WebGL2 enabled</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99677";>Bug 99677</a> - heap-use-after-free in glsl</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99715";>Bug 99715</a> - Don't print: "Note: Buggy applications may crash, if they do please report to vendor"</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99850";>Bug 99850</a> - Tessellation bug on Carrizo</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100049";>Bug 100049</a> - "ralloc: Make sure ralloc() allocations match malloc()'s alignment." causes seg fault in 32bit build</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Alex Smith (2):</p>
+<ul>
+ <li>radv: Emit pending flushes before executing a secondary command buffer</li>
+ <li>radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer</li>
+</ul>
+
+<p>Bartosz Tomczyk (1):</p>
+<ul>
+ <li>glsl: fix heap-buffer-overflow</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (8):</p>
+<ul>
+ <li>radv: Pass CMASK alignment to application.</li>
+ <li>radv: Pass DCC alignment to application.</li>
+ <li>radv: Never try to create more than max_sets descriptor sets.</li>
+ <li>radv: Reset emitted compute pipeline when calling secondary cmd buffer.</li>
+ <li>radv: Only use PKT3_OCCLUSION_QUERY when it doesn't hang.</li>
+ <li>radv: Use correct size for availability flag.</li>
+ <li>radv: Disable HTILE for textures with multiple layers/levels.</li>
+ <li>radv: Emit cache flushes before CP DMA.</li>
+</ul>
+
+<p>Ben Crocker (3):</p>
+<ul>
+ <li>gallivm: Improve debug output (V2)</li>
+ <li>gallivm: Override getHostCPUName() "generic" w/ "pwr8" (v4)</li>
+ <li>gallivm: Reenable PPC VSX (v3)</li>
+</ul>
+
+<p>Brendan King (1):</p>
+<ul>
+ <li>egl/dri3: implement query surface hook</li>
+</ul>
+
+<p>Bruce Cherniak (1):</p>
+<ul>
+ <li>swr: Prune empty nodes in CalculateProcessorTopology.</li>
+</ul>
+
+<p>Connor Abbott (1):</p>
+<ul>
+ <li>anv: fix Get*MemoryRequirements for !LLC</li>
+</ul>
+
+<p>Dave Airlie (13):</p>
+<ul>
+ <li>radv: program a default point size.</li>
+ <li>radv: handle transfer_write as a dst flag.</li>
+ <li>radv/ac: handle nir irem opcode.</li>
+ <li>radv/ac: implement txs for buffer textures.</li>
+ <li>radv/ac: correctly size shared memory usage.</li>
+ <li>radv/ac: avoid the fmask path when doing txs.</li>
+ <li>radv: pass FMASK alignment to application</li>
+ <li>tgsi: fix memory leak in tgsi sanity check</li>
+ <li>radv: fix depth format in blit2d.</li>
+ <li>radv: fix txs for sampler buffers</li>
+ <li>radv: drop Z24 support.</li>
+ <li>radv: disable mip point pre clamping.</li>
+ <li>radv: setup llvm target data layout</li>
+</ul>
+
+<p>Emil Velikov (6):</p>
+<ul>
+ <li>docs: add sha256 checksums for 13.0.5</li>
+ <li>Revert "get-pick-list.sh: Require explicit "13.0" for nominating stable patches"</li>
+ <li>cherry-ignore: don't pick nir_op_pack_double optimisation fix</li>
+ <li>i965: move brw_define.h ifndef guard to the top</li>
+ <li>cherry-ignore: add ANV fast clears related fixes</li>
+ <li>Update version to 13.0.6</li>
+</ul>
+
+<p>Fredrik Höglund (2):</p>
+<ul>
+ <li>radv: fix the dynamic buffer index in vkCmdBindDescriptorSets</li>
+ <li>radv/ac: fix multiple descriptor sets with dynamic buffers</li>
+</ul>
+
+<p>George Kyriazis (1):</p>
+<ul>
+ <li>swr: Align query results allocation</li>
+</ul>
+
+<p>Grazvydas Ignotas (3):</p>
+<ul>
+ <li>r300g: only allow byteswapped formats on big endian</li>
+ <li>gallium/u_queue: fix a crash with atexit handlers</li>
+ <li>gallium/u_queue: set num_threads correctly if not all threads start</li>
+</ul>
+
+<p>Gregory Hainaut (1):</p>
+<ul>
+ <li>glapi: fix typo in count_scale</li>
+</ul>
+
+<p>Ian Romanick (1):</p>
+<ul>
+ <li>mesa: Don't advertise GL_OES_read_format in core profile</li>
+</ul>
+
+<p>Ilia Mirkin (8):</p>
+<ul>
+ <li>nvc0: increase number of ubo binding points</li>
+ <li>nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ compute</li>
+ <li>nvc0/ir: fix ubo max clamp, reset file index</li>
+ <li>gm107/ir: fix address offset bitfield for ATOMS</li>
+ <li>nvc0: set the render condition in the compute object</li>
+ <li>st/mesa: don't pass compare mode for stencil-sampled textures</li>
+ <li>nvc0: take extra pushbuf space into account for pushbuf_space calls</li>
+ <li>nvc0: increase alignment to 256 for texture buffers on fermi</li>
+</ul>
+
+<p>Jacob Lifshay (1):</p>
+<ul>
+ <li>vulkan/wsi: Improve the DRI3 error message</li>
+</ul>
+
+<p>Jason Ekstrand (11):</p>
+<ul>
+ <li>i965: Use a better guardband calculation.</li>
+ <li>intel/blorp: Swizzle clear colors on the CPU</li>
+ <li>i965/fs: Remove the inline pack_double_2x32 optimization</li>
+ <li>anv: Add an invalidate_range helper</li>
+ <li>anv/query: clflush the bo map on non-LLC platforms</li>
+ <li>genxml: Make MI_STORE_DATA_IMM more consistent</li>
+ <li>anv/query: Perform CmdResetQueryPool on the GPU</li>
+ <li>blorp/exec: Use uint32_t for copying varying data</li>
+ <li>intel/blorp: Explicitly flush all allocated state</li>
+ <li>anv: Accurately advertise dynamic descriptor limits</li>
+ <li>anv: Properly handle destroying NULL devices and instances</li>
+</ul>
+
+<p>Jonas Pfeil (1):</p>
+<ul>
+ <li>ralloc: Make sure ralloc() allocations match malloc()'s alignment.</li>
+</ul>
+
+<p>Jose Maria Casanova Crespo (1):</p>
+<ul>
+ <li>glsl: non-last member unsized array on SSBO must fail compilation on GLSL ES 3.1</li>
+</ul>
+
+<p>Kenneth Graunke (7):</p>
+<ul>
+ <li>i965: Fix fast depth clears for surfaces with a dimension of 16384.</li>
+ <li>i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.</li>
+ <li>i965: Fix check for negative pitch in can_do_fast_copy_blit().</li>
+ <li>i965: Support the force_glsl_version driconf option.</li>
+ <li>i965: Combine the Gen6 SF and Clip viewport atoms.</li>
+ <li>mesa: Do (TCS && !TES) draw time validation in ES as well.</li>
+ <li>egl: Ensure ResetNotificationStrategy matches for shared contexts.</li>
+</ul>
+
+<p>Lionel Landwerlin (3):</p>
+<ul>
+ <li>spirv: don't assert with location decorations on non i/o variables</li>
+ <li>anv: wsi: report presentation error per image request</li>
+ <li>i965/fs: fix uninitialized memory access</li>
+</ul>
+
+<p>Marc Di Luzio (1):</p>
+<ul>
+ <li>glsl: correct compute shader checks for memoryBarrier functions</li>
+</ul>
+
+<p>Marek Olšák (10):</p>
+<ul>
+ <li>st/mesa: destroy pipe_context before destroying st_context (v2)</li>
+ <li>radeonsi: don't invoke DCC decompression in update_all_texture_descriptors</li>
+ <li>radeonsi: fix UNSIGNED_BYTE index buffer fallback with non-zero start (v2)</li>
+ <li>gallium/util: remove unused u_index_modify helpers</li>
+ <li>gallium/u_index_modify: don't add PIPE_TRANSFER_UNSYNCHRONIZED unconditionally</li>
+ <li>gallium/u_queue: fix random crashes when the app calls exit()</li>
+ <li>st/mesa: reset sample_mask, min_sample, and render_condition for PBO ops</li>
+ <li>st/mesa: set blend state for PBO readbacks</li>
+ <li>radeonsi: fix broken tessellation on Carrizo and Stoney</li>
+ <li>radeonsi: mark all bound shader buffer ranges as initialized</li>
+</ul>
+
+<p>Matt Turner (1):</p>
+<ul>
+ <li>clover: Work around build failure with AltiVec.</li>
+</ul>
+
+<p>Nicolai Hähnle (12):</p>
+<ul>
+ <li>mesa/main: fix meta caller of _mesa_ClampColor</li>
+ <li>radeonsi: fix texture gather on stencil textures</li>
+ <li>glsl: split DIV_TO_MUL_RCP into single- and double-precision flags</li>
+ <li>glx/dri3: handle NULL pointers in loader-to-DRI3 drawable conversion</li>
+ <li>glx/dri3: guard in_current_context against a disappeared drawable</li>
+ <li>glx: guard swap-interval functions against destroyed drawables</li>
+ <li>dri/common: clear the loaderPrivate pointer in driDestroyDrawable</li>
+ <li>winsys/amdgpu: reduce max_alloc_size based on GTT limits</li>
+ <li>radeonsi: handle MultiDrawIndirect in si_get_draw_start_count</li>
+ <li>radeonsi: fix UINT/SINT clamping for 10-bit formats on <= CIK</li>
+ <li>st/glsl_to_tgsi: avoid iterating past the head of the instruction list</li>
+ <li>st/mesa: inform the driver of framebuffer changes before compute dispatches</li>
+</ul>
+
+<p>Samuel Iglesias Gonsálvez (6):</p>
+<ul>
+ <li>glsl: fix heap-use-after-free in ast_declarator_list::hir()</li>
+ <li>i965/fs: mark last DF uniform array element as 64 bit live one</li>
+ <li>i965/fs: detect different bit size accesses to uniforms to push them in proper locations</li>
+ <li>i965/fs: fix indirect load DF uniforms on BSW/BXT</li>
+ <li>i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles</li>
+ <li>i965/fs: emit MOV_INDIRECT with the source with the right register type</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+ <li>winsys/amdgpu: avoid potential segfault in amdgpu_bo_map()</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 069f00bf92d7bb9827b6f8bbd2065afd6660a115
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Fri Mar 17 18:13:30 2017 +0000
Update version to 13.0.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index f64807a..6fe535b 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-13.0.5
+13.0.6
commit 3b782f6bc405971e70a090be90a2899bb6d751fc
Author: Matt Turner <mattst88@gmail.com>
Date: Thu Mar 2 04:43:21 2017 +0000
clover: Work around build failure with AltiVec.
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=587210
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68504
Acked-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 7d1195c1e4d071fe796bf5f210c468ea1cc86225)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
configure.ac
diff --git a/configure.ac b/configure.ac
index fd78fbb..16ceea8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1974,6 +1974,21 @@ if test "x$enable_opencl" = xyes; then
if test "x$have_libelf" != xyes; then
AC_MSG_ERROR([Clover requires libelf])
fi
+
+ if test "x${ac_cv_cxx_compiler_gnu}" = xyes; then
+ altivec_enabled=no
+ AC_COMPILE_IFELSE([AC_LANG_SOURCE([
+ #if !defined(__VEC__) || !defined(__ALTIVEC__)
+ #error "AltiVec not enabled"
+ #endif
+ ])], altivec_enabled=yes)
+
+ if test "$altivec_enabled" = yes; then
+ CLOVER_STD_OVERRIDE="-std=gnu++11"
+ fi
+ AC_SUBST([CLOVER_STD_OVERRIDE])
+ fi
+
fi
AM_CONDITIONAL(HAVE_CLOVER, test "x$enable_opencl" = xyes)
AM_CONDITIONAL(HAVE_CLOVER_ICD, test "x$enable_opencl_icd" = xyes)
diff --git a/src/gallium/state_trackers/clover/Makefile.am b/src/gallium/state_trackers/clover/Makefile.am
index 8abcfec..edf1e26 100644
--- a/src/gallium/state_trackers/clover/Makefile.am
+++ b/src/gallium/state_trackers/clover/Makefile.am
@@ -33,6 +33,7 @@ noinst_LTLIBRARIES = libclover.la libcltgsi.la libclllvm.la
libcltgsi_la_CXXFLAGS = \
-std=c++11 \
+ $(CLOVER_STD_OVERRIDE) \
$(VISIBILITY_CXXFLAGS)
libcltgsi_la_SOURCES = $(TGSI_SOURCES)
@@ -41,6 +42,7 @@ libclllvm_la_CXXFLAGS = \
-std=c++11 \
$(VISIBILITY_CXXFLAGS) \
$(LLVM_CXXFLAGS) \
+ $(CLOVER_STD_OVERRIDE) \
$(DEFINES) \
$(LIBELF_CFLAGS) \
-DLIBCLC_INCLUDEDIR=\"$(LIBCLC_INCLUDEDIR)/\" \
@@ -51,6 +53,7 @@ libclllvm_la_SOURCES = $(LLVM_SOURCES)
libclover_la_CXXFLAGS = \
-std=c++11 \
+ $(CLOVER_STD_OVERRIDE) \
$(VISIBILITY_CXXFLAGS)
libclover_la_LIBADD = \
commit 97d68c863ce2d42e83ae567e9a542198d0f98ca7
Author: Alex Smith <asmith@feralinteractive.com>
Date: Tue Mar 14 15:26:32 2017 +0000
radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer
Need to flush before updating the buffer to ensure that the copy is
ordered after previous accesses (assuming the app has performed the
appropriate barriers).
This fixes potential issues due to draws prior to an update reading
the new buffer content, despite having the necessary barriers between
them.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e0cc32b85bd8cf5c2202037838a208983e2d793a)
diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index adea25e..a1188e7 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -523,6 +523,8 @@ void radv_CmdUpdateBuffer(
assert(!(va & 3));
if (dataSize < 4096) {
+ si_emit_cache_flush(cmd_buffer);
+
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);
commit 01c264c35caf2f4fa76c1f689b0826a9553106fa
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Tue Mar 14 21:46:54 2017 +0100
radv: Emit cache flushes before CP DMA.
The flushes could be due to TRANSFER barriers.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit cce43f6d8c40222099badaf52344d6a0eed993f3)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 0a78e04..332f9ff 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -853,6 +853,7 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
uint64_t main_src_va, main_dest_va;
uint64_t skipped_size = 0, realign_size = 0;
+ si_emit_cache_flush(cmd_buffer);
if (cmd_buffer->device->instance->physicalDevice.rad_info.family <= CHIP_CARRIZO ||
cmd_buffer->device->instance->physicalDevice.rad_info.family == CHIP_STONEY) {
@@ -916,6 +917,8 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
assert(va % 4 == 0 && size % 4 == 0);
+ si_emit_cache_flush(cmd_buffer);
+
while (size) {
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
unsigned dma_flags = 0;
commit 1d143f0018d29c7f3867a8a7f3249aeeb931c1d4
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Mar 14 06:50:59 2017 +1000
radv: setup llvm target data layout
Ported from radeonsi, pointed out by Tom.
"This prevents LLVM from using sext instructions for local memory
offsets and allows the backend to fold immediate offsets into the
instruction. This also prevents some incorrect code generation for
ptrtoint and inttoptr instructions."
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tom Stellard <tstellar@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b8ee70384adc3286d18febba7a92047118cc0f0f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index dc7ccf5..60a3f09 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4499,6 +4499,13 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
memset(shader_info, 0, sizeof(*shader_info));
LLVMSetTarget(ctx.module, "amdgcn--");
+
+ LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
+ char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
+ LLVMSetDataLayout(ctx.module, data_layout_str);
+ LLVMDisposeTargetData(data_layout);
+ LLVMDisposeMessage(data_layout_str);
+
setup_types(&ctx);
ctx.builder = LLVMCreateBuilderInContext(ctx.context);
commit dac86c5d3cc5df61e3b1c429554bbb0587434bf4
Author: Marek Olšák <marek.olsak@amd.com>
Date: Mon Mar 6 01:47:52 2017 +0100
radeonsi: mark all bound shader buffer ranges as initialized
This should prevent cases when a buffer was incorrectly mapped without
synchronization just because this wasn't done.
Cc: 13.0 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 71a2e4e9452a6890197f8b629b2d8359bdd58913)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 1f3b827..4b22d01 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1200,6 +1200,9 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
descs->dirty_mask |= 1u << slot;
sctx->descriptors_dirty |=
1u << si_shader_buffer_descriptors_idx(shader);
+
+ util_range_add(&buf->valid_buffer_range, sbuffer->buffer_offset,
+ sbuffer->buffer_offset + sbuffer->buffer_size);
}
}
commit 0fbac2d641a4d4104c2e6f7a89a123c557d7e750
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Wed Mar 15 16:38:03 2017 +0000
cherry-ignore: add ANV fast clears related fixes
There is no ANV fast_clear support in branch.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 7a61b80..ef4ea2e 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -22,3 +22,7 @@ b18cd8ce2c07c2d1a666fbff1f0d92d17dd5b22c i965/miptree: Use intel_miptree_copy fo
# The optimisation itself is broken and was removed completely
a4393bd97fe62e8299273bae769201c5c9c816ea i965/fs: Fix the inline nir_op_pack_double optimization
+
+# There is no ANV fast_clear support in branch
+42b10b175d5e8dfb9c4c46edbc306e7fac6bd3ec anv/blorp/clear_subpass: Only set surface clear color for fast clears
+6b644e571e2344691e4d58ff0bba3ddc059c1a5d anv: Stall before fast-clear operations
commit 56044c43a8af643d5bb91b5069895974667fab66
Author: Ben Crocker <bcrocker@redhat.com>
Date: Wed Jan 18 20:44:09 2017 -0500
gallivm: Reenable PPC VSX (v3)
Reenable the PPC64LE Vector-Scalar Extension for LLVM versions >= 3.8.1,
now that LLVM bug 26775 and its corollary, 25503, are fixed.
Amendment: remove extraneous spaces in macro def & invocations.
We would prefer a runtime check, e.g. via an LLVMQueryString
(analogous to glGetString, eglQueryString) or LLVMGetVersion API,
but no such API exists at this time.
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
[Emil Velikov: remove LLVM_VERSION macro]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 3f1b6ef2aa9c99bebe539f1de5a5054d90fc5dc3)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index 9b61955..3efb6a8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -597,7 +597,8 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
#if defined(PIPE_ARCH_PPC)
MAttrs.push_back(util_cpu_caps.has_altivec ? "+altivec" : "-altivec");
-#if HAVE_LLVM >= 0x0304
+#if (HAVE_LLVM >= 0x0304)
+#if (HAVE_LLVM <= 0x0307) || (HAVE_LLVM == 0x0308 && MESA_LLVM_VERSION_PATCH == 0)
/*
* Make sure VSX instructions are disabled
* See LLVM bug https://llvm.org/bugs/show_bug.cgi?id=25503#c7
@@ -605,6 +606,17 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
if (util_cpu_caps.has_altivec) {
MAttrs.push_back("-vsx");
}
+#else
+ /*
+ * However, bug 25503 is fixed, by the same fix that fixed
+ * bug 26775, in versions of LLVM later than 3.8 (starting with 3.8.1):
+ * Make sure VSX instructions are ENABLED
+ * See LLVM bug https://llvm.org/bugs/show_bug.cgi?id=26775
+ */
+ if (util_cpu_caps.has_altivec) {
+ MAttrs.push_back("+vsx");
+ }
+#endif
#endif
#endif
commit 5e5c720c6a7dcb0fa016ffcae0a4bbcaa30ded13
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Wed Mar 1 11:09:30 2017 -0500
nvc0: increase alignment to 256 for texture buffers on fermi
When binding as textures, the alignment can be 16. However when binding
as an image, the address has to be aligned to 256. (Also when binding as
an RT, but that can't happen with GL or current gallium APIs.)
Reported-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 32dd8d59b6d1b6828e16e854d589d0f04536da14)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 2cac3c7..2ef09dc 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -147,7 +147,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 16; /* 256 for binding as RT, but that's not possible in GL */
+ if (class_3d < NVE4_3D_CLASS)
+ return 256; /* IMAGE bindings require alignment to 256 */
+ return 16;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 16;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
commit f42e8a76e5a45c23ea3de392138257a346be14c9
Author: Gregory Hainaut <gregory.hainaut@gmail.com>
Date: Mon Mar 6 15:25:32 2017 +1100
glapi: fix typo in count_scale
2*4=8
Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 2ab5eccf5de4a68d0d8d2668f6c5244cc6a41846)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 00c9bb7..2ab0672 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -5858,7 +5858,7 @@
<param name="location" type="GLint"/>
<param name="count" type="GLsizei" counter="true"/>
<param name="transpose" type="GLboolean"/>
- <param name="value" type="const GLfloat *" count="count" count_scale="6"/>
+ <param name="value" type="const GLfloat *" count="count" count_scale="8"/>
<glx ignore="true"/>
</function>
<function name="UniformMatrix4x2fv" es2="3.0">
commit d348151c9990f7558efc2b0d6ae42e2673bbef6d
Author: Grazvydas Ignotas <notasas@gmail.com>
Date: Sun Feb 26 02:44:07 2017 +0200
gallium/u_queue: set num_threads correctly if not all threads start
If i-th thread could not be created it means we have i threads,
not i+1, because we start from 0.
Fixes: 404d0d5 "gallium/u_queue: add an option to have multiple worker threads"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 7f268cf12b39d1de8ff38cf5beea50298cf841c2)
diff --git a/src/gallium/auxiliary/util/u_queue.c b/src/gallium/auxiliary/util/u_queue.c
index d0b1378..643c92b 100644
--- a/src/gallium/auxiliary/util/u_queue.c
+++ b/src/gallium/auxiliary/util/u_queue.c
@@ -215,7 +215,7 @@ util_queue_init(struct util_queue *queue,
goto fail;
} else {
/* at least one thread created, so use it */
- queue->num_threads = i+1;
+ queue->num_threads = i;
break;
}
}
commit ce5770728a6c16c4190c070f9d97a33447a301d9
Author: Grazvydas Ignotas <notasas@gmail.com>
Date: Sun Feb 26 02:44:06 2017 +0200
gallium/u_queue: fix a crash with atexit handlers
Commit 4aea8fe ("gallium/u_queue: fix random crashes when the app calls
exit()") added a atexit handler which calls
util_queue_killall_and_wait() for each queue to stop the threads.
However the app is also free to use atexit handlers to clean up things,
leading to util_queue_destroy() call which will also call
util_queue_killall_and_wait() for the same queue again, causing threads
being joined twice, and that is undefined. This happens with libglut,
for example. A simple fix is to just set num_threads to 0 as there are
no more valid threads after util_queue_killall_and_wait() returns.
Fixes: 4aea8fe "gallium/u_queue: fix random crashes when the app calls exit()"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 993612193575f5f218af52c4ed7525e15083548e)
diff --git a/src/gallium/auxiliary/util/u_queue.c b/src/gallium/auxiliary/util/u_queue.c
index 7ecee41..d0b1378 100644
--- a/src/gallium/auxiliary/util/u_queue.c
+++ b/src/gallium/auxiliary/util/u_queue.c
@@ -251,6 +251,7 @@ util_queue_killall_and_wait(struct util_queue *queue)
for (i = 0; i < queue->num_threads; i++)
pipe_thread_wait(queue->threads[i]);
+ queue->num_threads = 0;
}
void
commit 0d8d249f082f8e76cfeac2c294c336aaacd59d49
Author: Grazvydas Ignotas <notasas@gmail.com>
Date: Sat Feb 11 01:01:40 2017 +0200
r300g: only allow byteswapped formats on big endian
They cause regressions on little endian.
Fixes: 172bfdaa9e ("r300g: add support for PIPE_FORMAT_x8R8G8B8_*")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98869
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 66d1cb587ac7b24fb04f26d30e686c3991fc8885)
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index fbac07a..929c3fe 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -47,6 +47,11 @@
*/
static enum pipe_format r300_unbyteswap_array_format(enum pipe_format format)
{
+ /* FIXME: Disabled on little endian because of a reported regression:
+ * https://bugs.freedesktop.org/show_bug.cgi?id=98869 */
+ if (PIPE_ENDIAN_NATIVE != PIPE_ENDIAN_BIG)
+ return format;
+
/* Only BGRA 8888 array formats are supported for simplicity of
* the implementation. */
switch (format) {
commit c0c964489b129d71f23052c6fa4c858b9bc16b32
Author: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue Feb 28 20:30:57 2017 -0800
vulkan/wsi: Improve the DRI3 error message
This commit improves the message by telling them that they could probably
enable DRI3. More importantly, it includes a little heuristic to check
to see if we're running on AMD or NVIDIA's proprietary X11 drivers and,
if we are, doesn't emit the warning. This way, users with both a discrete
card and Intel graphics don't get the warning when they're just running
on the discrete card.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99715
Co-authored-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Rene Lindsay <rjklindsay@hotmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Cc: "17.0" <mesa-dev@lists.freedesktop.org>
(cherry picked from commit 3d8feb38e8fdbc05b591164cb934b48a495adfbc)
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index ae5ffed..e7bb6f7 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -49,6 +49,7 @@
struct wsi_x11_connection {
bool has_dri3;
bool has_present;
+ bool is_proprietary_x11;
};
struct wsi_x11 {
@@ -63,8 +64,8 @@ static struct wsi_x11_connection *
wsi_x11_connection_create(const VkAllocationCallbacks *alloc,
xcb_connection_t *conn)
{
- xcb_query_extension_cookie_t dri3_cookie, pres_cookie;
- xcb_query_extension_reply_t *dri3_reply, *pres_reply;
+ xcb_query_extension_cookie_t dri3_cookie, pres_cookie, amd_cookie, nv_cookie;
+ xcb_query_extension_reply_t *dri3_reply, *pres_reply, *amd_reply, *nv_reply;
struct wsi_x11_connection *wsi_conn =
vk_alloc(alloc, sizeof(*wsi_conn), 8,
@@ -75,20 +76,43 @@ wsi_x11_connection_create(const VkAllocationCallbacks *alloc,
dri3_cookie = xcb_query_extension(conn, 4, "DRI3");
pres_cookie = xcb_query_extension(conn, 7, "PRESENT");
+ /* We try to be nice to users and emit a warning if they try to use a
+ * Vulkan application on a system without DRI3 enabled. However, this ends
+ * up spewing the warning when a user has, for example, both Intel
+ * integrated graphics and a discrete card with proprietary drivers and are
+ * running on the discrete card with the proprietary DDX. In this case, we
+ * really don't want to print the warning because it just confuses users.
+ * As a heuristic to detect this case, we check for a couple of proprietary
+ * X11 extensions.
+ */
+ amd_cookie = xcb_query_extension(conn, 11, "ATIFGLRXDRI");
+ nv_cookie = xcb_query_extension(conn, 10, "NV-CONTROL");
+
dri3_reply = xcb_query_extension_reply(conn, dri3_cookie, NULL);
pres_reply = xcb_query_extension_reply(conn, pres_cookie, NULL);
- if (dri3_reply == NULL || pres_reply == NULL) {
+ amd_reply = xcb_query_extension_reply(conn, amd_cookie, NULL);
+ nv_reply = xcb_query_extension_reply(conn, nv_cookie, NULL);
+ if (!dri3_reply || !pres_reply) {
free(dri3_reply);
free(pres_reply);
+ free(amd_reply);
+ free(nv_reply);
vk_free(alloc, wsi_conn);
return NULL;
}
wsi_conn->has_dri3 = dri3_reply->present != 0;
wsi_conn->has_present = pres_reply->present != 0;
+ wsi_conn->is_proprietary_x11 = false;
+ if (amd_reply && amd_reply->present)
+ wsi_conn->is_proprietary_x11 = true;
+ if (nv_reply && nv_reply->present)
+ wsi_conn->is_proprietary_x11 = true;
free(dri3_reply);
free(pres_reply);
+ free(amd_reply);
+ free(nv_reply);
return wsi_conn;
}
@@ -100,6 +124,18 @@ wsi_x11_connection_destroy(const VkAllocationCallbacks *alloc,
vk_free(alloc, conn);
}
+static bool
+wsi_x11_check_for_dri3(struct wsi_x11_connection *wsi_conn)
+{
+ if (wsi_conn->has_dri3)
+ return true;
+ if (!wsi_conn->is_proprietary_x11) {
+ fprintf(stderr, "vulkan: No DRI3 support detected - required for presentation\n"
+ "Note: you can probably enable DRI3 in your Xorg config\n");
+ }
+ return false;
+}
+
static struct wsi_x11_connection *
wsi_x11_get_connection(struct wsi_device *wsi_dev,
const VkAllocationCallbacks *alloc,
@@ -264,11 +300,8 @@ VkBool32 wsi_get_physical_device_xcb_presentation_support(
if (!wsi_conn)
return false;
- if (!wsi_conn->has_dri3) {
- fprintf(stderr, "vulkan: No DRI3 support detected - required for presentation\n");
- fprintf(stderr, "Note: Buggy applications may crash, if they do please report to vendor\n");
+ if (!wsi_x11_check_for_dri3(wsi_conn))
return false;
- }
unsigned visual_depth;
if (!connection_get_visualtype(connection, visual_id, &visual_depth))
@@ -313,9 +346,7 @@ x11_surface_get_support(VkIcdSurfaceBase *icd_surface,
if (!wsi_conn)
return VK_ERROR_OUT_OF_HOST_MEMORY;
- if (!wsi_conn->has_dri3) {
- fprintf(stderr, "vulkan: No DRI3 support detected - required for presentation\n");
- fprintf(stderr, "Note: Buggy applications may crash, if they do please report to vendor\n");
+ if (!wsi_x11_check_for_dri3(wsi_conn)) {
*pSupported = false;
return VK_SUCCESS;
}
commit 010f672d103c919a606d162e5581f1b7ba18d3b5
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed Mar 1 08:39:49 2017 -0800
anv: Properly handle destroying NULL devices and instances
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.0 13.0" <mesa-dev@lists.freedesktop.org>
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