mesa: Changes to 'debian-experimental'
VERSION | 2
configure.ac | 16
debian/changelog | 20 +
debian/control | 2
debian/libglx-mesa0.links.in | 1
docs/specs/enums.txt | 26 -
meson.build | 2
src/Makefile.am | 2
src/amd/vulkan/radv_cmd_buffer.c | 2
src/amd/vulkan/radv_descriptor_set.c | 55 +++
src/amd/vulkan/radv_device.c | 32 +
src/broadcom/compiler/v3d_compiler.c | 43 --
src/compiler/glsl/ast_to_hir.cpp | 2
src/compiler/glsl/link_atomics.cpp | 4
src/compiler/glsl/link_uniforms.cpp | 17 -
src/compiler/glsl/link_varyings.cpp | 24 -
src/compiler/glsl/linker.cpp | 168 ++++++----
src/compiler/glsl/shader_cache.cpp | 6
src/compiler/nir/nir.h | 1
src/compiler/nir/nir_print.c | 2
src/compiler/spirv/spirv_to_nir.c | 12
src/compiler/spirv/vtn_private.h | 1
src/compiler/spirv/vtn_variables.c | 1
src/egl/drivers/dri2/platform_wayland.c | 32 +
src/gallium/auxiliary/tgsi/tgsi_exec.c | 2
src/gallium/drivers/r600/r600_shader.c | 13
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl | 12
src/gallium/drivers/swr/rasterizer/common/simdlib_512_emu.inl | 34 --
src/gallium/drivers/vc5/Makefile.sources | 1
src/gallium/targets/opencl/Makefile.am | 2
src/glx/dri3_glx.c | 3
src/glx/drisw_glx.c | 6
src/intel/Makefile.am | 3
src/intel/Makefile.common.am | 2
src/intel/blorp/blorp.h | 7
src/intel/blorp/blorp_genX_exec.h | 20 -
src/intel/compiler/brw_fs.cpp | 94 +++--
src/intel/compiler/brw_fs_generator.cpp | 75 ++--
src/intel/compiler/brw_fs_nir.cpp | 128 ++++++-
src/intel/compiler/brw_fs_visitor.cpp | 60 +--
src/intel/compiler/brw_nir.c | 63 ++-
src/intel/compiler/brw_nir.h | 4
src/intel/compiler/brw_reg.h | 16
src/intel/tools/aubinator_error_decode.c | 2
src/intel/vulkan/anv_blorp.c | 68 ++--
src/intel/vulkan/genX_blorp_exec.c | 1
src/intel/vulkan/genX_cmd_buffer.c | 11
src/loader/loader_dri3_helper.c | 77 +++-
src/loader/loader_dri3_helper.h | 10
src/mesa/drivers/dri/i965/brw_blorp.c | 32 +
src/mesa/drivers/dri/i965/brw_context.c | 1
src/mesa/drivers/dri/i965/brw_defines.h | 2
src/mesa/drivers/dri/i965/brw_draw.c | 4
src/mesa/drivers/dri/i965/brw_link.cpp | 43 --
src/mesa/drivers/dri/i965/brw_misc_state.c | 9
src/mesa/drivers/dri/i965/brw_pipe_control.c | 52 ++-
src/mesa/drivers/dri/i965/brw_state.h | 1
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 -
src/mesa/drivers/dri/i965/gen7_l3_state.c | 2
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 10
src/mesa/drivers/dri/i965/genX_state_upload.c | 2
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4
src/mesa/drivers/dri/i965/intel_blit.c | 15
src/mesa/main/mtypes.h | 7
src/mesa/main/shaderobj.c | 60 ---
src/mesa/main/shaderobj.h | 3
src/mesa/program/ir_to_mesa.cpp | 2
67 files changed, 895 insertions(+), 562 deletions(-)
New commits:
commit a989b66605d31c066c6262774ba04aee50eadc3a
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Tue Nov 21 11:45:22 2017 +0100
Upload to experimental.
diff --git a/debian/changelog b/debian/changelog
index 4015cb6..cd3fca0 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,8 @@
-mesa (17.3.0~rc5-1) UNRELEASED; urgency=medium
+mesa (17.3.0~rc5-1) experimental; urgency=medium
* New upstream release candidate.
- -- Andreas Boll <andreas.boll.dev@gmail.com> Tue, 21 Nov 2017 11:07:51 +0100
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Tue, 21 Nov 2017 11:44:37 +0100
mesa (17.3.0~rc3-1) experimental; urgency=medium
commit 94b40609fb156092f785daa417e13a7f3d487c2d
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Tue Nov 21 11:08:05 2017 +0100
Bump changelog
diff --git a/debian/changelog b/debian/changelog
index c1e5d9e..4015cb6 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.3.0~rc5-1) UNRELEASED; urgency=medium
+
+ * New upstream release candidate.
+
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Tue, 21 Nov 2017 11:07:51 +0100
+
mesa (17.3.0~rc3-1) experimental; urgency=medium
[ Andreas Boll ]
commit d1e6cf4639cd771c5896fb82d549cf5c5681a9f8
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Nov 20 13:59:12 2017 +0000
Update version to 17.3.0-rc5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index fac25a5..de21bbd 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.3.0-rc4
+17.3.0-rc5
commit 7bc213a6446e32143e3b478857d23c82d05c3f1d
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Nov 16 22:31:27 2017 -0800
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
This apparently causes hangs on Broadwell, so let's back it out for now.
I think there are other PIPE_CONTROL workarounds that we're missing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
(cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index eec4e72..3013b6a 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -115,7 +115,7 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
brw_emit_pipe_control_flush(brw, 0);
}
- if (devinfo->gen >= 8) {
+ if (devinfo->gen >= 9) {
/* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue:
*
* "Project: BDW+
@@ -126,6 +126,10 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
*
* If there's a BO, we're already doing some kind of write.
* If not, add a write to the workaround BO.
+ *
+ * XXX: This causes GPU hangs on Broadwell, so restrict it to
+ * Gen9+ for now...see this bug for more information:
+ * https://bugs.freedesktop.org/show_bug.cgi?id=103787
*/
if (!bo) {
flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
commit 093ae29b3cd3a5ed243257e42a83e736a2f2d3bc
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sat Nov 11 11:52:41 2017 -0800
anv/cmd_buffer: Take bo_offset into account in fast clear state addresses
Otherwise, if the image is not bound to the start of the buffer, we're
going to be reading and writing its fast clear state in the wrong spot.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit a07f7b26198ce0f5c8799481a673754968ac5daf)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 7850793..15691aa 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -461,7 +461,7 @@ get_fast_clear_state_address(const struct anv_device *device,
return (struct anv_address) {
.bo = image->planes[plane].bo,
- .offset = offset,
+ .offset = image->planes[plane].bo_offset + offset,
};
}
commit d2d5439412302de14627682f87b5bc0c71d074f1
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sat Nov 11 22:03:45 2017 -0800
anv/cmd_buffer: Advance the address when initializing clear colors
Found by inspection
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit a6cc361e5fd2450249847d5ee8093d26ed7ff545)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 20a885c..7850793 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -557,12 +557,13 @@ init_fast_clear_state_entry(struct anv_cmd_buffer *cmd_buffer,
/* Other combinations of auxiliary buffers and platforms require specific
* values in the clear value dword(s).
*/
+ struct anv_address addr =
+ get_fast_clear_state_address(cmd_buffer->device, image, aspect, level,
+ FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
unsigned i = 0;
for (; i < cmd_buffer->device->isl_dev.ss.clear_value_size; i += 4) {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
- sdi.Address =
- get_fast_clear_state_address(cmd_buffer->device, image, aspect, level,
- FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
+ sdi.Address = addr;
if (GEN_GEN >= 9) {
/* MCS buffers on SKL+ can only have 1/0 clear colors. */
@@ -586,6 +587,8 @@ init_fast_clear_state_entry(struct anv_cmd_buffer *cmd_buffer,
sdi.ImmediateData = 0;
}
}
+
+ addr.offset += 4;
}
}
commit b3bc46f1c74b5d8ed46e827b4d0b2957f0c9d74a
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Thu Nov 9 11:30:10 2017 -0800
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_blit.c
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index c9b2593..eec4e72 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -463,11 +463,14 @@ brw_emit_mi_flush(struct brw_context *brw)
const struct gen_device_info *devinfo = &brw->screen->devinfo;
if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
- BEGIN_BATCH_BLT(4);
- OUT_BATCH(MI_FLUSH_DW | (4 - 2));
+ const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
+ BEGIN_BATCH_BLT(n_dwords);
+ OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
+ if (n_dwords == 5)
+ OUT_BATCH(0);
ADVANCE_BATCH();
} else {
int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index b766f19..5f25bfa 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -102,14 +102,16 @@ set_blitter_tiling(struct brw_context *brw,
uint32_t *__map)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
-
+ const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
assert(devinfo->gen >= 6);
/* Idle the blitter before we update how tiling is interpreted. */
- OUT_BATCH(MI_FLUSH_DW | (4 - 2));
+ OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
+ if (n_dwords == 5)
+ OUT_BATCH(0);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(BCS_SWCTRL);
@@ -121,7 +123,14 @@ set_blitter_tiling(struct brw_context *brw,
#define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
- BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
+ unsigned set_tiling_batch_size = 0; \
+ if (dst_y_tiled || src_y_tiled) { \
+ if (devinfo->gen >= 8) \
+ set_tiling_batch_size = 16; \
+ else \
+ set_tiling_batch_size = 14; \
+ } \
+ BEGIN_BATCH_BLT(n + set_tiling_batch_size); \
if (dst_y_tiled || src_y_tiled) \
SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
commit bf0c7200bd46618e6bfda3e3e0ea85afb33fa6c0
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Fri Nov 10 14:39:17 2017 -0800
i965: Program DWord Length in MI_FLUSH_DW
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6)
Squashed with:
i965: Remove DWord length from MI_FLUSH_DW definition
Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 4abb790..6bd5c54 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1428,7 +1428,7 @@ enum brw_pixel_shader_coverage_mask_mode {
#define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
-#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2)
+#define MI_FLUSH_DW (CMD_MI | (0x26 << 23))
#define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
# define MI_STORE_REGISTER_MEM_USE_GGTT (1 << 22)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 7e0cd1d..c9b2593 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -464,7 +464,7 @@ brw_emit_mi_flush(struct brw_context *brw)
if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
BEGIN_BATCH_BLT(4);
- OUT_BATCH(MI_FLUSH_DW);
+ OUT_BATCH(MI_FLUSH_DW | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 819a3da..b766f19 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -106,7 +106,7 @@ set_blitter_tiling(struct brw_context *brw,
assert(devinfo->gen >= 6);
/* Idle the blitter before we update how tiling is interpreted. */
- OUT_BATCH(MI_FLUSH_DW);
+ OUT_BATCH(MI_FLUSH_DW | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
commit d38e92b6e9d74b35f4b65fb5839a002d68aa04e2
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Fri Nov 17 15:32:47 2017 +0000
meson: explicitly disable the build system for 17.3.x
This build system is rather incomplete in the 17.3 branch, with multiple
bugs and user facing changes already addressed in master.
It's not shipped in the tarball and we don't want to receive bug reports
about 17.3, 18.0 is the release that I hope to have the meson build in
shape for.
Simply error() out, if anyone tries to use it.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/meson.build b/meson.build
index 92b875b..f1a766f 100644
--- a/meson.build
+++ b/meson.build
@@ -21,6 +21,8 @@
project('mesa', ['c', 'cpp'], version : '17.3.0-devel', license : 'MIT',
default_options : ['c_std=c99', 'cpp_std=c++11'])
+error('The meson build is unsupported for building mesa 17.3.x releases.')
+
# Arguments for the preprocessor, put these in a separate array from the C and
# C++ (cpp in meson terminology) arguments since they need to be added to the
# default arguments for both C and C++.
commit 55c492132650599bf93c069f90c2f7255f95bb64
Author: Matt Turner <mattst88@gmail.com>
Date: Tue Nov 14 11:24:08 2017 -0800
Revert "intel/fs: Use a pure vertical stride for large register strides"
This reverts commit e8c9e65185de3e821e1e482e77906d1d51efa3ec.
With the actual bug fixed (by commit 6ac2d1690192), this is not
necessary. I'm doubtful of its correctness in any case.
(cherry picked from commit a31d0382084c8aa860ffcef9b12592c5c44e192f)
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 0521664..5a07736 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -90,19 +90,9 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
* different execution size when the number of components
* written to each destination GRF is not the same.
*/
- if (reg->stride > 4) {
- /* For registers with an exceptionally large stride, we use a
- * width of 1 and only use the vertical stride. This only works
- * for sources since destinations require hstride == 1.
- */
- assert(reg != &inst->dst);
- brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
- brw_reg = stride(brw_reg, reg->stride, 1, 0);
- } else {
- const unsigned width = MIN2(reg_width, phys_width);
- brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
- brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
- }
+ const unsigned width = MIN2(reg_width, phys_width);
+ brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
+ brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
if (devinfo->gen == 7 && !devinfo->is_haswell) {
/* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
commit 78a7e2a2d41e72ddfc4371ce70c1b52d1f9cf641
Author: Matt Turner <mattst88@gmail.com>
Date: Wed Nov 8 15:14:19 2017 -0800
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Fixes the following tests on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115
(cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 0c0912c..2efd1c4 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -635,8 +635,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
break;
case nir_op_f2f64:
+ case nir_op_f2i64:
+ case nir_op_f2u64:
case nir_op_i2f64:
+ case nir_op_i2i64:
case nir_op_u2f64:
+ case nir_op_u2u64:
/* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
*
* "When source or destination is 64b (...), regioning in Align1
@@ -664,12 +668,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_f2f32:
case nir_op_f2i32:
case nir_op_f2u32:
- case nir_op_f2i64:
- case nir_op_f2u64:
case nir_op_i2i32:
- case nir_op_i2i64:
case nir_op_u2u32:
- case nir_op_u2u64:
inst = bld.MOV(result, op[0]);
inst->saturate = instr->dest.saturate;
break;
commit 3be7bb6741222e1fab6a3a872acfd527acc14f11
Author: Matt Turner <mattst88@gmail.com>
Date: Fri Nov 10 14:00:24 2017 -0800
i965/fs: Fix extract_i8/u8 to a 64-bit destination
The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.
For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.
Fixes the following test on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 6ac2d16901927013393f873a34c717ece5014c1a)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index a1c3ee2..0c0912c 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1304,10 +1304,31 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_extract_u8:
case nir_op_extract_i8: {
- const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
assert(byte != NULL);
- bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+
+ /* The PRMs say:
+ *
+ * BDW+
+ * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
+ * Use two instructions and a word or DWord intermediate integer type.
+ */
+ if (nir_dest_bit_size(instr->dest.dest) == 64) {
+ const brw_reg_type type = brw_int_type(2, instr->op == nir_op_extract_i8);
+
+ if (instr->op == nir_op_extract_i8) {
+ /* If we need to sign extend, extract to a word first */
+ fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
+ bld.MOV(w_temp, subscript(op[0], type, byte->u32[0]));
+ bld.MOV(result, w_temp);
+ } else {
+ /* Otherwise use an AND with 0xff and a word type */
+ bld.AND(result, subscript(op[0], type, byte->u32[0] / 2), brw_imm_uw(0xff));
+ }
+ } else {
+ const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
+ bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+ }
break;
}
commit f539ea0e8bf87d5c0fc244e2a044e7a819025348
Author: Nicolai Hähnle <nicolai.haehnle@amd.com>
Date: Wed Nov 15 19:34:00 2017 +0100
tgsi/exec: fix LDEXP in softpipe
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103128
Fixes: cad959d90145 ("gallium: add LDEXP TGSI instruction and corresponding cap")
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit f3fa3b0d95c712c00318ca5601433bce1b82432d)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index afed96c..793c0da 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -5130,7 +5130,7 @@ exec_instruction(
break;
case TGSI_OPCODE_LDEXP:
- exec_scalar_binary(mach, inst, micro_ldexp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
+ exec_vector_binary(mach, inst, micro_ldexp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_COS:
commit e4f186d3aee41ee37e9d9196642275560ff0f178
Author: Derek Foreman <derekf@osg.samsung.com>
Date: Mon Oct 30 15:52:22 2017 -0500
egl/wayland: Add a fallback when fourcc query isn't supported
When queryImage doesn't support __DRI_IMAGE_ATTRIB_FOURCC wayland clients
will die with a NULL derefence in wl_proxy_add_listener.
Attempt to provide a simple fallback to keep ancient systems working.
Fixes: 6595c699511 ("egl/wayland: Remove more surface specifics from
create_wl_buffer")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103519
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 0db36caa192b129cb4f22d152f82f38fcf6f06d4)
Squashed with:
egl: fix var type
queryImage() takes an `int*`; compiler is warning about the
signed<->unsigned pointer mismatch.
Fixes: 0db36caa192b129cb4f2 "egl/wayland: Add a fallback when fourcc
query isn't supported"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Derek Foreman <derekf@osg.samsung.com>
(cherry picked from commit ca95d7ad4e1b900eb3d559ed5bda0b96b232961d)
diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c
index b38eb1c..b844df3 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -671,6 +671,35 @@ static const struct wl_callback_listener throttle_listener = {
.done = wayland_throttle_callback
};
+static EGLBoolean
+get_fourcc(struct dri2_egl_display *dri2_dpy,
+ __DRIimage *image, int *fourcc)
+{
+ EGLBoolean query;
+ int dri_format;
+
+ query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC,
+ fourcc);
+ if (query)
+ return true;
+
+ query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FORMAT,
+ &dri_format);
+ if (!query)
+ return false;
+
+ switch (dri_format) {
+ case __DRI_IMAGE_FORMAT_ARGB8888:
+ *fourcc = __DRI_IMAGE_FOURCC_ARGB8888;
+ return true;
+ case __DRI_IMAGE_FORMAT_XRGB8888:
+ *fourcc = __DRI_IMAGE_FOURCC_XRGB8888;
+ return true;
+ default:
+ return false;
+ }
+}
+
static struct wl_buffer *
create_wl_buffer(struct dri2_egl_display *dri2_dpy,
struct dri2_egl_surface *dri2_surf,
@@ -684,8 +713,7 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
query = dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_WIDTH, &width);
query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_HEIGHT,
&height);
- query &= dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FOURCC,
- &fourcc);
+ query &= get_fourcc(dri2_dpy, image, &fourcc);
if (!query)
return NULL;
commit 8269b7ec4b67623b70f0b4e13813c3843f15d3a5
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Mon Nov 13 23:26:32 2017 +0100
radv: Free temporary syncobj after waiting on it.
Otherwise we leak it.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 7c255788637b8fdfc31aca5f7891f39a110c5cb2)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 63129a1..7b75703 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1828,10 +1828,6 @@ static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
if (sem->temp_syncobj) {
counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
- if (reset_temp) {
- /* after we wait on a temp import - drop it */
- sem->temp_syncobj = 0;
- }
}
else if (sem->syncobj)
counts->syncobj[syncobj_idx++] = sem->syncobj;
@@ -1852,6 +1848,21 @@ void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
free(sem_info->signal.sem);
}
+
+static void radv_free_temp_syncobjs(struct radv_device *device,
+ int num_sems,
+ const VkSemaphore *sems)
+{
+ for (uint32_t i = 0; i < num_sems; i++) {
+ RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
+
+ if (sem->temp_syncobj) {
+ device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
+ sem->temp_syncobj = 0;
+ }
+ }
+}
+
VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
int num_wait_sems,
const VkSemaphore *wait_sems,
@@ -1990,6 +2001,9 @@ VkResult radv_QueueSubmit(
}
}
+ radv_free_temp_syncobjs(queue->device,
+ pSubmits[i].waitSemaphoreCount,
+ pSubmits[i].pWaitSemaphores);
radv_free_sem_info(&sem_info);
free(cs_array);
}
commit 577af89bd13e69541329136138a19e043bc63a17
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Mon Nov 13 23:18:19 2017 +0100
radv: Free syncobj with multiple imports.
Otherwise we can leak the old syncobj.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 917d3b43f2b206ccf036542aa1c39f1dbdd84f62)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index abdbdeb..63129a1 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3515,6 +3515,7 @@ VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
uint32_t syncobj_handle = 0;
+ uint32_t *syncobj_dst = NULL;
assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
@@ -3522,10 +3523,15 @@ VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
- sem->temp_syncobj = syncobj_handle;
+ syncobj_dst = &sem->temp_syncobj;
} else {
- sem->syncobj = syncobj_handle;
+ syncobj_dst = &sem->syncobj;
}
+
+ if (*syncobj_dst)
+ device->ws->destroy_syncobj(device->ws, *syncobj_dst);
+
+ *syncobj_dst = syncobj_handle;
close(pImportSemaphoreFdInfo->fd);
return VK_SUCCESS;
}
commit 040c0df11dbc43017700a15f94439bd49c5d26b7
Author: Thomas Hellstrom <thellstrom@vmware.com>
Date: Tue Sep 19 19:41:22 2017 +0200
loader/dri3: Improve dri3 thread-safety
It turned out that with recent changes that call into dri3 from glFinish(),
it appears like different thread end up waiting for X events simultaneously,
causing deadlocks since they steal events from eachoter and update the dri3
counters behind eachothers backs.
This patch intends to improve on that. It allows at most one thread at a
time to wait on events for a single drawable. If another thread intends to
do the same, it's put to sleep until the first thread finishes waiting, and
then it rechecks counters and optionally retries the waiting. Threads that
poll for X events never pulls X events off the event queue if there are
other threads waiting for events on that drawable. Counters in the
dri3 drawable structure are protected by a mutex. Finally, the mutex we
introduce is never held while waiting for the X server to avoid
unnecessary stalls.
This does not make dri3 drawables completely thread-safe but at least it's a
first step.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102358
Fixes: d5ba75f8881 "st/dri2 Plumb the flush_swapbuffer functionality through to dri3"
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 54a58b2856377e18ea6a42706bea0304a8d7845e)
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 19ab581..7e6b8b2 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -32,7 +32,6 @@
#include <X11/Xlib-xcb.h>
-#include <c11/threads.h>
#include "loader_dri3_helper.h"
/* From xmlpool/options.h, user exposed so should be stable */
@@ -186,8 +185,11 @@ dri3_fence_await(xcb_connection_t *c, struct loader_dri3_drawable *draw,
{
xcb_flush(c);
xshmfence_await(buffer->shm_fence);
- if (draw)
+ if (draw) {
+ mtx_lock(&draw->mtx);
dri3_flush_present_events(draw);
+ mtx_unlock(&draw->mtx);
+ }
}
static void
@@ -245,6 +247,9 @@ loader_dri3_drawable_fini(struct loader_dri3_drawable *draw)
xcb_discard_reply(draw->conn, cookie.sequence);
xcb_unregister_for_special_event(draw->conn, draw->special_event);
}
+
+ cnd_destroy(&draw->event_cnd);
+ mtx_destroy(&draw->mtx);
}
int
@@ -276,6 +281,8 @@ loader_dri3_drawable_init(xcb_connection_t *conn,
draw->cur_blit_source = -1;
draw->back_format = __DRI_IMAGE_FORMAT_NONE;
+ mtx_init(&draw->mtx, mtx_plain);
+ cnd_init(&draw->event_cnd);
if (draw->ext->config)
draw->ext->config->configQueryi(draw->dri_screen,
@@ -407,13 +414,27 @@ dri3_handle_present_event(struct loader_dri3_drawable *draw,
}
static bool
-dri3_wait_for_event(struct loader_dri3_drawable *draw)
+dri3_wait_for_event_locked(struct loader_dri3_drawable *draw)
{
xcb_generic_event_t *ev;
xcb_present_generic_event_t *ge;
xcb_flush(draw->conn);
- ev = xcb_wait_for_special_event(draw->conn, draw->special_event);
+
+ /* Only have one thread waiting for events at a time */
+ if (draw->has_event_waiter) {
+ cnd_wait(&draw->event_cnd, &draw->mtx);
+ /* Another thread has updated the protected info, so retest. */
+ return true;
+ } else {
+ draw->has_event_waiter = true;
+ /* Allow other threads access to the drawable while we're waiting. */
+ mtx_unlock(&draw->mtx);
+ ev = xcb_wait_for_special_event(draw->conn, draw->special_event);
+ mtx_lock(&draw->mtx);
+ draw->has_event_waiter = false;
+ cnd_broadcast(&draw->event_cnd);
+ }
if (!ev)
return false;
ge = (void *) ev;
@@ -442,19 +463,23 @@ loader_dri3_wait_for_msc(struct loader_dri3_drawable *draw,
divisor,
remainder);
+ mtx_lock(&draw->mtx);
xcb_flush(draw->conn);
/* Wait for the event */
if (draw->special_event) {
while ((int32_t) (msc_serial - draw->recv_msc_serial) > 0) {
- if (!dri3_wait_for_event(draw))
+ if (!dri3_wait_for_event_locked(draw)) {
+ mtx_unlock(&draw->mtx);
return false;
+ }
}
}
*ust = draw->notify_ust;
*msc = draw->notify_msc;
*sbc = draw->recv_sbc;
+ mtx_unlock(&draw->mtx);
return true;
}
@@ -476,17 +501,21 @@ loader_dri3_wait_for_sbc(struct loader_dri3_drawable *draw,
* swaps requested with glXSwapBuffersMscOML for that window have
* completed."
*/
+ mtx_lock(&draw->mtx);
if (!target_sbc)
target_sbc = draw->send_sbc;
while (draw->recv_sbc < target_sbc) {
- if (!dri3_wait_for_event(draw))
+ if (!dri3_wait_for_event_locked(draw)) {
+ mtx_unlock(&draw->mtx);
return 0;
+ }
}
*ust = draw->ust;
*msc = draw->msc;
*sbc = draw->recv_sbc;
+ mtx_unlock(&draw->mtx);
return 1;
}
@@ -499,16 +528,16 @@ static int
dri3_find_back(struct loader_dri3_drawable *draw)
{
int b;
- xcb_generic_event_t *ev;
- xcb_present_generic_event_t *ge;
- int num_to_consider = draw->num_back;
+ int num_to_consider;
+ mtx_lock(&draw->mtx);
/* Increase the likelyhood of reusing current buffer */
dri3_flush_present_events(draw);
/* Check whether we need to reuse the current back buffer as new back.
* In that case, wait until it's not busy anymore.
*/
+ num_to_consider = draw->num_back;
if (!loader_dri3_have_image_blit(draw) && draw->cur_blit_source != -1) {
num_to_consider = 1;
draw->cur_blit_source = -1;
@@ -521,15 +550,14 @@ dri3_find_back(struct loader_dri3_drawable *draw)
if (!buffer || !buffer->busy) {
draw->cur_back = id;
+ mtx_unlock(&draw->mtx);
return id;
}
}
- xcb_flush(draw->conn);
- ev = xcb_wait_for_special_event(draw->conn, draw->special_event);
- if (!ev)
+ if (!dri3_wait_for_event_locked(draw)) {
+ mtx_unlock(&draw->mtx);
return -1;
- ge = (void *) ev;
- dri3_handle_present_event(draw, ge);
+ }
}
}
@@ -745,6 +773,9 @@ dri3_flush_present_events(struct loader_dri3_drawable *draw)
/* Check to see if any configuration changes have occurred
* since we were last invoked
*/
+ if (draw->has_event_waiter)
+ return;
+
if (draw->special_event) {
xcb_generic_event_t *ev;
@@ -774,6 +805,7 @@ loader_dri3_swap_buffers_msc(struct loader_dri3_drawable *draw,
back = dri3_find_back_alloc(draw);
+ mtx_lock(&draw->mtx);
if (draw->is_different_gpu && back) {
/* Update the linear buffer before presenting the pixmap */
(void) loader_dri3_blit_image(draw,
@@ -893,6 +925,7 @@ loader_dri3_swap_buffers_msc(struct loader_dri3_drawable *draw,
if (draw->stamp)
++(*draw->stamp);
}
+ mtx_unlock(&draw->mtx);
draw->ext->flush->invalidate(draw->dri_drawable);
@@ -903,11 +936,14 @@ int
loader_dri3_query_buffer_age(struct loader_dri3_drawable *draw)
{
struct loader_dri3_buffer *back = dri3_find_back_alloc(draw);
+ int ret;
- if (!back || back->last_swap == 0)
- return 0;
+ mtx_lock(&draw->mtx);
+ ret = (!back || back->last_swap == 0) ? 0 :
+ draw->send_sbc - back->last_swap + 1;
+ mtx_unlock(&draw->mtx);
- return draw->send_sbc - back->last_swap + 1;
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