mesa: Changes to 'debian-unstable'
VERSION | 2
bin/.cherry-ignore | 28 +++-
debian/changelog | 7 -
docs/relnotes/17.2.4.html | 3
docs/relnotes/17.2.5.html | 155 +++++++++++++++++++++++
src/amd/common/ac_surface.c | 37 +++++
src/amd/vulkan/radv_cmd_buffer.c | 2
src/amd/vulkan/radv_descriptor_set.c | 55 +++++++-
src/amd/vulkan/radv_device.c | 135 ++++++++++++--------
src/amd/vulkan/radv_pipeline.c | 24 +++
src/amd/vulkan/radv_private.h | 3
src/amd/vulkan/radv_wsi.c | 16 ++
src/compiler/glsl/linker.cpp | 14 +-
src/compiler/nir/nir_opt_intrinsics.c | 24 +++
src/compiler/spirv/spirv_to_nir.c | 3
src/gallium/drivers/i915/i915_state_derived.c | 17 ++
src/gallium/drivers/i915/i915_state_dynamic.c | 3
src/gallium/drivers/i915/i915_state_immediate.c | 6
src/gallium/drivers/i915/i915_state_static.c | 2
src/gallium/drivers/r600/sb/sb_sched.cpp | 43 ++++--
src/gallium/drivers/r600/sb/sb_sched.h | 8 -
src/gallium/drivers/radeon/radeon_video.c | 5
src/gallium/drivers/vc4/vc4_cl.h | 12 -
src/gallium/state_trackers/dri/dri2.c | 8 -
src/intel/compiler/brw_fs.cpp | 29 ++++
src/mesa/drivers/dri/i965/brw_blorp.c | 26 +--
src/mesa/drivers/dri/i965/brw_context.c | 6
src/mesa/drivers/dri/i965/brw_draw.c | 13 +
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 17 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 50 +++++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 -
src/mesa/main/fbobject.c | 9 +
32 files changed, 623 insertions(+), 148 deletions(-)
New commits:
commit 95118e2ead3d6c1a7d80733577f0c48cb091bd40
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Fri Nov 17 10:46:56 2017 +0100
Upload to unstable.
diff --git a/debian/changelog b/debian/changelog
index c839f69..a7cf535 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (17.2.5-1) UNRELEASED; urgency=medium
+mesa (17.2.5-1) unstable; urgency=medium
[ Emilio Pozuelo Monfort ]
* Make mesa-va-drivers enhance libva2 rather than libva1 (Closes: #881374).
@@ -10,7 +10,7 @@ mesa (17.2.5-1) UNRELEASED; urgency=medium
[ Andreas Boll ]
* New upstream release.
- -- Andreas Boll <andreas.boll.dev@gmail.com> Fri, 17 Nov 2017 10:11:03 +0100
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Fri, 17 Nov 2017 10:46:35 +0100
mesa (17.2.4-1) unstable; urgency=medium
commit 70df5104827629f3d5b6e448c590610bc2af7f00
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Fri Nov 17 10:11:29 2017 +0100
Bump changelog
diff --git a/debian/changelog b/debian/changelog
index 1ac9b4f..c839f69 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (17.2.4-2) UNRELEASED; urgency=medium
+mesa (17.2.5-1) UNRELEASED; urgency=medium
[ Emilio Pozuelo Monfort ]
* Make mesa-va-drivers enhance libva2 rather than libva1 (Closes: #881374).
@@ -7,7 +7,10 @@ mesa (17.2.4-2) UNRELEASED; urgency=medium
* libglx-mesa0.links.in: Add libGLX_indirect.so.0 to link against
libGLX_mesa so that GLX with a remote xserver works. (Closes: #881789)
- -- Emilio Pozuelo Monfort <pochu@debian.org> Sun, 05 Nov 2017 01:44:41 +0100
+ [ Andreas Boll ]
+ * New upstream release.
+
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Fri, 17 Nov 2017 10:11:03 +0100
mesa (17.2.4-1) unstable; urgency=medium
commit ae52410bf08aa9c054651258f2fd0d0a2c9c5241
Author: Andres Gomez <agomez@igalia.com>
Date: Fri Nov 10 15:33:58 2017 +0200
docs: add release notes for 17.2.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/docs/relnotes/17.2.5.html b/docs/relnotes/17.2.5.html
new file mode 100644
index 0000000..282e200
--- /dev/null
+++ b/docs/relnotes/17.2.5.html
@@ -0,0 +1,155 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.2.5 Release Notes / November 10, 2017</h1>
+
+<p>
+Mesa 17.2.5 is a bug fix release which fixes bugs found since the 17.2.4 release.
+</p>
+<p>
+Mesa 17.2.5 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97532";>Bug 97532</a> - Regression: GLB 2.7 & Glmark-2 GLES versions segfault due to linker precision error (259fc505) on dead variable</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102680";>Bug 102680</a> - [OpenGL CTS] KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102809";>Bug 102809</a> - Rust shadows(?) flash random colours</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103142";>Bug 103142</a> - R600g+sb: optimizer apparently stuck in an endless loop</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+<p>Andres Gomez (8):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.2.4</li>
+ <li>cherry-ignore: radv: copy indirect lowering settings from radeonsi</li>
+ <li>cherry-ignore: i965: fix blorp stage_prog_data->param leak</li>
+ <li>cherry-ignore: etnaviv: don't do resolve-in-place without valid TS</li>
+ <li>cherry-ignore: intel/fs: Alloc pull constants off mem_ctx</li>
+ <li>cherry-ignore: added 17.3 nominations.</li>
+ <li>cherry-ignore: automake: include git_sha1.h.in in release tarball</li>
+ <li>Update version to 17.2.5</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+ <li>radv: Don't expose heaps with 0 memory.</li>
+ <li>radv: Don't use vgpr indexing for outputs on GFX9.</li>
+ <li>radv: Disallow indirect outputs for GS on GFX9 as well.</li>
+</ul>
+
+<p>Dave Airlie (3):</p>
+<ul>
+ <li>i915g: make gears run again.</li>
+ <li>radv: free attachments on end command buffer.</li>
+ <li>radv: add initial copy descriptor support. (v2)</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+ <li>vc4: fix release build</li>
+</ul>
+
+<p>Gert Wollny (1):</p>
+<ul>
+ <li>r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling</li>
+</ul>
+
+<p>Jason Ekstrand (4):</p>
+<ul>
+ <li>spirv: Claim support for the simple memory model</li>
+ <li>i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees</li>
+ <li>i965/blorp: Use more temporary isl_format variables</li>
+ <li>i965/miptree: Take an isl_format in render_aux_usage</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.</li>
+</ul>
+
+<p>Leo Liu (1):</p>
+<ul>
+ <li>radeon/video: add gfx9 offsets when rejoin the video surface</li>
+</ul>
+
+<p>Marek Olšák (2):</p>
+<ul>
+ <li>st/dri: don't expose modifiers in EGL if the driver doesn't implement them</li>
+ <li>ac/surface/gfx9: don't allow DCC for the smallest mipmap levels</li>
+</ul>
+
+<p>Nanley Chery (1):</p>
+<ul>
+ <li>i965: Check CCS_E compatibility for texture view rendering</li>
+</ul>
+
+<p>Neil Roberts (1):</p>
+<ul>
+ <li>nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+ <li>amd/common/gfx9: workaround DCC corruption more conservatively</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+ <li>i965: unref push_const_bo in intelDestroyContext</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+ <li>radv: copy indirect lowering settings from radeonsi</li>
+</ul>
+
+<p>Tomasz Figa (1):</p>
+<ul>
+ <li>glsl: Allow precision mismatch on dead data with GLSL ES 1.00</li>
+</ul>
+
+<p>Topi Pohjolainen (1):</p>
+<ul>
+ <li>intel/compiler/gen9: Pixel shader header only workaround</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 2c582b4cf72e9e0c48e55b26a269316ca9207dfa
Author: Andres Gomez <agomez@igalia.com>
Date: Fri Nov 10 15:24:51 2017 +0200
Update version to 17.2.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/VERSION b/VERSION
index 97dbfc8..61d7548 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.2.4
+17.2.5
commit 0195b78aa74f7c133519a26160d47365e64b68be
Author: Andres Gomez <agomez@igalia.com>
Date: Tue Nov 7 12:49:54 2017 +0200
cherry-ignore: automake: include git_sha1.h.in in release tarball
fixes: This commit has more than one Fixes tag but the commit it
addresses didn't land in branch.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 8d6a32f..7735431 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -80,3 +80,7 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# stable: 17.3 nomination only.
7dae419aa7c34af820c08896acef3b65d855188e Android: move drivers' symlinks to /vendor (v2)
+
+# fixes: This commit has more than one Fixes tag but the commit it
+# addresses didn't land in branch.
+e17e8934f9e4b008bdfb4f9abd8ed4faa604c7d9 automake: include git_sha1.h.in in release tarball
commit a23bd4ea8789e060b41292325f92d198001ea036
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Nov 1 11:24:12 2017 +0200
cherry-ignore: added 17.3 nominations.
stable: 17.3 nominations only.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 35ee870..8d6a32f 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -74,3 +74,9 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# stable: This commit addressed earlier commit 8d90e28839 which did
# not land in branch.
7b4387519c382cffef9c62bbbbefcfe71cfde905 intel/fs: Alloc pull constants off mem_ctx
+
+# stable: 17.3 nomination only.
+3f8e3c2bd8f54ae6817f7496be47f4e1a8860d9c radeonsi: add a workaround for weird s_buffer_load_dword behavior on SI
+
+# stable: 17.3 nomination only.
+7dae419aa7c34af820c08896acef3b65d855188e Android: move drivers' symlinks to /vendor (v2)
commit 27cd0abe8e171b254471888455f5eb21ae6f51d0
Author: Andres Gomez <agomez@igalia.com>
Date: Fri Nov 3 14:53:31 2017 +0200
cherry-ignore: intel/fs: Alloc pull constants off mem_ctx
stable: This commit addressed earlier commit 8d90e28839 which did not
land in branch.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index a6af29a..35ee870 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -70,3 +70,7 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# stable: This commit addressed earlier commit 78ade659569 which did
# not land in branch.
8fbd82f464f26a56167f7962174b2b69756a105a etnaviv: don't do resolve-in-place without valid TS
+
+# stable: This commit addressed earlier commit 8d90e28839 which did
+# not land in branch.
+7b4387519c382cffef9c62bbbbefcfe71cfde905 intel/fs: Alloc pull constants off mem_ctx
commit b5dc8c43aa3d14642bac3502b685c41969b08f00
Author: Andres Gomez <agomez@igalia.com>
Date: Fri Nov 3 15:17:15 2017 +0200
cherry-ignore: etnaviv: don't do resolve-in-place without valid TS
stable: This commit addressed earlier commit 78ade659569 which did not
land in branch.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 7765df2..a6af29a 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -66,3 +66,7 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# stable: This commit addressed earlier commit 8d90e28839 which did
# not land in branch.
446c5726ecb968d06a6607e0df42be1cb74948c4 i965: fix blorp stage_prog_data->param leak
+
+# stable: This commit addressed earlier commit 78ade659569 which did
+# not land in branch.
+8fbd82f464f26a56167f7962174b2b69756a105a etnaviv: don't do resolve-in-place without valid TS
commit 526ecbe4176e01f5b353df05ed0773e1198606bf
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Nov 1 13:00:47 2017 +0200
cherry-ignore: i965: fix blorp stage_prog_data->param leak
stable: This commit addressed earlier commit 8d90e28839 which did not
land in branch.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 3a26997..7765df2 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -62,3 +62,7 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# extra: Commit is not applicable when ade416d0236 is missing.
07bfdb478bf844a0ac9cf3679f51f83c4abea5a1 broadcom/vc5: Propagate vc4 aliasing fix to vc5.
+
+# stable: This commit addressed earlier commit 8d90e28839 which did
+# not land in branch.
+446c5726ecb968d06a6607e0df42be1cb74948c4 i965: fix blorp stage_prog_data->param leak
commit 0d91d135649e6b0665c39866512cdbb7cb0a0ca3
Author: Andres Gomez <agomez@igalia.com>
Date: Tue Nov 7 12:39:31 2017 +0200
cherry-ignore: radv: copy indirect lowering settings from radeonsi
fixes: remove 6ce550453f1 and 059434e1763, which were depending in now
backported 087e010b2b3.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 3d6480d..3a26997 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -56,12 +56,6 @@ fee9d05e2136b2b7c5a1ad2be7180b99f733f539 radv: Update code pointer correctly if
# stable: 17.3 nomination only.
d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation like radeonsi.
-# fixes: Commit is not applicable when 087e010b2b3 is missing.
-6ce550453f1df64caeb956f215d32da96b89f2b1 radv: Don't use vgpr indexing for outputs on GFX9.
-
-# fixes: Commit is not applicable when 6ce550453f1 is missing.
-c07d719e8b683e1bf78f187dd17fe4716f4e5e9c radv: Disallow indirect outputs for GS on GFX9 as well.
-
# fixes: This commit addressed earlier commit 35ac13ed3 which did not
# land in branch.
11d688d9f0d2ee4d0178d1807c0075e5e8364b1d mesa/bufferobj: don't double negate the range
commit fd0cf2c9460228cc6f2e3ee00a6e1b0f07757a49
Author: Tomasz Figa <tfiga@chromium.org>
Date: Tue Sep 26 17:35:56 2017 +0900
glsl: Allow precision mismatch on dead data with GLSL ES 1.00
Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
mismatching uniform precision, as required by GLES 3.0 specification and
conformance test-suite.
Several Android applications, including Forge of Empires, have shaders
which violate this rule, on a dead varying that will be eliminated.
The problem affects a big number of applications using Cocos2D engine
and other GLES implementations accept this, this poses a serious
application compatibility issue.
Starting from GLSL ES 3.0, declarations with conflicting precision
qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
clearly specify the behavior, except that
"Uniforms are defined to behave as if they are using the same storage in
the vertex and fragment processors and may be implemented this way.
If uniforms are used in both the vertex and fragment shaders, developers
should be warned if the precisions are different. Conversion of
precision should never be implicit."
The word "used" is not clear in this context and might refer to
1) declared (same as GLES 3.x)
2) referred after post-processing, or
3) linked after all optimizations are done.
Looking at existing applications, 2) or 3) seems to be widely adopted.
To avoid compatibility issues, turn the error into a warning if GLSL ES
version is lower than 3.0 and the data is dead in at least one of the
shaders.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97532
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 0886be093fb871b0b6169718277e0f4d18df3ea7)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 03b0db4..c7a7fc5 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -1128,10 +1128,16 @@ cross_validate_globals(struct gl_shader_program *prog,
if (prog->IsES && (prog->data->Version != 310 ||
!var->get_interface_type()) &&
existing->data.precision != var->data.precision) {
- linker_error(prog, "declarations for %s `%s` have "
- "mismatching precision qualifiers\n",
- mode_string(var), var->name);
- return;
+ if ((existing->data.used && var->data.used) || prog->data->Version >= 300) {
+ linker_error(prog, "declarations for %s `%s` have "
+ "mismatching precision qualifiers\n",
+ mode_string(var), var->name);
+ return;
+ } else {
+ linker_warning(prog, "declarations for %s `%s` have "
+ "mismatching precision qualifiers\n",
+ mode_string(var), var->name);
+ }
}
} else
variables->add_variable(var);
commit 6a73458510c124856ade7e5a7e805fb08ae13671
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Tue Nov 7 10:00:50 2017 +0100
radv: Disallow indirect outputs for GS on GFX9 as well.
Since it also uses the output vector before writing to memory.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit c07d719e8b683e1bf78f187dd17fe4716f4e5e9c)
[Bas Nieuwenhuizen: resolve conflicts]
Conflicts:
src/amd/vulkan/radv_shader.c
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 56b987a..bf01026 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -290,10 +290,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_variable_mode indirect_mask = 0;
indirect_mask |= nir_var_shader_in;
- if (!llvm_has_working_vgpr_indexing &&
- (nir->info.stage == MESA_SHADER_VERTEX ||
- nir->info.stage == MESA_SHADER_TESS_EVAL ||
- nir->info.stage == MESA_SHADER_FRAGMENT))
+ if (!llvm_has_working_vgpr_indexing &&
+ nir->info.stage != MESA_SHADER_TESS_CTRL)
indirect_mask |= nir_var_shader_out;
/* TODO: We shouldn't need to do this, however LLVM isn't currently
commit 9ba45e7d33bb91d7b0fc65ecae9cbc8a2ba68593
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Tue Nov 7 10:00:49 2017 +0100
radv: Don't use vgpr indexing for outputs on GFX9.
Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
tests.
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6ce550453f1df64caeb956f215d32da96b89f2b1)
[Bas Nieuwenhuizen: resolve conflicts]
Conflicts:
src/amd/vulkan/radv_shader.c
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e5487fa..56b987a 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -290,6 +290,12 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_variable_mode indirect_mask = 0;
indirect_mask |= nir_var_shader_in;
+ if (!llvm_has_working_vgpr_indexing &&
+ (nir->info.stage == MESA_SHADER_VERTEX ||
+ nir->info.stage == MESA_SHADER_TESS_EVAL ||
+ nir->info.stage == MESA_SHADER_FRAGMENT))
+ indirect_mask |= nir_var_shader_out;
+
/* TODO: We shouldn't need to do this, however LLVM isn't currently
* smart enough to handle indirects without causing excess spilling
* causing the gpu to hang.
commit 662cff8fe4c5cd06b7cb44edefdc2d182b8328d8
Author: Timothy Arceri <tarceri@itsqueeze.com>
Date: Tue Nov 7 10:00:48 2017 +0100
radv: copy indirect lowering settings from radeonsi
It looks the original indirect mask was probably copied from
ANV.
Sascha Willems demo results:
tessellation ~4000 -> ~4200 fps
V2: continue lowering local indirects due to llvm deficiencies.
(cherry picked from commit 087e010b2b3dd83a539f97203909d6c43b5da87c)
[Bas Nieuwenhuizen: patch is a backport for 17.2 of the cherry-pick above]
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index ddd1464..e5487fa 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -275,8 +275,28 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_shader_gather_info(nir, entry_point->impl);
+ /* While it would be nice not to have this flag, we are constrained
+ * by the reality that LLVM 5.0 doesn't have working VGPR indexing
+ * on GFX9.
+ */
+ bool llvm_has_working_vgpr_indexing =
+ device->physical_device->rad_info.chip_class <= VI;
+
+ /* TODO: Indirect indexing of GS inputs is unimplemented.
+ *
+ * TCS and TES load inputs directly from LDS or offchip memory, so
+ * indirect indexing is trivial.
+ */
nir_variable_mode indirect_mask = 0;
indirect_mask |= nir_var_shader_in;
+
+ /* TODO: We shouldn't need to do this, however LLVM isn't currently
+ * smart enough to handle indirects without causing excess spilling
+ * causing the gpu to hang.
+ *
+ * See the following thread for more details of the problem:
+ * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
+ */
indirect_mask |= nir_var_local;
nir_lower_indirect_derefs(nir, indirect_mask);
commit 0b0b7f1833513aa2164361f7b3d50c2a36af53b0
Author: Dave Airlie <airlied@redhat.com>
Date: Fri Nov 3 04:06:35 2017 +0000
radv: add initial copy descriptor support. (v2)
It appears the latest dota2 vulkan uses this,
and we get a hang in VR mode without it.
v2: remove finishme I left in after finishing.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4bcb48b8319fd8185a326bbd1f77191bddd35506)
diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c
index 314ab5a..d8593cf 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -735,8 +735,59 @@ void radv_update_descriptor_sets(
}
}
- if (descriptorCopyCount)
- radv_finishme("copy descriptors");
+
+ for (i = 0; i < descriptorCopyCount; i++) {
+ const VkCopyDescriptorSet *copyset = &pDescriptorCopies[i];
+ RADV_FROM_HANDLE(radv_descriptor_set, src_set,
+ copyset->srcSet);
+ RADV_FROM_HANDLE(radv_descriptor_set, dst_set,
+ copyset->dstSet);
+ const struct radv_descriptor_set_binding_layout *src_binding_layout =
+ src_set->layout->binding + copyset->srcBinding;
+ const struct radv_descriptor_set_binding_layout *dst_binding_layout =
+ dst_set->layout->binding + copyset->dstBinding;
+ uint32_t *src_ptr = src_set->mapped_ptr;
+ uint32_t *dst_ptr = dst_set->mapped_ptr;
+ struct radeon_winsys_bo **src_buffer_list = src_set->descriptors;
+ struct radeon_winsys_bo **dst_buffer_list = dst_set->descriptors;
+
+ src_ptr += src_binding_layout->offset / 4;
+ dst_ptr += dst_binding_layout->offset / 4;
+
+ src_ptr += src_binding_layout->size * copyset->srcArrayElement / 4;
+ dst_ptr += dst_binding_layout->size * copyset->dstArrayElement / 4;
+
+ src_buffer_list += src_binding_layout->buffer_offset;
+ src_buffer_list += copyset->srcArrayElement;
+
+ dst_buffer_list += dst_binding_layout->buffer_offset;
+ dst_buffer_list += copyset->dstArrayElement;
+
+ for (j = 0; j < copyset->descriptorCount; ++j) {
+ switch (src_binding_layout->type) {
+ case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
+ case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
+ unsigned src_idx = copyset->srcArrayElement + j;
+ unsigned dst_idx = copyset->dstArrayElement + j;
+ struct radv_descriptor_range *src_range, *dst_range;
+ src_idx += src_binding_layout->dynamic_offset_offset;
+ dst_idx += dst_binding_layout->dynamic_offset_offset;
+
+ src_range = src_set->dynamic_descriptors + src_idx;
+ dst_range = dst_set->dynamic_descriptors + dst_idx;
+ *dst_range = *src_range;
+ break;
+ }
+ default:
+ memcpy(dst_ptr, src_ptr, src_binding_layout->size);
+ }
+ src_ptr += src_binding_layout->size / 4;
+ dst_ptr += dst_binding_layout->size / 4;
+ dst_buffer_list[j] = src_buffer_list[j];
+ ++src_buffer_list;
+ ++dst_buffer_list;
+ }
+ }
}
void radv_UpdateDescriptorSets(
commit 23eaeeb88ad787b0e3253807fb6f7180a0cb0711
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Nov 6 00:35:17 2017 +0000
radv: free attachments on end command buffer.
If we allocate attachments in the begin command buffer due to the
render pass continue bit, we were leaking them.
Since renderpasses inside a cmd buffer malloc/free these properly,
and set to NULL, we just need to call free at end.
Fixes a memory leak with multithreading demo.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit f0ae06a13c1a60f58de77401f705eaf620b5b822)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index afa6045..d4c4217 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2258,6 +2258,8 @@ VkResult radv_EndCommandBuffer(
si_emit_cache_flush(cmd_buffer);
}
+ vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
+
if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
cmd_buffer->record_fail)
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
commit d8e0f66b5562769c59a86744e91e8f6d13347943
Author: Dave Airlie <airlied@redhat.com>
Date: Fri May 26 11:24:59 2017 +1000
i915g: make gears run again.
We need to validate some structs exist before we dirty the states, and
avoid the problem in some other places.
Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
(cherry picked from commit cc69f2385ee5405cd1bef746d3e9006fc5430545)
diff --git a/src/gallium/drivers/i915/i915_state_derived.c b/src/gallium/drivers/i915/i915_state_derived.c
index dbfbc84..7809010 100644
--- a/src/gallium/drivers/i915/i915_state_derived.c
+++ b/src/gallium/drivers/i915/i915_state_derived.c
@@ -216,6 +216,23 @@ void i915_update_derived(struct i915_context *i915)
if (I915_DBG_ON(DBG_ATOMS))
i915_dump_dirty(i915, __FUNCTION__);
+ if (!i915->fs) {
+ i915->dirty &= ~(I915_NEW_FS_CONSTANTS | I915_NEW_FS);
+ i915->hardware_dirty &= ~(I915_HW_PROGRAM | I915_HW_CONSTANTS);
+ }
+
+ if (!i915->vs)
+ i915->dirty &= ~I915_NEW_VS;
+
+ if (!i915->blend)
+ i915->dirty &= ~I915_NEW_BLEND;
+
+ if (!i915->rasterizer)
+ i915->dirty &= ~I915_NEW_RASTERIZER;
+
+ if (!i915->depth_stencil)
+ i915->dirty &= ~I915_NEW_DEPTH_STENCIL;
+
for (i = 0; atoms[i]; i++)
if (atoms[i]->dirty & i915->dirty)
atoms[i]->update(i915);
diff --git a/src/gallium/drivers/i915/i915_state_dynamic.c b/src/gallium/drivers/i915/i915_state_dynamic.c
index 85b2721..434b09d 100644
--- a/src/gallium/drivers/i915/i915_state_dynamic.c
+++ b/src/gallium/drivers/i915/i915_state_dynamic.c
@@ -213,7 +213,8 @@ static void upload_STIPPLE(struct i915_context *i915)
/* I915_NEW_RASTERIZER
*/
- st[1] |= i915->rasterizer->st;
+ if (i915->rasterizer)
+ st[1] |= i915->rasterizer->st;
/* I915_NEW_STIPPLE
*/
diff --git a/src/gallium/drivers/i915/i915_state_immediate.c b/src/gallium/drivers/i915/i915_state_immediate.c
index b6007ac..14566a4 100644
--- a/src/gallium/drivers/i915/i915_state_immediate.c
+++ b/src/gallium/drivers/i915/i915_state_immediate.c
@@ -168,11 +168,13 @@ static void upload_S6(struct i915_context *i915)
/* I915_NEW_BLEND
*/
- LIS6 |= i915->blend->LIS6;
+ if (i915->blend)
+ LIS6 |= i915->blend->LIS6;
/* I915_NEW_DEPTH
*/
- LIS6 |= i915->depth_stencil->depth_LIS6;
+ if (i915->depth_stencil)
+ LIS6 |= i915->depth_stencil->depth_LIS6;
set_immediate(i915, I915_IMMEDIATE_S6, LIS6);
}
diff --git a/src/gallium/drivers/i915/i915_state_static.c b/src/gallium/drivers/i915/i915_state_static.c
index 9a7ea22..88b418b 100644
--- a/src/gallium/drivers/i915/i915_state_static.c
+++ b/src/gallium/drivers/i915/i915_state_static.c
@@ -216,7 +216,7 @@ static void update_dst_buf_vars(struct i915_context *i915)
zformat = translate_depth_format(depth_surface->format);
if (is->is_i945 && tex->tiling != I915_TILE_NONE
- && !i915->fs->info.writes_z)
+ && (i915->fs && !i915->fs->info.writes_z))
early_z = CLASSIC_EARLY_DEPTH;
} else
zformat = 0;
commit bd2037da82ec8abc1db8834f67496b4b3cd74504
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Wed Nov 1 09:26:48 2017 +0100
radv: Don't expose heaps with 0 memory.
It confuses CTS. This pregenerates the heap info into the
physical device, so we can use it for translating contiguous
indices into our "standard" ones.
This also makes the WSI a bit smarter in case the first preferred
heap does not exist.
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 806721429afa090380bf39a4958fe4e21c63816c)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_private.h
src/amd/vulkan/radv_wsi.c
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 53b7dfa..6b4c43c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -263,6 +263,75 @@ get_chip_name(enum radeon_family family)
}
}
+static void
+radv_physical_device_init_mem_types(struct radv_physical_device *device)
+{
+ STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
+ uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
+ device->rad_info.vram_vis_size);
+
+ int vram_index = -1, visible_vram_index = -1, gart_index = -1;
+ device->memory_properties.memoryHeapCount = 0;
+ if (device->rad_info.vram_size - visible_vram_size > 0) {
+ vram_index = device->memory_properties.memoryHeapCount++;
+ device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
+ .size = device->rad_info.vram_size - visible_vram_size,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ };
+ }
+ if (visible_vram_size) {
+ visible_vram_index = device->memory_properties.memoryHeapCount++;
+ device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
+ .size = visible_vram_size,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ };
+ }
+ if (device->rad_info.gart_size > 0) {
+ gart_index = device->memory_properties.memoryHeapCount++;
+ device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
+ .size = device->rad_info.gart_size,
+ .flags = 0,
+ };
+ }
+
+ STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
+ unsigned type_count = 0;
+ if (vram_index >= 0) {
+ device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
+ device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
+ .heapIndex = vram_index,
+ };
+ }
+ if (gart_index >= 0) {
+ device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
+ device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
+ .heapIndex = gart_index,
+ };
+ }
+ if (visible_vram_index >= 0) {
+ device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
+ device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
+ VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
+ .heapIndex = visible_vram_index,
+ };
+ }
+ if (gart_index >= 0) {
+ device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
+ device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
+ VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
+ .heapIndex = gart_index,
+ };
+ }
+ device->memory_properties.memoryTypeCount = type_count;
+}
+
static VkResult
radv_physical_device_init(struct radv_physical_device *device,
struct radv_instance *instance,
@@ -346,6 +415,7 @@ radv_physical_device_init(struct radv_physical_device *device,
device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
}
+ radv_physical_device_init_mem_types(device);
return VK_SUCCESS;
fail:
@@ -902,49 +972,7 @@ void radv_GetPhysicalDeviceMemoryProperties(
{
RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
- STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
-
- pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
- pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
- .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
- .heapIndex = RADV_MEM_HEAP_VRAM,
- };
- pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
- .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
- .heapIndex = RADV_MEM_HEAP_GTT,
- };
- pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
- .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
- VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
- .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
- };
- pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
- .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
- VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
- .heapIndex = RADV_MEM_HEAP_GTT,
- };
-
- STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
- uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
- physical_device->rad_info.vram_vis_size);
-
- pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
- pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
- .size = physical_device->rad_info.vram_size -
- visible_vram_size,
- .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
- };
- pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
- .size = visible_vram_size,
- .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
- };
- pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
- .size = physical_device->rad_info.gart_size,
- .flags = 0,
- };
+ *pMemoryProperties = physical_device->memory_properties;
}
void radv_GetPhysicalDeviceMemoryProperties2KHR(
@@ -2233,6 +2261,7 @@ VkResult radv_AllocateMemory(
VkResult result;
enum radeon_bo_domain domain;
uint32_t flags = 0;
+ enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
@@ -2275,18 +2304,18 @@ VkResult radv_AllocateMemory(
}
uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
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