mesa: Changes to 'upstream-unstable'
VERSION | 2
bin/.cherry-ignore | 29 +++
docs/relnotes/17.2.3.html | 3
docs/relnotes/17.2.4.html | 131 ++++++++++++++
src/amd/common/ac_nir_to_llvm.c | 10 -
src/amd/vulkan/radv_cmd_buffer.c | 2
src/amd/vulkan/radv_private.h | 8
src/compiler/nir/nir_intrinsics.h | 2
src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c | 2
src/gallium/state_trackers/clover/llvm/codegen/common.cpp | 5
src/gallium/state_trackers/clover/llvm/compat.hpp | 12 +
src/gallium/state_trackers/dri/dri_drawable.c | 4
src/gallium/state_trackers/glx/xlib/xm_st.c | 4
src/gallium/state_trackers/hgl/hgl.c | 4
src/gallium/state_trackers/osmesa/osmesa.c | 2
src/gallium/state_trackers/wgl/stw_st.c | 4
src/intel/compiler/brw_eu_emit.c | 2
src/intel/compiler/brw_fs.cpp | 4
src/intel/compiler/brw_fs_generator.cpp | 1
src/intel/vulkan/anv_pipeline.c | 3
src/mesa/drivers/dri/i965/brw_state_upload.c | 24 --
src/mesa/drivers/dri/i965/intel_screen.c | 2
src/mesa/main/texstate.c | 8
src/mesa/state_tracker/st_manager.c | 2
src/vulkan/wsi/wsi_common_x11.c | 1
25 files changed, 209 insertions(+), 62 deletions(-)
New commits:
commit a4b72e2643b71d37697e2288a5f61e333b1a62fd
Author: Andres Gomez <agomez@igalia.com>
Date: Mon Oct 30 16:46:20 2017 +0200
docs: add release notes for 17.2.4
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/docs/relnotes/17.2.4.html b/docs/relnotes/17.2.4.html
new file mode 100644
index 0000000..cfe9ecb
--- /dev/null
+++ b/docs/relnotes/17.2.4.html
@@ -0,0 +1,131 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.2.4 Release Notes / October 30, 2017</h1>
+
+<p>
+Mesa 17.2.4 is a bug fix release which fixes bugs found since the 17.2.3 release.
+</p>
+<p>
+Mesa 17.2.4 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102774";>Bug 102774</a> - [BDW] [Bisected] Absolute constant buffers break VAAPI in mpv</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103388";>Bug 103388</a> - Linking libcltgsi.la (llvm/codegen/libclllvm_la-common.lo) fails with "error: no match for 'operator-'" with GCC-7, Mesa from Git and current LLVM revisions</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+<p>Andres Gomez (8):</p>
+<ul>
+ <li>cherry-ignore: configure.ac: rework llvm detection and handling</li>
+ <li>cherry-ignore: glsl: fix derived cs variables</li>
+ <li>cherry-ignore: added 17.3 nominations.</li>
+ <li>cherry-ignore: radv: Don't use vgpr indexing for outputs on GFX9.</li>
+ <li>cherry-ignore: radv: Disallow indirect outputs for GS on GFX9 as well.</li>
+ <li>cherry-ignore: mesa/bufferobj: don't double negate the range</li>
+ <li>cherry-ignore: broadcom/vc5: Propagate vc4 aliasing fix to vc5.</li>
+ <li>Update version to 17.2.4</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+ <li>ac/nir: Fix nir_texop_lod on GFX for 1D arrays.</li>
+</ul>
+
+<p>Dave Airlie (1):</p>
+<ul>
+ <li>radv/image: bump all the offset to uint64_t.</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.2.3</li>
+</ul>
+
+<p>Henri Verbeet (1):</p>
+<ul>
+ <li>vulkan/wsi: Free the event in x11_manage_fifo_queues().</li>
+</ul>
+
+<p>Jan Vesely (1):</p>
+<ul>
+ <li>clover: Fix compilation after clang r315871</li>
+</ul>
+
+<p>Jason Ekstrand (4):</p>
+<ul>
+ <li>nir/intrinsics: Set the correct num_indices for load_output</li>
+ <li>intel/fs: Handle flag read/write aliasing in needs_src_copy</li>
+ <li>anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir</li>
+ <li>intel/eu: Use EXECUTE_1 for JMPI</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>i965: Revert absolute mode for constant buffer pointers.</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+ <li>Revert "mesa: fix texture updates for ATI_fragment_shader"</li>
+</ul>
+
+<p>Matthew Nicholls (1):</p>
+<ul>
+ <li>ac/nir: generate correct instruction for atomic min/max on unsigned images</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+ <li>st/mesa: Initialize textures array in st_framebuffer_validate</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+ <li>radv: add the draw count buffer to the list of buffers</li>
+</ul>
+
+<p>Stefan Schake (1):</p>
+<ul>
+ <li>broadcom/vc4: Fix aliasing issue</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit fe9dc0fad61236a841b484dcf72de01e0c6d2835
Author: Andres Gomez <agomez@igalia.com>
Date: Mon Oct 30 16:37:41 2017 +0200
Update version to 17.2.4
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/VERSION b/VERSION
index afbe633..97dbfc8 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.2.3
+17.2.4
commit 162fa27b12489d475fbb9d12e7e620f47500c0c9
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Oct 25 04:19:13 2017 +0300
cherry-ignore: broadcom/vc5: Propagate vc4 aliasing fix to vc5.
extra: Commit is not applicable when ade416d0236 is missing.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 2ea1bd2..3d6480d 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -65,3 +65,6 @@ c07d719e8b683e1bf78f187dd17fe4716f4e5e9c radv: Disallow indirect outputs for GS
# fixes: This commit addressed earlier commit 35ac13ed3 which did not
# land in branch.
11d688d9f0d2ee4d0178d1807c0075e5e8364b1d mesa/bufferobj: don't double negate the range
+
+# extra: Commit is not applicable when ade416d0236 is missing.
+07bfdb478bf844a0ac9cf3679f51f83c4abea5a1 broadcom/vc5: Propagate vc4 aliasing fix to vc5.
commit b3207d9ff793dd3163f62ab85047675140d0f8d2
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Oct 25 04:13:05 2017 +0300
cherry-ignore: mesa/bufferobj: don't double negate the range
fixes: This commit addressed earlier commit 35ac13ed3 which did not
land in branch.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index e034d13..2ea1bd2 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -61,3 +61,7 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# fixes: Commit is not applicable when 6ce550453f1 is missing.
c07d719e8b683e1bf78f187dd17fe4716f4e5e9c radv: Disallow indirect outputs for GS on GFX9 as well.
+
+# fixes: This commit addressed earlier commit 35ac13ed3 which did not
+# land in branch.
+11d688d9f0d2ee4d0178d1807c0075e5e8364b1d mesa/bufferobj: don't double negate the range
commit 6cab29e9736d7bdc130095b73e028c4c5d9f8c6c
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Oct 25 04:09:45 2017 +0300
cherry-ignore: radv: Disallow indirect outputs for GS on GFX9 as well.
fixes: Commit is not applicable when 6ce550453f1 is missing.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 65b613a..e034d13 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -58,3 +58,6 @@ d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation
# fixes: Commit is not applicable when 087e010b2b3 is missing.
6ce550453f1df64caeb956f215d32da96b89f2b1 radv: Don't use vgpr indexing for outputs on GFX9.
+
+# fixes: Commit is not applicable when 6ce550453f1 is missing.
+c07d719e8b683e1bf78f187dd17fe4716f4e5e9c radv: Disallow indirect outputs for GS on GFX9 as well.
commit 1c2f79066cc7a7f3024197a620a4d358c3237853
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Oct 25 04:06:49 2017 +0300
cherry-ignore: radv: Don't use vgpr indexing for outputs on GFX9.
fixes: Commit is not applicable when 087e010b2b3 is missing.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 0c0afa4..65b613a 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -55,3 +55,6 @@ fee9d05e2136b2b7c5a1ad2be7180b99f733f539 radv: Update code pointer correctly if
# stable: 17.3 nomination only.
d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation like radeonsi.
+
+# fixes: Commit is not applicable when 087e010b2b3 is missing.
+6ce550453f1df64caeb956f215d32da96b89f2b1 radv: Don't use vgpr indexing for outputs on GFX9.
commit 0c63d53765664201946b645874a102e4fbdcad7b
Author: Andres Gomez <agomez@igalia.com>
Date: Wed Oct 25 03:53:26 2017 +0300
cherry-ignore: added 17.3 nominations.
stable: 17.3 nominations only.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 67a78a2..0c0afa4 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -49,3 +49,9 @@ df3a43018020c16c1dfa88a76c9a84c9fb85be38 configure.ac: add missing LLVM componen
# stable: Commit is too big for stable at this point.
4d24a7cb97641cacecd371d1968f6964785822e4 glsl: fix derived cs variables
+
+# stable: 17.3 nomination only.
+fee9d05e2136b2b7c5a1ad2be7180b99f733f539 radv: Update code pointer correctly if a variant is already created
+
+# stable: 17.3 nomination only.
+d8cefaa197f02944812ef535b1b303dd5bf26848 radv: use device name in cache creation like radeonsi.
commit 52019bad1dbd4abd5a89957c70490827ef6367ec
Author: Andres Gomez <agomez@igalia.com>
Date: Thu Oct 26 16:15:47 2017 +0300
cherry-ignore: glsl: fix derived cs variables
stable: Commit is too big for stable at this point.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index aeca666..67a78a2 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -46,3 +46,6 @@ fe2a6281b3b299998fe7399e7dbcc2077d773824 egl/drm: Fix misused x and y offsets in
a7ecf7b86f4eae59f3ceac2125e5d1725c403c07 Travis: add binutils 2.26 for a few more LLVM 3.9 builds
36d6d1e931936a80da327889862ba02942ac427b configure.ac: add llvm_add_optional_component helper
df3a43018020c16c1dfa88a76c9a84c9fb85be38 configure.ac: add missing LLVM components for OpenCL
+
+# stable: Commit is too big for stable at this point.
+4d24a7cb97641cacecd371d1968f6964785822e4 glsl: fix derived cs variables
commit 9bdd943ff258a0d942a7e49fa6a57ee0a75c9427
Author: Andres Gomez <agomez@igalia.com>
Date: Thu Oct 26 16:10:54 2017 +0300
cherry-ignore: configure.ac: rework llvm detection and handling
stable: Commits are too invasive for 17.2.
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index ad96159..aeca666 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -39,3 +39,10 @@ fe2a6281b3b299998fe7399e7dbcc2077d773824 egl/drm: Fix misused x and y offsets in
# stable: The commit addresses earlier commit a62a9793357 which is no applicable
# for the stable branch
6c7720ed78db754d52f204cbb74897aa9e65ea7e anv/wsi: Allocate enough memory for the entire image
+
+# stable: Commits are too invasive for 17.2.
+98fdff7247b6877d028d33284f9cc63189ee204e configure.ac: factor out detection for old and buggy llvm
+13a53c4f5cdd664fd155c9e78fb46a4387af006c configure.ac: rework llvm libs handling for 3.9+
+a7ecf7b86f4eae59f3ceac2125e5d1725c403c07 Travis: add binutils 2.26 for a few more LLVM 3.9 builds
+36d6d1e931936a80da327889862ba02942ac427b configure.ac: add llvm_add_optional_component helper
+df3a43018020c16c1dfa88a76c9a84c9fb85be38 configure.ac: add missing LLVM components for OpenCL
commit 1393d37d7bd5ff3834ec8fe1948a8a900f844a3e
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Aug 31 11:42:00 2017 -0700
intel/eu: Use EXECUTE_1 for JMPI
The PRM says "The execution size must be 1." In 73137997e23ff6c11, the
execution size was set to 1 when it should have been BRW_EXECUTE_1
(which maps to 0). Later, in dc2d3a7f5c217a7cee9, JMPI was used for
line AA on gen6 and earlier and we started manually stomping the
exeution size to BRW_EXECUTE_1 in the generator. This commit fixes the
original bug and makes brw_JMPI just do the right thing.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 73137997e23ff6c1145d036315d1a9ad96651281
(cherry picked from commit 562b8d458c2de262019da2c056f75cb9feb5ee54)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0b0d67a..fa59086 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1376,7 +1376,7 @@ brw_JMPI(struct brw_codegen *p, struct brw_reg index,
struct brw_reg ip = brw_ip_reg();
brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
- brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_2);
+ brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, inst, predicate_control);
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 2ade486..0c14c03 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -397,7 +397,6 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
- brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
{
/* Don't send AA data */
fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
commit 74f19032341748ad257a0c2527624b661e2d2e6f
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Oct 2 09:53:50 2017 -0700
anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir
We currently have a bug where nir_lower_system_values gets called before
nir_lower_var_copies so it will miss any system value uses which come
from a copy_var intrinsic. Moving it to after brw_preprocess_nir fixes
this problem.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 279f8fb69cf68d05287e14f60cf67fc025643bc4)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/anv_pipeline.c
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 6ae682f..8c4daa0 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -171,13 +171,14 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
NIR_PASS_V(nir, nir_propagate_invariant);
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
entry_point->impl, true, false);
- NIR_PASS_V(nir, nir_lower_system_values);
/* Vulkan uses the separate-shader linking model */
nir->info.separate_shader = true;
nir = brw_preprocess_nir(compiler, nir);
+ NIR_PASS_V(nir, nir_lower_system_values);
+
NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
if (stage == MESA_SHADER_FRAGMENT)
commit aac0807f4843d42690119007a5c40fe03714accf
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed Sep 6 18:33:38 2017 -0700
intel/fs: Handle flag read/write aliasing in needs_src_copy
In order to implement the ballot intrinsic, we do a MOV from flag
register to some GRF. If that GRF is used in a SEL, cmod propagation
helpfully changes it into a MOV from the flag register with a cmod.
This is perfectly valid but when lower_simd_width comes along, it simply
splits into two instructions which both have conditional modifiers.
This is a problem since we're reading the flag register. This commit
makes us check whether or not flags_written() overlaps with the flag
values that we are reading via the instruction source and, if we have
any interference, will force us to emit a copy of the source.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit fa6e74e33e5bc5f6fba8f9de76b8b059515e708f)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 38b5e52..91e9f92 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5013,7 +5013,9 @@ needs_src_copy(const fs_builder &lbld, const fs_inst *inst, unsigned i)
{
return !(is_periodic(inst->src[i], lbld.dispatch_width()) ||
(inst->components_read(i) == 1 &&
- lbld.dispatch_width() <= inst->exec_size));
+ lbld.dispatch_width() <= inst->exec_size)) ||
+ (inst->flags_written() &
+ flag_mask(inst->src[i], type_sz(inst->src[i].type)));
}
/**
commit 03f3899f99163f918d107fd91d486b87a9d51aa2
Author: Jan Vesely <jan.vesely@rutgers.edu>
Date: Sat Oct 21 15:38:54 2017 -0400
clover: Fix compilation after clang r315871
v2: use a more generic compat function
v3: rename and formatting cleanup
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a6d38f476beaaf0a9677cfc168172121b5779570)
diff --git a/src/gallium/state_trackers/clover/llvm/codegen/common.cpp b/src/gallium/state_trackers/clover/llvm/codegen/common.cpp
index 0751834..ddf2083 100644
--- a/src/gallium/state_trackers/clover/llvm/codegen/common.cpp
+++ b/src/gallium/state_trackers/clover/llvm/codegen/common.cpp
@@ -70,7 +70,6 @@ namespace {
make_kernel_args(const Module &mod, const std::string &kernel_name,
const clang::CompilerInstance &c) {
std::vector<module::argument> args;
- const auto address_spaces = c.getTarget().getAddressSpaceMap();
const Function &f = *mod.getFunction(kernel_name);
::llvm::DataLayout dl(&mod);
const auto size_type =
@@ -128,8 +127,8 @@ namespace {
const unsigned address_space =
cast< ::llvm::PointerType>(actual_type)->getAddressSpace();
- if (address_space == address_spaces[clang::LangAS::opencl_local
- - compat::lang_as_offset]) {
+ if (address_space == compat::target_address_space(
+ c.getTarget(), clang::LangAS::opencl_local)) {
args.emplace_back(module::argument::local, arg_api_size,
target_size, target_align,
module::argument::zero_ext);
diff --git a/src/gallium/state_trackers/clover/llvm/compat.hpp b/src/gallium/state_trackers/clover/llvm/compat.hpp
index 06d3b6f..1b4bc23 100644
--- a/src/gallium/state_trackers/clover/llvm/compat.hpp
+++ b/src/gallium/state_trackers/clover/llvm/compat.hpp
@@ -68,11 +68,19 @@ namespace clover {
typedef ::llvm::TargetLibraryInfo target_library_info;
#endif
+ template<typename T, typename AS>
+ unsigned target_address_space(const T &target, const AS lang_as) {
+ const auto &map = target.getAddressSpaceMap();
+#if HAVE_LLVM >= 0x0500
+ return map[static_cast<unsigned>(lang_as)];
+#else
+ return map[lang_as - clang::LangAS::Offset];
+#endif
+ }
+
#if HAVE_LLVM >= 0x0500
- const auto lang_as_offset = 0;
const clang::InputKind ik_opencl = clang::InputKind::OpenCL;
#else
- const auto lang_as_offset = clang::LangAS::Offset;
const clang::InputKind ik_opencl = clang::IK_OpenCL;
#endif
commit 87a9a989ee2c3a86faaf0b817e833045917d06b2
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri Sep 15 16:22:00 2017 -0700
nir/intrinsics: Set the correct num_indices for load_output
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit c1b84256ccc443a9792893bc780bba970c0dcd4e)
diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h
index 70da545..4082820 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -433,7 +433,7 @@ INTRINSIC(load_interpolated_input, 2, ARR(2, 1), true, 0, 0,
/* src[] = { buffer_index, offset }. No const_index */
LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { offset }. const_index[] = { base, component } */
-LOAD(output, 1, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
+LOAD(output, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { vertex, offset }. const_index[] = { base, component } */
LOAD(per_vertex_output, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { offset }. const_index[] = { base } */
commit ce725baa7c90420b46e16087a4f201a7e62b23e5
Author: Matthew Nicholls <mnicholls@feralinteractive.com>
Date: Wed Oct 25 14:20:43 2017 +0100
ac/nir: generate correct instruction for atomic min/max on unsigned images
v2: fix silly typo
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 27a0b24bf238342031e0709584e4d71ab228f1ec)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0c46566..a9c231c 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3511,15 +3511,17 @@ static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
if (ctx->stage == MESA_SHADER_FRAGMENT)
ctx->shader_info->fs.writes_memory = true;
+ bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
+
switch (instr->intrinsic) {
case nir_intrinsic_image_atomic_add:
atomic_name = "add";
break;
case nir_intrinsic_image_atomic_min:
- atomic_name = "smin";
+ atomic_name = is_unsigned ? "umin" : "smin";
break;
case nir_intrinsic_image_atomic_max:
- atomic_name = "smax";
+ atomic_name = is_unsigned ? "umax" : "smax";
break;
case nir_intrinsic_image_atomic_and:
atomic_name = "and";
commit f46ba9ee35265bcbd2b3b9b61ac79e25951eb224
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Oct 22 18:32:14 2017 +0200
ac/nir: Fix nir_texop_lod on GFX for 1D arrays.
Fixes: 1bcb953e166 'radv: handle GFX9 1D textures'
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 2c5b43c87fc4e5dcc50f72d782d7b3718e3c2c1c)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ea4441c..0c46566 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4553,7 +4553,9 @@ static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
filler = LLVMConstReal(ctx->f32, 0.5);
if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
- if (instr->is_array) {
+ /* No nir_texop_lod, because it does not take a slice
+ * even with array textures. */
+ if (instr->is_array && instr->op != nir_texop_lod ) {
address[count] = address[count - 1];
address[count - 1] = filler;
count++;
commit 2d51d41865852a78047c36756ea385083292b6dd
Author: Stefan Schake <stschake@gmail.com>
Date: Fri Oct 20 16:16:44 2017 +0200
broadcom/vc4: Fix aliasing issue
This was causing Android clang version 3.8.256229 to miscompile,
presumably due to strict aliasing.
Fixes: 14dc281c1332 ("vc4: Enforce one-uniform-per-instruction after optimization.")
(cherry picked from commit e5fea0d621af2b14cf6c5e364eeaf293db460f2a)
diff --git a/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c b/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c
index 9ecfe65..ad19f06 100644
--- a/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c
+++ b/src/gallium/drivers/vc4/vc4_qir_lower_uniforms.c
@@ -66,7 +66,7 @@ remove_uniform(struct hash_table *ht, struct qreg reg)
entry = _mesa_hash_table_search(ht, key);
assert(entry);
- entry->data--;
+ entry->data = (void *)(((uintptr_t) entry->data) - 1);
if (entry->data == NULL)
_mesa_hash_table_remove(ht, entry);
}
commit cbc081b8711a519dd9aa371debbf68aa0add4076
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Oct 19 14:38:30 2017 -0700
i965: Revert absolute mode for constant buffer pointers.
The kernel doesn't initialize the value of the INSTPM or CS_DEBUG_MODE2
registers at context initialization time. Instead, they're inherited
from whatever happened to be running on the GPU prior to first run of a
new context. So, when we started setting these, other contexts in the
system started inheriting our values. Since this controls whether
3DSTATE_CONSTANT_* takes a pointer or an offset, getting the wrong
setting is fatal for almost any process which isn't expecting this.
Unfortunately, VA-API and Beignet don't initialize this (nor does older
Mesa), so they will die horribly if we start doing this. UXA and SNA
don't use any push constants, so they are unaffected.
Until we have some kind of solution to this problem, I'm going to revert
this patch and abandon using the feature for now. It will lead to fewer
pushed UBO ranges on Broadwell+, which may lead to lower performance,
though I don't have any data on the impact.
Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102774
(cherry picked from commit 013d33122028f2492da90a03ae4bc1dab84c3ee9)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_state_upload.c
src/mesa/drivers/dri/i965/intel_screen.c
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 278ef2e..07df3cc 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -99,30 +99,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
}
-
- /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
- * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
- *
- * On Gen6-7.5, we use an execbuf parameter to do this for us.
- * However, the kernel ignores that when execlists are in use.
- * Fortunately, we can just write the registers from userspace
- * on Gen8+, and they're context saved/restored.
- */
- if (brw->gen >= 9) {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(CS_DEBUG_MODE2);
- OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) |
- CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE);
- ADVANCE_BATCH();
- } else if (brw->gen == 8) {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(INSTPM);
- OUT_BATCH(REG_MASK(INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) |
- INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE);
- ADVANCE_BATCH();
- }
}
static inline const struct brw_tracked_state *
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 5adb8ef..d7f2a31 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2342,7 +2342,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
screen->compiler = brw_compiler_create(screen, devinfo);
screen->compiler->shader_debug_log = shader_debug_log_mesa;
screen->compiler->shader_perf_log = shader_perf_log_mesa;
- screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8;
+ screen->compiler->constant_buffer_0_is_relative = true;
screen->program_id = 1;
screen->has_exec_fence =
commit 546b4d455ac694000c74057a8eecf9ab8aa7acf6
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Mon Oct 16 16:35:18 2017 +0200
st/mesa: Initialize textures array in st_framebuffer_validate
And just reference pipe_resources to it in the validate callbacks.
Avoids pipe_resource leaks when st_framebuffer_validate ends up calling
the validate callback multiple times, e.g. when a window is resized.
v2:
* Use generic stable tag instead of Fixes: tag, since the problem could
already happen before the commit referenced in v1 (Thomas Hellstrom)
* Use memset to initialize the array on the stack instead of allocating
the array with os_calloc.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
(cherry picked from commit 7561da367baeb49c848dc49b65e252deb6428422)
Squashed with:
st/osmesa: include u_inlines.h for pipe_resource_reference
Fixes build failure due to unresolved symbol.
Fixes: 7561da367bae "st/mesa: Initialize textures array in
st_framebuffer_validate"
Trivial.
(cherry picked from commit 8c9e7c9638278687297fbc6ba4344771d61f721e)
diff --git a/src/gallium/state_trackers/dri/dri_drawable.c b/src/gallium/state_trackers/dri/dri_drawable.c
index 9e0dd6b..4176c1c 100644
--- a/src/gallium/state_trackers/dri/dri_drawable.c
+++ b/src/gallium/state_trackers/dri/dri_drawable.c
@@ -99,10 +99,8 @@ dri_st_framebuffer_validate(struct st_context_iface *stctx,
return TRUE;
/* Set the window-system buffers for the state tracker. */
- for (i = 0; i < count; i++) {
- out[i] = NULL;
+ for (i = 0; i < count; i++)
pipe_resource_reference(&out[i], textures[statts[i]]);
- }
return TRUE;
}
diff --git a/src/gallium/state_trackers/glx/xlib/xm_st.c b/src/gallium/state_trackers/glx/xlib/xm_st.c
index 0c42e65..946b5dc 100644
--- a/src/gallium/state_trackers/glx/xlib/xm_st.c
+++ b/src/gallium/state_trackers/glx/xlib/xm_st.c
@@ -245,10 +245,8 @@ xmesa_st_framebuffer_validate(struct st_context_iface *stctx,
}
}
- for (i = 0; i < count; i++) {
- out[i] = NULL;
+ for (i = 0; i < count; i++)
pipe_resource_reference(&out[i], xstfb->textures[statts[i]]);
- }
return TRUE;
}
diff --git a/src/gallium/state_trackers/hgl/hgl.c b/src/gallium/state_trackers/hgl/hgl.c
index 1b70281..bbc477a 100644
--- a/src/gallium/state_trackers/hgl/hgl.c
+++ b/src/gallium/state_trackers/hgl/hgl.c
@@ -193,10 +193,8 @@ hgl_st_framebuffer_validate(struct st_context_iface *stctxi,
//}
}
- for (i = 0; i < count; i++) {
- out[i] = NULL;
+ for (i = 0; i < count; i++)
pipe_resource_reference(&out[i], buffer->textures[statts[i]]);
- }
return TRUE;
}
diff --git a/src/gallium/state_trackers/osmesa/osmesa.c b/src/gallium/state_trackers/osmesa/osmesa.c
index 751d255..8326918 100644
--- a/src/gallium/state_trackers/osmesa/osmesa.c
+++ b/src/gallium/state_trackers/osmesa/osmesa.c
@@ -62,6 +62,7 @@
#include "util/u_box.h"
#include "util/u_debug.h"
#include "util/u_format.h"
+#include "util/u_inlines.h"
#include "util/u_memory.h"
#include "postprocess/filters.h"
@@ -432,6 +433,7 @@ osmesa_st_framebuffer_validate(struct st_context_iface *stctx,
templat.format = format;
templat.bind = bind;
+ pipe_resource_reference(&out[i], NULL);
out[i] = osbuffer->textures[statts[i]] =
screen->resource_create(screen, &templat);
}
diff --git a/src/gallium/state_trackers/wgl/stw_st.c b/src/gallium/state_trackers/wgl/stw_st.c
index 5e165c8..7cf18f0 100644
--- a/src/gallium/state_trackers/wgl/stw_st.c
+++ b/src/gallium/state_trackers/wgl/stw_st.c
@@ -161,10 +161,8 @@ stw_st_framebuffer_validate(struct st_context_iface *stctx,
stwfb->fb->must_resize = FALSE;
}
- for (i = 0; i < count; i++) {
- out[i] = NULL;
+ for (i = 0; i < count; i++)
pipe_resource_reference(&out[i], stwfb->textures[statts[i]]);
- }
stw_framebuffer_unlock(stwfb->fb);
diff --git a/src/mesa/state_tracker/st_manager.c b/src/mesa/state_tracker/st_manager.c
index 5ad0816..011c05f 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -190,6 +190,8 @@ st_framebuffer_validate(struct st_framebuffer *stfb,
if (stfb->iface_stamp == new_stamp)
return;
+ memset(textures, 0, stfb->num_statts * sizeof(textures[0]));
+
/* validate the fb */
do {
if (!stfb->iface->validate(&st->iface, stfb->iface, stfb->statts,
commit 9cbf8c910e8967334d5f26489b5924025cc03478
Author: Henri Verbeet <hverbeet@gmail.com>
Date: Fri Oct 13 17:10:26 2017 +0200
vulkan/wsi: Free the event in x11_manage_fifo_queues().
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
Fixes: e73d136a023 ("vulkan/wsi/x11: Implement FIFO mode.")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com
(cherry picked from commit 3de87f7cd79b21ef3844670e601af4a60409986b)
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index ecdaf91..22b067b 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -939,6 +939,7 @@ x11_manage_fifo_queues(void *state)
goto fail;
result = x11_handle_dri3_present_event(chain, (void *)event);
+ free(event);
if (result != VK_SUCCESS)
goto fail;
}
commit 1eb4cbc934afd72ea45521eeac763e43564d972b
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Oct 17 08:17:12 2017 +0100
radv/image: bump all the offset to uint64_t.
So one of the CTS tests tries to allocate a 16384x1 2048 array
texture. This overflows a bunch of calculations when we want it
tiled as the heights goes to 128.
addrlib returns us the correct size (16GB or so), but we mangle
it in the htile calcs due to the 32-bit offset fields, then
userspace gives us the reduced number and we try to allocate
it on a heap and things blow up.
We really need to give the app back the correct size for the
image so we can blow up properly in memory allocation later.
This should fix hangs in
dEQP-VK.pipeline.render_to_image.core.1d_array.huge.width_layers.r8g8b8a8_unorm_d32_sfloat_s8_uint
since
Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.)
Now there's an open question if we should be enabling tc-compat
htile at all for shallow textures like the above.
This might cause some other wierd side effects in CTS even
without the tc compat so:
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 35c66f3e40177a97d74e614e2a324a03e2149c73)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/vulkan/radv_private.h
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 5cfc62e..478b3af 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1213,14 +1213,14 @@ struct radv_image {
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
- uint32_t dcc_offset;
- uint32_t htile_offset;
+ uint64_t dcc_offset;
+ uint64_t htile_offset;
struct radeon_surf surface;
struct radv_fmask_info fmask;
struct radv_cmask_info cmask;
- uint32_t clear_value_offset;
- uint32_t dcc_pred_offset;
+ uint64_t clear_value_offset;
+ uint64_t dcc_pred_offset;
};
/* Whether the image has a htile that is known consistent with the contents of
commit fba44d91d0c31fb7c531f3443e34956415a14199
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Oct 17 03:08:47 2017 +0200
Revert "mesa: fix texture updates for ATI_fragment_shader"
This reverts commit 9d54025cd1eee3f42b80c062d1f644904bf2ba41.
It breaks KOTOR.
Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 5d071bf04bcf4c35452faaac253cdc9bac31f780)
diff --git a/src/mesa/main/texstate.c b/src/mesa/main/texstate.c
index edd2253..269e291 100644
--- a/src/mesa/main/texstate.c
+++ b/src/mesa/main/texstate.c
@@ -840,11 +840,9 @@ _mesa_update_texture_state(struct gl_context *ctx)
memcpy(prog, ctx->_Shader->CurrentProgram, sizeof(prog));
- if (prog[MESA_SHADER_FRAGMENT] == NULL) {
- if (_mesa_arb_fragment_program_enabled(ctx))
- prog[MESA_SHADER_FRAGMENT] = ctx->FragmentProgram.Current;
- else if (_mesa_ati_fragment_shader_enabled(ctx))
- prog[MESA_SHADER_FRAGMENT] = ctx->ATIFragmentShader.Current->Program;
+ if (prog[MESA_SHADER_FRAGMENT] == NULL &&
+ _mesa_arb_fragment_program_enabled(ctx)) {
+ prog[MESA_SHADER_FRAGMENT] = ctx->FragmentProgram.Current;
}
/* TODO: only set this if there are actual changes */
commit 9cba4d491cccd1a7bcc13bd5d46089b87ad13cd0
Author: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Fri Oct 13 18:20:21 2017 +0200
radv: add the draw count buffer to the list of buffers
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