libdrm: Changes to 'debian-unstable'
amdgpu/amdgpu-symbol-check | 1
amdgpu/amdgpu.h | 17 +++++++-
amdgpu/amdgpu_cs.c | 17 ++++++--
configure.ac | 2
debian/changelog | 8 +++
debian/control | 2
debian/libdrm-amdgpu1.symbols | 1
debian/rules | 2
include/drm/amdgpu_drm.h | 32 ++++++++++++++-
tests/modetest/modetest.c | 89 +++++++++++++++++++++++++++++++++++++++++-
xf86drmMode.c | 10 ++--
xf86drmMode.h | 11 ++---
12 files changed, 171 insertions(+), 21 deletions(-)
New commits:
commit d3feff5f1afbdee438c7375763f13846e965c3e1
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Mon Oct 30 14:01:53 2017 +0100
Upload to unstable.
diff --git a/debian/changelog b/debian/changelog
index febcc7a..d866408 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,10 @@
-libdrm (2.4.85-1) UNRELEASED; urgency=medium
+libdrm (2.4.85-1) unstable; urgency=medium
* New upstream release.
* Update libdrm-amdgpu1.symbols and shlibs.
* Bump standards version to 4.1.1.
- -- Andreas Boll <andreas.boll.dev@gmail.com> Mon, 30 Oct 2017 13:38:25 +0100
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Mon, 30 Oct 2017 14:01:40 +0100
libdrm (2.4.84-2) unstable; urgency=medium
commit 0e8476c29d68f07032212bae9d4b3d18e14319c7
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Mon Oct 30 13:52:39 2017 +0100
Bump standards version to 4.1.1.
diff --git a/debian/changelog b/debian/changelog
index 18ce89d..febcc7a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -2,6 +2,7 @@ libdrm (2.4.85-1) UNRELEASED; urgency=medium
* New upstream release.
* Update libdrm-amdgpu1.symbols and shlibs.
+ * Bump standards version to 4.1.1.
-- Andreas Boll <andreas.boll.dev@gmail.com> Mon, 30 Oct 2017 13:38:25 +0100
diff --git a/debian/control b/debian/control
index 3777fcc..2274f72 100644
--- a/debian/control
+++ b/debian/control
@@ -14,7 +14,7 @@ Build-Depends:
libpciaccess-dev,
valgrind [amd64 armhf i386 mips mipsel powerpc s390x],
libbsd-dev [kfreebsd-any],
-Standards-Version: 4.0.0
+Standards-Version: 4.1.1
Section: libs
Vcs-Git: https://anonscm.debian.org/git/pkg-xorg/lib/libdrm.git
Vcs-Browser: https://anonscm.debian.org/cgit/pkg-xorg/lib/libdrm.git
commit af89a5aba1c4e275cbf07bb4e3f6476981e07ad0
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Mon Oct 30 13:51:33 2017 +0100
Update libdrm-amdgpu1.symbols and shlibs.
diff --git a/debian/changelog b/debian/changelog
index 848315c..18ce89d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,7 @@
libdrm (2.4.85-1) UNRELEASED; urgency=medium
* New upstream release.
+ * Update libdrm-amdgpu1.symbols and shlibs.
-- Andreas Boll <andreas.boll.dev@gmail.com> Mon, 30 Oct 2017 13:38:25 +0100
diff --git a/debian/libdrm-amdgpu1.symbols b/debian/libdrm-amdgpu1.symbols
index 8a6dd8d..0b516ff 100644
--- a/debian/libdrm-amdgpu1.symbols
+++ b/debian/libdrm-amdgpu1.symbols
@@ -18,6 +18,7 @@ libdrm_amdgpu.so.1 libdrm-amdgpu1 #MINVER#
amdgpu_cs_chunk_fence_to_dep@Base 2.4.82
amdgpu_cs_create_semaphore@Base 2.4.67
amdgpu_cs_create_syncobj@Base 2.4.82
+ amdgpu_cs_ctx_create2@Base 2.4.85
amdgpu_cs_ctx_create@Base 2.4.63
amdgpu_cs_ctx_free@Base 2.4.63
amdgpu_cs_destroy_semaphore@Base 2.4.67
diff --git a/debian/rules b/debian/rules
index fecf6e4..113a619 100755
--- a/debian/rules
+++ b/debian/rules
@@ -108,7 +108,7 @@ ifeq ($(NOUVEAU), yes)
dh_makeshlibs -plibdrm-nouveau2 -V'libdrm-nouveau2 (>= 2.4.66)' -- -c4
endif
dh_makeshlibs -plibdrm-radeon1 -V'libdrm-radeon1 (>= 2.4.39)' -- -c4
- dh_makeshlibs -plibdrm-amdgpu1 -V'libdrm-amdgpu1 (>= 2.4.82)' -- -c4
+ dh_makeshlibs -plibdrm-amdgpu1 -V'libdrm-amdgpu1 (>= 2.4.85)' -- -c4
ifeq ($(ARM), yes)
dh_makeshlibs -plibdrm-omap1 -V'libdrm-omap1 (>= 2.4.38)' -- -c4
dh_makeshlibs -plibdrm-exynos1 -V'libdrm-exynos1 (>= 2.4.66)' -- -c4
commit ffde4528e6647e5b5a2668f0139857c061b62de6
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Mon Oct 30 13:38:41 2017 +0100
Bump changelog
diff --git a/debian/changelog b/debian/changelog
index 96948fa..848315c 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+libdrm (2.4.85-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Mon, 30 Oct 2017 13:38:25 +0100
+
libdrm (2.4.84-2) unstable; urgency=medium
* libdrm-amdgpu1.symbols: Updated.
commit e580be90e88eeed95faa5452e343f3ec509517e5
Author: Marek Olšák <marek.olsak@amd.com>
Date: Sat Oct 21 00:26:24 2017 +0200
configure.ac: bump version to 2.4.85
diff --git a/configure.ac b/configure.ac
index ccb910a..16df3a6 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.84],
+ [2.4.85],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit f579747485115cb1605a671082a70181b9a5b425
Author: Marek Olšák <marek.olsak@amd.com>
Date: Sat Oct 21 00:19:52 2017 +0200
amdgpu: add padding to the fence to handle ioctl
copied from Dave's kernel patch.
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index ff01818..919248f 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -553,6 +553,7 @@ union drm_amdgpu_fence_to_handle {
struct {
struct drm_amdgpu_fence fence;
__u32 what;
+ __u32 pad;
} in;
struct {
__u32 handle;
commit 09be54122fbd145d23751eddf7be5b220774a117
Author: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Date: Tue Oct 10 12:12:52 2017 +0200
Add const qualifier to arguments of drmModeAddFB2()
Both drmModeAddFB2() and drmModeAddFB2WithModifiers() have some
arguments that are just pointers to uint32_t in disguise. These
are not modified (just copied) in the function, so we can add a
const qualifier here.
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
diff --git a/xf86drmMode.c b/xf86drmMode.c
index d3bc20e..2b3887b 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -271,9 +271,9 @@ int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
}
int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height,
- uint32_t pixel_format, uint32_t bo_handles[4],
- uint32_t pitches[4], uint32_t offsets[4],
- uint64_t modifier[4], uint32_t *buf_id, uint32_t flags)
+ uint32_t pixel_format, const uint32_t bo_handles[4],
+ const uint32_t pitches[4], const uint32_t offsets[4],
+ const uint64_t modifier[4], uint32_t *buf_id, uint32_t flags)
{
struct drm_mode_fb_cmd2 f;
int ret;
@@ -297,8 +297,8 @@ int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height,
}
int drmModeAddFB2(int fd, uint32_t width, uint32_t height,
- uint32_t pixel_format, uint32_t bo_handles[4],
- uint32_t pitches[4], uint32_t offsets[4],
+ uint32_t pixel_format, const uint32_t bo_handles[4],
+ const uint32_t pitches[4], const uint32_t offsets[4],
uint32_t *buf_id, uint32_t flags)
{
return drmModeAddFB2WithModifiers(fd, width, height,
diff --git a/xf86drmMode.h b/xf86drmMode.h
index 5b390d9..6dbe335 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -369,15 +369,16 @@ extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
uint32_t *buf_id);
/* ...with a specific pixel format */
extern int drmModeAddFB2(int fd, uint32_t width, uint32_t height,
- uint32_t pixel_format, uint32_t bo_handles[4],
- uint32_t pitches[4], uint32_t offsets[4],
+ uint32_t pixel_format, const uint32_t bo_handles[4],
+ const uint32_t pitches[4], const uint32_t offsets[4],
uint32_t *buf_id, uint32_t flags);
/* ...with format modifiers */
int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height,
- uint32_t pixel_format, uint32_t bo_handles[4],
- uint32_t pitches[4], uint32_t offsets[4],
- uint64_t modifier[4], uint32_t *buf_id, uint32_t flags);
+ uint32_t pixel_format, const uint32_t bo_handles[4],
+ const uint32_t pitches[4], const uint32_t offsets[4],
+ const uint64_t modifier[4], uint32_t *buf_id,
+ uint32_t flags);
/**
* Destroies the given framebuffer.
commit 35bc82cee9aab62d556e2ea6dfe29f71ce13dcb3
Author: Andres Rodriguez <andresx7@gmail.com>
Date: Fri Oct 20 10:57:59 2017 -0400
amdgpu: implement context priority for amdgpu_cs_ctx_create2 v3
Add a new context creation function that allows specifying the context
priority.
A high priority context has the potential of starving lower priority
contexts. The current kernel driver implementation allows only apps
that hold CAP_SYS_NICE or DRM_MASTER to acquire a priority above
AMDGPU_CTX_PRIORITY_NORMAL.
v2: corresponding changes for kernel patch v2
v3: Fixed 'make check' symbol error
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index d9f89ef..095c3a0 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -30,6 +30,7 @@ amdgpu_cs_chunk_fence_to_dep
amdgpu_cs_create_semaphore
amdgpu_cs_create_syncobj
amdgpu_cs_ctx_create
+amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 23cde10..ecc975f 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -798,8 +798,9 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
* context will always be executed in order (first come, first serve).
*
*
- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
- * \param context - \c [out] GPU Context handle
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_*
+ * \param context - \c [out] GPU Context handle
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
@@ -807,6 +808,18 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
* \sa amdgpu_cs_ctx_free()
*
*/
+int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
+ uint32_t priority,
+ amdgpu_context_handle *context);
+/**
+ * Create GPU execution Context
+ *
+ * Refer to amdgpu_cs_ctx_create2 for full documentation. This call
+ * is missing the priority parameter.
+ *
+ * \sa amdgpu_cs_ctx_create2()
+ *
+*/
int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
amdgpu_context_handle *context);
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 9577d5c..b9fc01e 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -46,13 +46,14 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
/**
* Create command submission context
*
- * \param dev - \c [in] amdgpu device handle
- * \param context - \c [out] amdgpu context handle
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_*
+ * \param context - \c [out] GPU Context handle
*
* \return 0 on success otherwise POSIX Error code
*/
-int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
- amdgpu_context_handle *context)
+int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, uint32_t priority,
+ amdgpu_context_handle *context)
{
struct amdgpu_context *gpu_context;
union drm_amdgpu_ctx args;
@@ -75,6 +76,8 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
/* Create the context */
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
+ args.in.priority = priority;
+
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
if (r)
goto error;
@@ -94,6 +97,12 @@ error:
return r;
}
+int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
+ amdgpu_context_handle *context)
+{
+ return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context);
+}
+
/**
* Release command submission context
*
commit bcae7226a1c36bee22ad747dc12960e52a706cfa
Author: Andres Rodriguez <andresx7@gmail.com>
Date: Fri Oct 20 10:57:58 2017 -0400
headers: Sync amdgpu_drm.h with drm-next
Generated using make headers_install from:
airlied/drm-next 282dc83 Merge tag 'drm-intel-next-2017-10-12' ...
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 4c6e8c4..ff01818 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -53,6 +53,7 @@ extern "C" {
#define DRM_AMDGPU_WAIT_FENCES 0x12
#define DRM_AMDGPU_VM 0x13
#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
+#define DRM_AMDGPU_SCHED 0x15
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -69,6 +70,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
+#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -91,6 +93,8 @@ extern "C" {
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -166,13 +170,22 @@ union drm_amdgpu_bo_list {
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
+/* Context priority level */
+#define AMDGPU_CTX_PRIORITY_UNSET -2048
+#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
+#define AMDGPU_CTX_PRIORITY_LOW -512
+#define AMDGPU_CTX_PRIORITY_NORMAL 0
+/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
+#define AMDGPU_CTX_PRIORITY_HIGH 512
+#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
+
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
/** For future use, no flags defined so far */
__u32 flags;
__u32 ctx_id;
- __u32 _pad;
+ __s32 priority;
};
union drm_amdgpu_ctx_out {
@@ -216,6 +229,21 @@ union drm_amdgpu_vm {
struct drm_amdgpu_vm_out out;
};
+/* sched ioctl */
+#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
+
+struct drm_amdgpu_sched_in {
+ /* AMDGPU_SCHED_OP_* */
+ __u32 op;
+ __u32 fd;
+ __s32 priority;
+ __u32 flags;
+};
+
+union drm_amdgpu_sched {
+ struct drm_amdgpu_sched_in in;
+};
+
/*
* This is not a reliable API and you should expect it to fail for any
* number of reasons and have fallback path that do not use userptr to
@@ -629,6 +657,7 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
+#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
commit ba68d7bf600125f2755a5b3d6b1a17e8a130ba36
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Wed Oct 11 17:58:11 2017 +0300
modetest: Allow full testing of primary planes
Allow the user to override the default configuration set by setcrtc
for the primary plane. On some hardware primary planes can be freely
positioned/sized, and it'd be nice if we can actually test that feature.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 8ad4766..62d9332 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -1091,7 +1091,8 @@ static int set_plane(struct device *dev, struct plane_arg *p)
if (!format_support(ovr, p->fourcc))
continue;
- if ((ovr->possible_crtcs & (1 << pipe)) && !ovr->crtc_id) {
+ if ((ovr->possible_crtcs & (1 << pipe)) &&
+ (ovr->crtc_id == 0 || ovr->crtc_id == p->crtc_id)) {
plane_id = ovr->plane_id;
break;
}
commit 511c71c868a7b0fac23e1387290554fee1a85434
Author: Kristian H. Kristensen <hoegsberg@chromium.org>
Date: Thu Sep 28 16:02:09 2017 -0700
modetest: Decode IN_FORMATS plane blob property
This teaches modetest about the new IN_FORMATS blob and decodes the
blob to show supported formats and modifiers.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index b8891ff..8ad4766 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -251,6 +251,89 @@ static void dump_blob(struct device *dev, uint32_t blob_id)
drmModeFreePropertyBlob(blob);
}
+static const char *modifier_to_string(uint64_t modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_INVALID:
+ return "INVALID";
+ case DRM_FORMAT_MOD_LINEAR:
+ return "LINEAR";
+ case I915_FORMAT_MOD_X_TILED:
+ return "X_TILED";
+ case I915_FORMAT_MOD_Y_TILED:
+ return "Y_TILED";
+ case I915_FORMAT_MOD_Yf_TILED:
+ return "Yf_TILED";
+ case I915_FORMAT_MOD_Y_TILED_CCS:
+ return "Y_TILED_CCS";
+ case I915_FORMAT_MOD_Yf_TILED_CCS:
+ return "Yf_TILED_CCS";
+ case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
+ return "SAMSUNG_64_32_TILE";
+ case DRM_FORMAT_MOD_VIVANTE_TILED:
+ return "VIVANTE_TILED";
+ case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
+ return "VIVANTE_SUPER_TILED";
+ case DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED:
+ return "VIVANTE_SPLIT_TILED";
+ case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED:
+ return "VIVANTE_SPLIT_SUPER_TILED";
+ case NV_FORMAT_MOD_TEGRA_TILED:
+ return "MOD_TEGRA_TILED";
+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+ return "MOD_TEGRA_16BX2_BLOCK(0)";
+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(1):
+ return "MOD_TEGRA_16BX2_BLOCK(1)";
+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(2):
+ return "MOD_TEGRA_16BX2_BLOCK(2)";
+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(3):
+ return "MOD_TEGRA_16BX2_BLOCK(3)";
+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(4):
+ return "MOD_TEGRA_16BX2_BLOCK(4)";
+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(5):
+ return "MOD_TEGRA_16BX2_BLOCK(5)";
+ case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
+ return "MOD_BROADCOM_VC4_T_TILED";
+ default:
+ return "(UNKNOWN MODIFIER)";
+ }
+}
+
+static void dump_in_formats(struct device *dev, uint32_t blob_id)
+{
+ uint32_t i, j;
+ drmModePropertyBlobPtr blob;
+ struct drm_format_modifier_blob *header;
+ uint32_t *formats;
+ struct drm_format_modifier *modifiers;
+
+ printf("\t\tin_formats blob decoded:\n");
+ blob = drmModeGetPropertyBlob(dev->fd, blob_id);
+ if (!blob) {
+ printf("\n");
+ return;
+ }
+
+ header = blob->data;
+ formats = (uint32_t *) ((char *) header + header->formats_offset);
+ modifiers = (struct drm_format_modifier *)
+ ((char *) header + header->modifiers_offset);
+
+ for (i = 0; i < header->count_formats; i++) {
+ printf("\t\t\t");
+ dump_fourcc(formats[i]);
+ printf(": ");
+ for (j = 0; j < header->count_modifiers; j++) {
+ uint64_t mask = 1ULL << i;
+ if (modifiers[j].formats & mask)
+ printf(" %s", modifier_to_string(modifiers[j].modifier));
+ }
+ printf("\n");
+ }
+
+ drmModeFreePropertyBlob(blob);
+}
+
static void dump_prop(struct device *dev, drmModePropertyPtr prop,
uint32_t prop_id, uint64_t value)
{
@@ -328,6 +411,9 @@ static void dump_prop(struct device *dev, drmModePropertyPtr prop,
printf(" %"PRId64"\n", value);
else
printf(" %"PRIu64"\n", value);
+
+ if (strcmp(prop->name, "IN_FORMATS") == 0)
+ dump_in_formats(dev, value);
}
static void dump_connectors(struct device *dev)
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