mesa: Changes to 'debian-experimental'
VERSION | 2
configure.ac | 2
debian/changelog | 4
src/amd/common/ac_binary.c | 12 +
src/amd/common/ac_binary.h | 2
src/amd/common/ac_nir_to_llvm.c | 18 +
src/amd/vulkan/radv_cmd_buffer.c | 5
src/amd/vulkan/radv_device.c | 10 -
src/amd/vulkan/radv_meta.c | 46 ----
src/amd/vulkan/radv_meta.h | 1
src/amd/vulkan/radv_meta_decompress.c | 102 +++++++---
src/amd/vulkan/radv_meta_resolve.c | 5
src/amd/vulkan/radv_meta_resolve_cs.c | 48 ++++-
src/amd/vulkan/radv_meta_resolve_fs.c | 38 +---
src/amd/vulkan/radv_private.h | 4
src/amd/vulkan/vk_format.h | 23 ++
src/egl/drivers/dri2/platform_x11.c | 1
src/egl/main/eglapi.c | 4
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 1
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 2
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 5
src/gallium/drivers/radeonsi/si_state.c | 12 -
src/intel/isl/isl.c | 131 +-------------
src/intel/vulkan/anv_formats.c | 3
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 -
26 files changed, 232 insertions(+), 270 deletions(-)
New commits:
commit 92e09b47dd65de52d5586a2f71a918d33ef89784
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Aug 15 09:53:27 2017 +0300
upload to experimental, reuse old changelog entry as it's still in NEW
diff --git a/debian/changelog b/debian/changelog
index f9c5cbf..4d9b97b 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (17.2.0~rc3-2) experimental; urgency=medium
+mesa (17.2.0~rc4-1) experimental; urgency=medium
* Migrate mesa to build against libglvnd:
+ patches:
@@ -21,7 +21,7 @@ mesa (17.2.0~rc3-2) experimental; urgency=medium
- GLESv2 libs still get built, purge them from debian/tmp
- Remove lib{EGL,GLX}_mesa.so which are not needed for anything
- -- Timo Aaltonen <tjaalton@debian.org> Thu, 10 Aug 2017 13:40:34 +0300
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 15 Aug 2017 09:44:24 +0300
mesa (17.2.0~rc3-1) experimental; urgency=medium
commit 3165f9877e65efd950b37eb9abc21bed8d13e2f0
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Sat Aug 12 17:04:27 2017 +0100
Update version to 17.2.0-rc4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index fd4078e..c879616 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.2.0-rc3
+17.2.0-rc4
commit 1e11687029372dc0f945d5e7a088b6c3ea75d531
Author: Dave Airlie <airlied@redhat.com>
Date: Wed Jul 26 04:37:53 2017 +0100
radv: force cs/ps/l2 flush at end of command stream. (v2)
This seems like a workaround, but we don't see the bug on CIK/VI.
On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.*
tests, when one tests complete, the first flush at the start of the next
test causes a VM fault as we've destroyed the VM, but we end up flushing
the compute shader then, and it must still be in the process of doing
something.
Could also be a kernel difference between SI and CIK.
v2: hit this with a bigger hammer. This fixes a bunch of hangs
in the vk cts with the robustness tests.
Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 82ba384c10d598bee4786ef5f79e92a0e7b53892)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4b08781..c73b5f4 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2233,8 +2233,11 @@ VkResult radv_EndCommandBuffer(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
- if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
+ if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
si_emit_cache_flush(cmd_buffer);
+ }
if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
cmd_buffer->record_fail)
commit ea595756f80db74cce174a7a2817587189ec7840
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Aug 7 07:39:41 2017 +0100
radv: fix MSAA on SI gpus.
This ports the workaround from radeonsi, that was missing in radv.
This fixes Talos rendering when MSAA is enabled on my Tahiti card.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8bf39307517a04263532e3c5a49b5be1f4a99032)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7cf4b12..47a0c7b 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3079,9 +3079,13 @@ radv_initialise_color_surface(struct radv_device *device,
format != V_028C70_COLOR_24_8) |
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
- if (iview->image->info.samples > 1)
- if (iview->image->fmask.size)
- cb->cb_color_info |= S_028C70_COMPRESSION(1);
+ if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
+ cb->cb_color_info |= S_028C70_COMPRESSION(1);
+ if (device->physical_device->rad_info.chip_class == SI) {
+ unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
+ cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
+ }
+ }
if (iview->image->cmask.size &&
!(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
commit ffd8120284e7592963ed68ffa0775b087530941b
Author: Dave Airlie <airlied@redhat.com>
Date: Fri Aug 4 00:17:34 2017 +0100
radv: fix f16->f32 denorm handling for SI/CIK. (v2)
This just copies the code from the -pro shaders,
and fixes the tests on CIK.
With this CIK passes the same set of conformance
tests as VI.
Fixes: 83e58b03 (radv: flush f32->f16 conversion denormals to zero. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3f389f75b6e9b55467aca681af09b83998ee0e46)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 540976d..5ed7e43 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1315,7 +1315,6 @@ static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
src0 = to_float(&ctx->ac, src0);
result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
- /* TODO SI/CIK options here */
if (ctx->options->chip_class >= VI) {
LLVMValueRef args[2];
/* Check if the result is a denormal - and flush to 0 if so. */
@@ -1329,7 +1328,22 @@ static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
if (ctx->options->chip_class >= VI)
result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
-
+ else {
+ /* for SI/CIK */
+ /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
+ * so compare the result and flush to 0 if it's smaller.
+ */
+ LLVMValueRef temp, cond2;
+ temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
+ ctx->f32, result);
+ cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
+ LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
+ temp, "");
+ cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
+ temp, ctx->f32zero, "");
+ cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
+ result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
+ }
return result;
}
commit 9d65214f3dd7d17403da249af9ea469027a6fe34
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Aug 6 01:58:21 2017 +0200
radv: Use the correct channel for alpha in resolve srgb conversion.
The argument here is a bitmask, so the old code selected .xy, which
got silently truncated to .x when constructing the vec4 from components,
instead of using .w.
Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit acba3a3151dbbba0ab834e062e0feb12af4873de)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index f13e79e..d20d042 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -66,7 +66,7 @@ static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
nir_ssa_def *comp[4];
for (i = 0; i < 3; i++)
comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
- comp[3] = nir_channels(b, input, 3);
+ comp[3] = nir_channels(b, input, 1 << 3);
return nir_vec(b, comp, 4);
}
commit a57390cee01c63bb48402214f65c28298bd4c268
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Aug 6 01:56:17 2017 +0200
radv: Only convert linear->srgb in compute resolves.
It justs works with the fragment shader resolve, so no need to do
a custom conversion. In fact with SRGB dest, it actually gives
wrong results.
Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 15e5a7a6832bba011564bfa2045fba9e833eede2)
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 263181a..af56f49 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -477,48 +477,8 @@ radv_meta_build_nir_fs_noop(void)
return b.shader;
}
-static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
- nir_ssa_def *input)
-{
- nir_const_value v;
- unsigned i;
- v.u32[0] = 0x3b4d2e1c; // 0.00313080009
-
- nir_ssa_def *cmp[3];
- for (i = 0; i < 3; i++)
- cmp[i] = nir_flt(b, nir_channel(b, input, i),
- nir_build_imm(b, 1, 32, v));
-
- nir_ssa_def *ltvals[3];
- v.f32[0] = 12.92;
- for (i = 0; i < 3; i++)
- ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
- nir_build_imm(b, 1, 32, v));
-
- nir_ssa_def *gtvals[3];
-
- for (i = 0; i < 3; i++) {
- v.f32[0] = 1.0/2.4;
- gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
- nir_build_imm(b, 1, 32, v));
- v.f32[0] = 1.055;
- gtvals[i] = nir_fmul(b, gtvals[i],
- nir_build_imm(b, 1, 32, v));
- v.f32[0] = 0.055;
- gtvals[i] = nir_fsub(b, gtvals[i],
- nir_build_imm(b, 1, 32, v));
- }
-
- nir_ssa_def *comp[4];
- for (i = 0; i < 3; i++)
- comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
- comp[3] = nir_channels(b, input, 3);
- return nir_vec(b, comp, 4);
-}
-
void radv_meta_build_resolve_shader_core(nir_builder *b,
bool is_integer,
- bool is_srgb,
int samples,
nir_variable *input_img,
nir_variable *color,
@@ -596,10 +556,4 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
if (outer_if)
b->cursor = nir_after_cf_node(&outer_if->cf_node);
-
- if (is_srgb) {
- nir_ssa_def *newv = nir_load_var(b, color);
- newv = radv_meta_build_resolve_srgb_conversion(b, newv);
- nir_store_var(b, color, newv, 0xf);
- }
}
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index c4a81a2..adc889b 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -234,7 +234,6 @@ nir_shader *radv_meta_build_nir_fs_noop(void);
void radv_meta_build_resolve_shader_core(nir_builder *b,
bool is_integer,
- bool is_srgb,
int samples,
nir_variable *input_img,
nir_variable *color,
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index 832ae7b..f13e79e 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -31,6 +31,45 @@
#include "sid.h"
#include "vk_format.h"
+static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
+ nir_ssa_def *input)
+{
+ nir_const_value v;
+ unsigned i;
+ v.u32[0] = 0x3b4d2e1c; // 0.00313080009
+
+ nir_ssa_def *cmp[3];
+ for (i = 0; i < 3; i++)
+ cmp[i] = nir_flt(b, nir_channel(b, input, i),
+ nir_build_imm(b, 1, 32, v));
+
+ nir_ssa_def *ltvals[3];
+ v.f32[0] = 12.92;
+ for (i = 0; i < 3; i++)
+ ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
+ nir_build_imm(b, 1, 32, v));
+
+ nir_ssa_def *gtvals[3];
+
+ for (i = 0; i < 3; i++) {
+ v.f32[0] = 1.0/2.4;
+ gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
+ nir_build_imm(b, 1, 32, v));
+ v.f32[0] = 1.055;
+ gtvals[i] = nir_fmul(b, gtvals[i],
+ nir_build_imm(b, 1, 32, v));
+ v.f32[0] = 0.055;
+ gtvals[i] = nir_fsub(b, gtvals[i],
+ nir_build_imm(b, 1, 32, v));
+ }
+
+ nir_ssa_def *comp[4];
+ for (i = 0; i < 3; i++)
+ comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
+ comp[3] = nir_channels(b, input, 3);
+ return nir_vec(b, comp, 4);
+}
+
static nir_shader *
build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
{
@@ -88,10 +127,13 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
- radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb, samples,
- input_img, color, img_coord);
+ radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
+ color, img_coord);
nir_ssa_def *outval = nir_load_var(&b, color);
+ if (is_srgb)
+ outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
+
nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
store->src[0] = nir_src_for_ssa(coord);
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index a90678a..2f745f0 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -51,7 +51,7 @@ build_nir_vertex_shader(void)
}
static nir_shader *
-build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
+build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples)
{
nir_builder b;
char name[64];
@@ -62,7 +62,7 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_
false,
GLSL_TYPE_FLOAT);
- snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
+ snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
b.shader->info.name = ralloc_strdup(b.shader, name);
@@ -92,8 +92,8 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, bool is_
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
- radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb,samples,
- input_img, color, img_coord);
+ radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
+ color, img_coord);
nir_ssa_def *outval = nir_load_var(&b, color);
nir_store_var(&b, color_out, outval, 0xf);
@@ -177,31 +177,25 @@ create_resolve_pipeline(struct radv_device *device,
VkFormat format)
{
VkResult result;
- bool is_integer = false, is_srgb = false;
+ bool is_integer = false;
uint32_t samples = 1 << samples_log2;
unsigned fs_key = radv_format_meta_fs_key(format);
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
vi_create_info = &normal_vi_create_info;
if (vk_format_is_int(format))
is_integer = true;
- else if (vk_format_is_srgb(format))
- is_srgb = true;
struct radv_shader_module fs = { .nir = NULL };
- fs.nir = build_resolve_fragment_shader(device, is_integer, is_srgb, samples);
+ fs.nir = build_resolve_fragment_shader(device, is_integer, samples);
struct radv_shader_module vs = {
.nir = build_nir_vertex_shader(),
};
- VkRenderPass *rp = is_srgb ?
- &device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
- &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
+ VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
assert(!*rp);
- VkPipeline *pipeline = is_srgb ?
- &device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
- &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
+ VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
assert(!*pipeline);
VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
@@ -350,8 +344,6 @@ radv_device_init_meta_resolve_fragment_state(struct radv_device *device)
for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
res = create_resolve_pipeline(device, i, pipeline_formats[j]);
}
-
- res = create_resolve_pipeline(device, i, VK_FORMAT_R8G8B8A8_SRGB);
}
return res;
@@ -370,12 +362,6 @@ radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
state->resolve_fragment.rc[i].pipeline[j],
&state->alloc);
}
- radv_DestroyRenderPass(radv_device_to_handle(device),
- state->resolve_fragment.rc[i].srgb_render_pass,
- &state->alloc);
- radv_DestroyPipeline(radv_device_to_handle(device),
- state->resolve_fragment.rc[i].srgb_pipeline,
- &state->alloc);
}
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
@@ -432,9 +418,7 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
push_constants);
unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
- VkPipeline pipeline_h = vk_format_is_srgb(dest_iview->vk_format) ?
- device->meta_state.resolve_fragment.rc[samples_log2].srgb_pipeline :
- device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
+ VkPipeline pipeline_h = device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
pipeline_h);
@@ -485,9 +469,7 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
}
- rp = vk_format_is_srgb(dest_image->vk_format) ?
- device->meta_state.resolve_fragment.rc[samples_log2].srgb_render_pass :
- device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
+ rp = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key];
radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
for (uint32_t r = 0; r < region_count; ++r) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 02de57d..50afc9d 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -433,8 +433,6 @@ struct radv_meta_state {
VkPipelineLayout p_layout;
struct {
- VkRenderPass srgb_render_pass;
- VkPipeline srgb_pipeline;
VkRenderPass render_pass[NUM_META_FS_KEYS];
VkPipeline pipeline[NUM_META_FS_KEYS];
} rc[MAX_SAMPLES_LOG2];
commit 8b706102ebe89984e0d2dce100fb681855c8e056
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun Aug 6 01:47:09 2017 +0200
radv: Don't use SRGB format for image stores during resolve.
These seem to store very bogus results. Luckily there is some code
that converts srgb->linear already, so just making the descriptor
format UNORM should work.
Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8286c3a49f03dc219e57d4a9ec27a4d840c5f603)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index 1eef22a..832ae7b 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -402,7 +402,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(dest_image),
.viewType = radv_meta_get_view_type(dest_image),
- .format = dest_image->vk_format,
+ .format = vk_to_non_srgb_format(dest_image->vk_format),
.subresourceRange = {
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = region->dstSubresource.mipLevel,
diff --git a/src/amd/vulkan/vk_format.h b/src/amd/vulkan/vk_format.h
index c2c7ca4..43265ed 100644
--- a/src/amd/vulkan/vk_format.h
+++ b/src/amd/vulkan/vk_format.h
@@ -465,4 +465,27 @@ vk_format_get_component_bits(VkFormat format,
}
}
+static inline VkFormat
+vk_to_non_srgb_format(VkFormat format)
+{
+ switch(format) {
+ case VK_FORMAT_R8_SRGB :
+ return VK_FORMAT_R8_UNORM;
+ case VK_FORMAT_R8G8_SRGB:
+ return VK_FORMAT_R8G8_UNORM;
+ case VK_FORMAT_R8G8B8_SRGB:
+ return VK_FORMAT_R8G8B8_UNORM;
+ case VK_FORMAT_B8G8R8_SRGB:
+ return VK_FORMAT_B8G8R8_UNORM;
+ case VK_FORMAT_R8G8B8A8_SRGB :
+ return VK_FORMAT_R8G8B8A8_UNORM;
+ case VK_FORMAT_B8G8R8A8_SRGB:
+ return VK_FORMAT_B8G8R8A8_UNORM;
+ case VK_FORMAT_A8B8G8R8_SRGB_PACK32:
+ return VK_FORMAT_A8B8G8R8_UNORM_PACK32;
+ default:
+ return format;
+ }
+}
+
#endif /* VK_FORMAT_H */
commit 7f5d86ebaa854ff3f60ba1a201bc2171d25f558b
Author: Marek Olšák <marek.olsak@amd.com>
Date: Thu Aug 10 22:29:54 2017 +0200
radeonsi/gfx9: use the VI codepath for clamping Z
This fixes corrupted shadows in Unigine Valley.
The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8
for depth.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 27fef5d52d44c8684fa4e7a21bd7a4284f3688ee)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 3b50ca5..76b8f57 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -1400,7 +1400,7 @@ static void tex_fetch_args(
* It's unnecessary if the original texture format was
* Z32_FLOAT, but we don't know that here.
*/
- if (ctx->screen->b.chip_class == VI)
+ if (ctx->screen->b.chip_class >= VI)
z = ac_build_clamp(&ctx->ac, z);
address[count++] = z;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b7f5566..f5d3f1b 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3162,14 +3162,13 @@ si_make_texture_descriptor(struct si_screen *screen,
uint32_t *fmask_state)
{
struct pipe_resource *res = &tex->resource.b.b;
- const struct util_format_description *base_desc, *desc;
+ const struct util_format_description *desc;
unsigned char swizzle[4];
int first_non_void;
unsigned num_format, data_format, type;
uint64_t va;
desc = util_format_description(pipe_format);
- base_desc = util_format_description(res->format);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
@@ -3270,15 +3269,6 @@ si_make_texture_descriptor(struct si_screen *screen,
data_format = 0;
}
- /* Enable clamping for UNORM depth formats promoted to Z32F. */
- if (screen->b.chip_class >= GFX9 &&
- util_format_has_depth(desc) &&
- num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
- util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
- /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
- data_format = V_008F14_IMG_DATA_FORMAT_24_8;
- }
-
/* S8 with Z32 HTILE needs a special format. */
if (screen->b.chip_class >= GFX9 &&
pipe_format == PIPE_FORMAT_S8_UINT &&
commit 1c1653d7b0234395493872ff11206743ce40eb6c
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed Aug 9 11:31:48 2017 -0700
isl: Validate row pitch of stencil surfaces.
Also, silence an obnoxious finishme that started occurring for all
GL applications which use stencil after the i965 ISL conversion.
v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using
separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using
combined depth-stencil.
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 5563872dbfbf733ed56e1b367bc8944ca59b1c3e)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6b4203d..1339867 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1367,8 +1367,13 @@ isl_calc_row_pitch(const struct isl_device *dev,
!pitch_in_range(row_pitch, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info)))
return false;
- if (surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT)
- isl_finishme("validate row pitch of stencil surfaces");
+ const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
+ _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
+ _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
+
+ if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
+ !pitch_in_range(row_pitch, stencil_pitch_bits))
+ return false;
done:
*out_row_pitch = row_pitch;
commit d4100b0d0950d87632e8f65f0583c639c89b7747
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Tue Aug 8 15:55:36 2017 +0100
egl: avoid eglCreatePlatform*Surface{EXT,} crash with invalid dpy
If we have an invalid display fed into the functions, the display lookup
will return NULL. Thus as we attempt to get the platform type, we'll
deref. it leading to a crash.
Keep in mind that this will not happen if Mesa is built without X11 or
when the legacy eglCreate*Surface codepaths are used.
A similar check was added with earlier commit 5e97b8f5ce9 ("egl: Fix
crashes in eglCreate*Surface), although it was only applicable when the
surfaceless platform is built.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 26fbb9eacddb1b809739cb12477bde13501d6d5a)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/egl/main/eglapi.c
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 000368a..16ae741 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -923,7 +923,7 @@ static void *
_fixupNativeWindow(_EGLDisplay *disp, void *native_window)
{
#ifdef HAVE_X11_PLATFORM
- if (disp->Platform == _EGL_PLATFORM_X11 && native_window != NULL) {
+ if (disp && disp->Platform == _EGL_PLATFORM_X11 && native_window != NULL) {
/* The `native_window` parameter for the X11 platform differs between
* eglCreateWindowSurface() and eglCreatePlatformPixmapSurfaceEXT(). In
* eglCreateWindowSurface(), the type of `native_window` is an Xlib
@@ -985,7 +985,7 @@ _fixupNativePixmap(_EGLDisplay *disp, void *native_pixmap)
* `Pixmap*`. Convert `Pixmap*` to `Pixmap` because that's what
* dri2_x11_create_pixmap_surface() expects.
*/
- if (disp->Platform == _EGL_PLATFORM_X11 && native_pixmap != NULL)
+ if (disp && disp->Platform == _EGL_PLATFORM_X11 && native_pixmap != NULL)
return (void *)(* (Pixmap*) native_pixmap);
#endif
return native_pixmap;
commit bb6e5e5476ebaec73a17831cb5c5b883d061560e
Author: Tim Rowley <timothy.o.rowley@intel.com>
Date: Thu Aug 10 12:58:57 2017 -0500
configure: remove trailing "-a" in swr architecture test
Fixes "configure: line 27326: test: argument expected"
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 4d9b0dcccb81ad10113d9aef52b4c84496e879f1)
diff --git a/configure.ac b/configure.ac
index 2736fbf..8d6c967 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2551,7 +2551,7 @@ if test -n "$with_gallium_drivers"; then
if test "x$HAVE_SWR_AVX" != xyes -a \
"x$HAVE_SWR_AVX2" != xyes -a \
"x$HAVE_SWR_KNL" != xyes -a \
- "x$HAVE_SWR_SKX" != xyes -a; then
+ "x$HAVE_SWR_SKX" != xyes; then
AC_MSG_ERROR([swr enabled but no swr architectures selected])
fi
commit 08d49e074dc95cbe04b6090e49ba067a31bb1a84
Author: Marek Olšák <marek.olsak@amd.com>
Date: Wed Aug 9 22:30:28 2017 +0200
ac: fail shader compilation if libelf is replaced by an incompatible version
UE4Editor has this issue.
This commit prevents hangs (release build) or assertion failures (debug
build). It doesn't fix the editor, but catastrophic scenarios are
prevented.
Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 4630ede1021d49c610de1274dc9d1006b843e46b)
diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 618b5cf..1bf52c7 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -109,7 +109,7 @@ static void parse_relocs(Elf *elf, Elf_Data *relocs, Elf_Data *symbols,
}
}
-void ac_elf_read(const char *elf_data, unsigned elf_size,
+bool ac_elf_read(const char *elf_data, unsigned elf_size,
struct ac_shader_binary *binary)
{
char *elf_buffer;
@@ -118,6 +118,7 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
Elf_Data *symbols = NULL, *relocs = NULL;
size_t section_str_index;
unsigned symbol_sh_link = 0;
+ bool success = true;
/* One of the libelf implementations
* (http://www.mr511.de/software/english.htm) requires calling
@@ -137,7 +138,8 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
GElf_Shdr section_header;
if (gelf_getshdr(section, §ion_header) != §ion_header) {
fprintf(stderr, "Failed to read ELF section header\n");
- return;
+ success = false;
+ break;
}
name = elf_strptr(elf, section_str_index, section_header.sh_name);
if (!strcmp(name, ".text")) {
@@ -148,6 +150,11 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
} else if (!strcmp(name, ".AMDGPU.config")) {
section_data = elf_getdata(section, section_data);
binary->config_size = section_data->d_size;
+ if (!binary->config_size) {
+ fprintf(stderr, ".AMDGPU.config is empty!\n");
+ success = false;
+ break;
+ }
binary->config = MALLOC(binary->config_size * sizeof(unsigned char));
memcpy(binary->config, section_data->d_buf, binary->config_size);
} else if (!strcmp(name, ".AMDGPU.disasm")) {
@@ -186,6 +193,7 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
binary->global_symbol_count = 1;
binary->config_size_per_symbol = binary->config_size;
}
+ return success;
}
const unsigned char *ac_shader_binary_config_start(
diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h
index a784a72..45f554e 100644
--- a/src/amd/common/ac_binary.h
+++ b/src/amd/common/ac_binary.h
@@ -83,7 +83,7 @@ struct ac_shader_config {
* Parse the elf binary stored in \p elf_data and create a
* ac_shader_binary object.
*/
-void ac_elf_read(const char *elf_data, unsigned elf_size,
+bool ac_elf_read(const char *elf_data, unsigned elf_size,
struct ac_shader_binary *binary);
/**
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index df37267..7a59c90 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -148,7 +148,10 @@ unsigned si_llvm_compile(LLVMModuleRef M, struct ac_shader_binary *binary,
buffer_size = LLVMGetBufferSize(out_buffer);
buffer_data = LLVMGetBufferStart(out_buffer);
- ac_elf_read(buffer_data, buffer_size, binary);
+ if (!ac_elf_read(buffer_data, buffer_size, binary)) {
+ fprintf(stderr, "radeonsi: cannot read an ELF shader binary\n");
+ diag.retval = 1;
+ }
/* Clean up */
LLVMDisposeMemoryBuffer(out_buffer);
commit 75f5abb82f81d9cb302c0db9862dff8c296811f8
Author: Karol Herbst <karolherbst@gmail.com>
Date: Sun Jul 30 17:51:22 2017 +0200
nv50/ir: fix ConstantFolding with saturation
For mul(a, +-1) codegen can generate OP_MOV with a saturation flag
set which is ignored at emission. The same can happen with add(a, 0),
and others.
Adding an assert for detecting more of such issues.
Fixes wrongly rendered water in Hitman Absolution running under wine.
Also a few shaders in Mad Max and Alien Isolation produce such MOVs.
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
[imirkin: generalize the fix for other cases]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 24a799ad35a824fba94062f9b018f603717ed145)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 14c00bd..58594f0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2006,6 +2006,7 @@ CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
void
CodeEmitterNVC0::emitMOV(const Instruction *i)
{
+ assert(!i->saturate);
if (i->def(0).getFile() == FILE_PREDICATE) {
if (i->src(0).getFile() == FILE_GPR) {
code[0] = 0xfc01c003;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index dac3e6f..cfc0dfc 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1509,6 +1509,14 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
default:
return;
}
+
+ // This can get left behind some of the optimizations which simplify
+ // saturatable values.
+ if (newi->op == OP_MOV && newi->saturate) {
+ newi->saturate = 0;
+ newi->op = OP_SAT;
+ }
+
if (newi->op != op)
foldCount++;
}
commit f0b6298c0505139bed1f15746a3f7be492d36082
Author: Alex Smith <asmith@feralinteractive.com>
Date: Thu Aug 3 15:32:46 2017 +0100
radv: Fix decompression on multisampled depth buffers
Need to take the sample count into account in the depth decompress and
resummarize pipelines and render pass.
Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 2e9a13bf2205b6e96cba408e3f48f1c3fe49634a)
diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
index 7afe08f..f68ce8d 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -29,7 +29,9 @@
#include "sid.h"
static VkResult
-create_pass(struct radv_device *device)
+create_pass(struct radv_device *device,
+ uint32_t samples,
+ VkRenderPass *pass)
{
VkResult result;
VkDevice device_h = radv_device_to_handle(device);
@@ -37,7 +39,7 @@ create_pass(struct radv_device *device)
VkAttachmentDescription attachment;
attachment.format = VK_FORMAT_D32_SFLOAT_S8_UINT;
- attachment.samples = 1;
+ attachment.samples = samples;
attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
attachment.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
attachment.initialLayout = VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
@@ -65,14 +67,18 @@ create_pass(struct radv_device *device)
.dependencyCount = 0,
},
alloc,
- &device->meta_state.depth_decomp.pass);
+ pass);
return result;
}
static VkResult
create_pipeline(struct radv_device *device,
- VkShaderModule vs_module_h)
+ VkShaderModule vs_module_h,
+ uint32_t samples,
+ VkRenderPass pass,
+ VkPipeline *decompress_pipeline,
+ VkPipeline *resummarize_pipeline)
{
VkResult result;
VkDevice device_h = radv_device_to_handle(device);
@@ -129,7 +135,7 @@ create_pipeline(struct radv_device *device,
},
.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
- .rasterizationSamples = 1,
+ .rasterizationSamples = samples,
.sampleShadingEnable = false,
.pSampleMask = NULL,
.alphaToCoverageEnable = false,
@@ -156,7 +162,7 @@ create_pipeline(struct radv_device *device,
VK_DYNAMIC_STATE_SCISSOR,
},
},
- .renderPass = device->meta_state.depth_decomp.pass,
+ .renderPass = pass,
.subpass = 0,
};
@@ -169,7 +175,7 @@ create_pipeline(struct radv_device *device,
.db_flush_stencil_inplace = true,
},
&device->meta_state.alloc,
- &device->meta_state.depth_decomp.decompress_pipeline);
+ decompress_pipeline);
if (result != VK_SUCCESS)
goto cleanup;
@@ -183,7 +189,7 @@ create_pipeline(struct radv_device *device,
.db_resummarize = true,
},
&device->meta_state.alloc,
- &device->meta_state.depth_decomp.resummarize_pipeline);
+ resummarize_pipeline);
Reply to: