libdrm: Changes to 'upstream-unstable'
Android.common.mk | 1
Makefile.am | 1
amdgpu/.editorconfig | 9
amdgpu/Makefile.am | 7
amdgpu/Makefile.sources | 2
amdgpu/amdgpu-symbol-check | 7
amdgpu/amdgpu.h | 85 ++++
amdgpu/amdgpu_asic_id.c | 219 ++++++++++
amdgpu/amdgpu_asic_id.h | 165 -------
amdgpu/amdgpu_cs.c | 85 ++++
amdgpu/amdgpu_device.c | 28 +
amdgpu/amdgpu_internal.h | 10
configure.ac | 6
data/Makefile.am | 23 +
data/amdgpu.ids | 159 +++++++
etnaviv/etnaviv_cmd_stream.c | 8
include/drm/amdgpu_drm.h | 54 ++
include/drm/drm.h | 26 +
include/drm/drm_fourcc.h | 147 +++++++
include/drm/drm_sarea.h | 8
include/drm/vc4_drm.h | 22 -
intel/intel_bufmgr_gem.c | 2
intel/intel_chipset.h | 65 ++-
intel/intel_decode.c | 4
tests/amdgpu/Makefile.am | 5
tests/amdgpu/amdgpu_test.c | 24 -
tests/amdgpu/amdgpu_test.h | 15
tests/amdgpu/cs_tests.c | 7
tests/amdgpu/decode_messages.h | 848 +++++++++++++++++++++++++++++++++++++++++
tests/amdgpu/uvd_messages.h | 813 ---------------------------------------
tests/amdgpu/vcn_tests.c | 410 +++++++++++++++++++
xf86drm.c | 83 +++-
xf86drm.h | 8
33 files changed, 2337 insertions(+), 1019 deletions(-)
New commits:
commit 23e234a3503f51b9d9c585123d33b936f522808d
Author: Lucas Stach <l.stach@pengutronix.de>
Date: Wed Jul 19 10:49:34 2017 +0200
configure.ac: bump version for release
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
diff --git a/configure.ac b/configure.ac
index aa9529c..5a7b1f8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.81],
+ [2.4.82],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit e12af382b5c59f531fddd6e5541f59474ba29ef1
Author: Dave Airlie <airlied@redhat.com>
Date: Wed Jul 19 00:40:38 2017 +0100
amdgpu: add new symbols to tests.
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 81ef9b4..c5b85b5 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -25,14 +25,21 @@ amdgpu_bo_va_op
amdgpu_bo_va_op_raw
amdgpu_bo_wait_for_idle
amdgpu_create_bo_from_user_mem
+amdgpu_cs_chunk_fence_info_to_data
+amdgpu_cs_chunk_fence_to_dep
amdgpu_cs_create_semaphore
+amdgpu_cs_create_syncobj
amdgpu_cs_ctx_create
amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
+amdgpu_cs_destroy_syncobj
+amdgpu_cs_export_syncobj
+amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
+amdgpu_cs_submit_raw
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
commit 22790a65d4a12c43ddbb266cb5985a9ab6b29662
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Jul 18 01:31:27 2017 +0100
drm/amdgpu: add new low overhead command submission API. (v2)
This just sends chunks to the kernel API for a single command
stream.
This should provide a more future proof and extensible API
for command submission.
v2: use amdgpu_bo_list_handle, add two helper functions to
access bo and context internals.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 183f974..238b1aa 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1382,6 +1382,36 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
int shared_fd,
uint32_t *syncobj);
+/**
+ * Submit raw command submission to kernel
+ *
+ * \param dev - \c [in] device handle
+ * \param context - \c [in] context handle for context id
+ * \param bo_list_handle - \c [in] request bo list handle (0 for none)
+ * \param num_chunks - \c [in] number of CS chunks to submit
+ * \param chunks - \c [in] array of CS chunks
+ * \param seq_no - \c [out] output sequence number for submission.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+struct drm_amdgpu_cs_chunk;
+struct drm_amdgpu_cs_chunk_dep;
+struct drm_amdgpu_cs_chunk_data;
+
+int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
+ amdgpu_context_handle context,
+ amdgpu_bo_list_handle bo_list_handle,
+ int num_chunks,
+ struct drm_amdgpu_cs_chunk *chunks,
+ uint64_t *seq_no);
+
+void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
+ struct drm_amdgpu_cs_chunk_dep *dep);
+void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
+ struct drm_amdgpu_cs_chunk_data *data);
+
#ifdef __cplusplus
}
#endif
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 722fd75..dfba875 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -634,3 +634,50 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
}
+
+int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
+ amdgpu_context_handle context,
+ amdgpu_bo_list_handle bo_list_handle,
+ int num_chunks,
+ struct drm_amdgpu_cs_chunk *chunks,
+ uint64_t *seq_no)
+{
+ union drm_amdgpu_cs cs = {0};
+ uint64_t *chunk_array;
+ int i, r;
+ if (num_chunks == 0)
+ return -EINVAL;
+
+ chunk_array = alloca(sizeof(uint64_t) * num_chunks);
+ for (i = 0; i < num_chunks; i++)
+ chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
+ cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
+ cs.in.ctx_id = context->id;
+ cs.in.bo_list_handle = bo_list_handle ? bo_list_handle->handle : 0;
+ cs.in.num_chunks = num_chunks;
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
+ &cs, sizeof(cs));
+ if (r)
+ return r;
+
+ if (seq_no)
+ *seq_no = cs.out.handle;
+ return 0;
+}
+
+void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
+ struct drm_amdgpu_cs_chunk_data *data)
+{
+ data->fence_data.handle = fence_info->handle->handle;
+ data->fence_data.offset = fence_info->offset * sizeof(uint64_t);
+}
+
+void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
+ struct drm_amdgpu_cs_chunk_dep *dep)
+{
+ dep->ip_type = fence->ip_type;
+ dep->ip_instance = fence->ip_instance;
+ dep->ring = fence->ring;
+ dep->ctx_id = fence->context->id;
+ dep->handle = fence->fence;
+}
commit 69532d0188ffa12454bc26bb1c30c52555a984e0
Author: Dave Airlie <airlied@redhat.com>
Date: Sun Jul 16 20:18:40 2017 +0100
drm/amdgpu: add syncobj create/destroy/import/export apis
These are just wrappers using the amdgpu device handle.
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 1901fa8..183f974 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1328,8 +1328,61 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
*/
const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
+/**
+ * Create kernel sync object
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [out] sync object handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
+ uint32_t *syncobj);
+/**
+ * Destroy kernel sync object
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [in] sync object handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
+ uint32_t syncobj);
+
+/**
+ * Export kernel sync object to shareable fd.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [in] sync object handle
+ * \param shared_fd - \c [out] shared file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *shared_fd);
+/**
+ * Import kernel sync object from shareable fd.
+ *
+ * \param dev - \c [in] device handle
+ * \param shared_fd - \c [in] shared file descriptor.
+ * \param syncobj - \c [out] sync object handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
+ int shared_fd,
+ uint32_t *syncobj);
+
#ifdef __cplusplus
}
#endif
-
#endif /* #ifdef _AMDGPU_H_ */
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 868eb7b..722fd75 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -596,3 +596,41 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
{
return amdgpu_cs_unreference_sem(sem);
}
+
+int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
+ uint32_t *handle)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjCreate(dev->fd, 0, handle);
+}
+
+int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
+ uint32_t handle)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjDestroy(dev->fd, handle);
+}
+
+int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
+ uint32_t handle,
+ int *shared_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
+}
+
+int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
+ int shared_fd,
+ uint32_t *handle)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
+}
commit ac214017904b31bc5f80f802d748d5f4f3149d22
Author: coypu <coypu@sdf.org>
Date: Fri Jun 30 03:56:55 2017 +0000
Remove redundant memclear
drmMalloc will zero out the memory for us
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
diff --git a/xf86drm.c b/xf86drm.c
index 2ac3f26..879f85b 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -866,8 +866,6 @@ drmVersionPtr drmGetVersion(int fd)
drmVersionPtr retval;
drm_version_t *version = drmMalloc(sizeof(*version));
- memclear(*version);
-
if (drmIoctl(fd, DRM_IOCTL_VERSION, version)) {
drmFreeKernelVersion(version);
return NULL;
commit 2393acd14487db0b7bedcf5af7b3710066809cbc
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date: Fri Jun 9 12:27:34 2017 +0200
etnaviv: submit full struct drm_etnaviv_gem_submit
It is safe to submit the full struct even on older kernels as such
kernels do not process the full struct. Without this change it
becomes quite challenging to extned the submit struct.
Freedreno has no special treatment too. See git commits
- freedreno: sync uapi header
- freedreno: add fence fd support
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c
index 3c7b0ed..8d0e813 100644
--- a/etnaviv/etnaviv_cmd_stream.c
+++ b/etnaviv/etnaviv_cmd_stream.c
@@ -203,14 +203,8 @@ static void flush(struct etna_cmd_stream *stream, int in_fence_fd,
if (out_fence_fd)
req.flags |= ETNA_SUBMIT_FENCE_FD_OUT;
- /*
- * Pass the complete submit structure only if flags are set. Otherwise,
- * only pass the fields up to, but not including the flags field for
- * backwards compatiblity with older kernels.
- */
ret = drmCommandWriteRead(gpu->dev->fd, DRM_ETNAVIV_GEM_SUBMIT,
- &req, req.flags ? sizeof(req) :
- offsetof(struct drm_etnaviv_gem_submit, flags));
+ &req, sizeof(req));
if (ret)
ERROR_MSG("submit failed: %d (%s)", ret, strerror(errno));
commit 68da7812fc8f859afa7f202f832c72a35c8d4a1d
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Fri Jun 30 14:24:55 2017 -0700
intel/intel_chipset: Move IS_9XX below IS_GEN10.
No functional change. Just organizing the code
so it gets clear for future platforms.
Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 770d21f..3ff59ad 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -499,15 +499,6 @@
IS_GEMINILAKE(devid) || \
IS_COFFEELAKE(devid))
-#define IS_9XX(dev) (IS_GEN3(dev) || \
- IS_GEN4(dev) || \
- IS_GEN5(dev) || \
- IS_GEN6(dev) || \
- IS_GEN7(dev) || \
- IS_GEN8(dev) || \
- IS_GEN9(dev) || \
- IS_GEN10(dev))
-
#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
@@ -525,4 +516,13 @@
#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
+#define IS_9XX(dev) (IS_GEN3(dev) || \
+ IS_GEN4(dev) || \
+ IS_GEN5(dev) || \
+ IS_GEN6(dev) || \
+ IS_GEN7(dev) || \
+ IS_GEN8(dev) || \
+ IS_GEN9(dev) || \
+ IS_GEN10(dev))
+
#endif /* _INTEL_CHIPSET_H */
commit 3095cc8eaba1aa87ad38c04ae2b1eabe30f7e16c
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Thu Apr 27 17:11:09 2017 -0300
intel: add GEN10 to IS_9XX.
As far as I understand, IS_9XX should return true for it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 37579c6..770d21f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -505,7 +505,8 @@
IS_GEN6(dev) || \
IS_GEN7(dev) || \
IS_GEN8(dev) || \
- IS_GEN9(dev))
+ IS_GEN9(dev) || \
+ IS_GEN10(dev))
#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
commit 5c490bd6854a5b265aaa62ef62926c3ac97092c7
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Wed Aug 24 14:51:43 2016 -0700
intel/gen10: Add missed gen10 stuff
This got lost on rebase, I believe
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 45a26da..71f140f 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3662,6 +3662,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->gen = 8;
else if (IS_GEN9(bufmgr_gem->pci_device))
bufmgr_gem->gen = 9;
+ else if (IS_GEN10(bufmgr_gem->pci_device))
+ bufmgr_gem->gen = 10;
else {
free(bufmgr_gem);
bufmgr_gem = NULL;
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2721ffd..3a81500 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3827,7 +3827,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
ctx->devid = devid;
ctx->out = stdout;
- if (IS_GEN9(devid))
+ if (IS_GEN10(devid))
+ ctx->gen = 10;
+ else if (IS_GEN9(devid))
ctx->gen = 9;
else if (IS_GEN8(devid))
ctx->gen = 8;
commit 80201d706712bd87f1bac8b7493bd784acd4a764
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Mon Dec 12 16:06:03 2016 -0800
intel: Add Cannonlake PCI IDs for Y-skus.
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e6b49d7..37579c6 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -237,6 +237,12 @@
#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
+#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
+#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
+#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
+#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
+#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
+#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -501,12 +507,20 @@
IS_GEN8(dev) || \
IS_GEN9(dev))
+#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
+
#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
(devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
(devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
(devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
-#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
+#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
+ IS_CNL_Y(devid))
#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
commit 6b624bf3c394e1883314925c65c7ed1e98f3639f
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Mon Dec 12 16:06:02 2016 -0800
intel: Add Cannonlake PCI IDs for U-skus.
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")
v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 891b50f..e6b49d7 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -233,6 +233,11 @@
#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
+#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
+#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
+#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
+#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
+
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
@@ -496,5 +501,13 @@
IS_GEN8(dev) || \
IS_GEN9(dev))
+#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
+ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
+ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
+ (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
+
+#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
+
+#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
#endif /* _INTEL_CHIPSET_H */
commit 4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34
Author: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Wed Jun 21 11:17:37 2017 -0700
intel: PCI Ids for U SKU in CFL
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index fed5a0d..891b50f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -228,6 +228,10 @@
#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -469,8 +473,14 @@
#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
+
#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
- IS_CFL_H(devid))
+ IS_CFL_H(devid) || \
+ IS_CFL_U(devid))
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid) || \
commit 2b48faf30e03cdafccffd7d6c6a715c2f969fc31
Author: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Wed Jun 21 11:17:36 2017 -0700
intel: PCI Ids for H SKU in CFL
Add the PCI IDs for H SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index aeb72ba..fed5a0d 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -226,6 +226,8 @@
#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
+#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
+#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -464,7 +466,11 @@
(devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
(devid) == PCI_CHIP_COFFEELAKE_S_GT2_3)
-#define IS_COFFEELAKE(devid) (IS_CFL_S(devid))
+#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
+
+#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
+ IS_CFL_H(devid))
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid) || \
commit 0733f376ae93f7580be1641d8ebc644561d438f4
Author: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Wed Jun 21 11:17:35 2017 -0700
intel: PCI Ids for S SKU in CFL
Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 41fc0da..aeb72ba 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -221,6 +221,12 @@
#define PCI_CHIP_GLK 0x3184
#define PCI_CHIP_GLK_2X6 0x3185
+#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
+#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
+#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
+#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
+#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
+
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
@@ -452,10 +458,19 @@
#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
(devid) == PCI_CHIP_GLK_2X6)
+#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3)
+
+#define IS_COFFEELAKE(devid) (IS_CFL_S(devid))
+
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid) || \
IS_KABYLAKE(devid) || \
- IS_GEMINILAKE(devid))
+ IS_GEMINILAKE(devid) || \
+ IS_COFFEELAKE(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
commit fc4922793f1871577bb44b1d69ec3801acb23eb6
Author: Dave Airlie <airlied@redhat.com>
Date: Sat Jun 17 11:01:01 2017 +1000
libdrm: add drm syncobj create/destroy/import/export
These ioctls are now in drm next so add the first set of libdrm APIs.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/xf86drm.c b/xf86drm.c
index 728ac78..2ac3f26 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4146,3 +4146,84 @@ char *drmGetDeviceNameFromFd2(int fd)
return strdup(node);
#endif
}
+
+int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle)
+{
+ struct drm_syncobj_create args;
+ int ret;
+
+ memclear(args);
+ args.flags = flags;
+ args.handle = 0;
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &args);
+ if (ret)
+ return ret;
+ *handle = args.handle;
+ return 0;
+}
+
+int drmSyncobjDestroy(int fd, uint32_t handle)
+{
+ struct drm_syncobj_destroy args;
+
+ memclear(args);
+ args.handle = handle;
+ return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &args);
+}
+
+int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd)
+{
+ struct drm_syncobj_handle args;
+ int ret;
+
+ memclear(args);
+ args.fd = -1;
+ args.handle = handle;
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args);
+ if (ret)
+ return ret;
+ *obj_fd = args.fd;
+ return 0;
+}
+
+int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle)
+{
+ struct drm_syncobj_handle args;
+ int ret;
+
+ memclear(args);
+ args.fd = obj_fd;
+ args.handle = 0;
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, &args);
+ if (ret)
+ return ret;
+ *handle = args.handle;
+ return 0;
+}
+
+int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd)
+{
+ struct drm_syncobj_handle args;
+
+ memclear(args);
+ args.fd = sync_file_fd;
+ args.handle = handle;
+ args.flags = DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE;
+ return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, &args);
+}
+
+int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd)
+{
+ struct drm_syncobj_handle args;
+ int ret;
+
+ memclear(args);
+ args.fd = -1;
+ args.handle = handle;
+ args.flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE;
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, &args);
+ if (ret)
+ return ret;
+ *sync_file_fd = args.fd;
+ return 0;
+}
diff --git a/xf86drm.h b/xf86drm.h
index 74f54f1..2855a3e 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -853,6 +853,14 @@ extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_device
extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b);
+extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);
+extern int drmSyncobjDestroy(int fd, uint32_t handle);
+extern int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd);
+extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle);
+
+extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd);
+extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd);
+
#if defined(__cplusplus)
}
#endif
commit 3832374dafb8d0b1b69d8856be28352514afab5d
Author: Dave Airlie <airlied@redhat.com>
Date: Thu Jun 29 05:27:39 2017 +1000
drm: update drm.h to latest in drm-next.
This syncs the drm.h header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
It brings over the semaphore API changes.
Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.
[airlied: I split patch in two, split reviewed by across both]
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 1e7a4bc..bf3674a 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -642,6 +642,7 @@ struct drm_gem_open {
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
+#define DRM_CAP_SYNCOBJ 0x13
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
@@ -691,6 +692,26 @@ struct drm_prime_handle {
__s32 fd;
};
+struct drm_syncobj_create {
+ __u32 handle;
+ __u32 flags;
+};
+
+struct drm_syncobj_destroy {
+ __u32 handle;
+ __u32 pad;
+};
+
+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
+struct drm_syncobj_handle {
+ __u32 handle;
+ __u32 flags;
+
+ __s32 fd;
+ __u32 pad;
+};
+
#if defined(__cplusplus)
}
#endif
@@ -809,6 +830,11 @@ extern "C" {
#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
+#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
+#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
+#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
+
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
commit 92b5b308ca2fec356dd29bb2f27d88a5aff61798
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Jun 27 12:56:25 2017 +1000
amdgpu: sync amdgpu_drm with kernel.
This syncs the amdgpu_drm header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
It brings over the VM and semaphore API changes.
Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 8cfe68c..d9aa4a3 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -51,6 +51,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_OP 0x10
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
+#define DRM_AMDGPU_VM 0x13
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -65,6 +66,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
+#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -190,6 +192,26 @@ union drm_amdgpu_ctx {
union drm_amdgpu_ctx_out out;
};
+/* vm ioctl */
+#define AMDGPU_VM_OP_RESERVE_VMID 1
+#define AMDGPU_VM_OP_UNRESERVE_VMID 2
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