mesa: Changes to 'debian-unstable'
VERSION | 2
bin/.cherry-ignore | 3
debian/changelog | 11
debian/control | 2
docs/relnotes/17.1.4.html | 3
docs/relnotes/17.1.5.html | 202 +++++++++++++++
scons/gallium.py | 4
src/amd/common/ac_nir_to_llvm.c | 94 ++++--
src/amd/vulkan/radv_pipeline.c | 1
src/compiler/glsl/ast_to_hir.cpp | 2
src/compiler/glsl/builtin_functions.cpp | 13
src/compiler/glsl/builtin_functions.h | 3
src/compiler/glsl/builtin_variables.cpp | 16 -
src/compiler/glsl/linker.cpp | 6
src/compiler/spirv/spirv_to_nir.c | 7
src/compiler/spirv/vtn_alu.c | 67 ++++
src/gallium/auxiliary/draw/draw_pipe_validate.c | 7
src/gallium/drivers/etnaviv/etnaviv_compiler.c | 60 ++--
src/gallium/drivers/etnaviv/etnaviv_resource.c | 10
src/gallium/drivers/etnaviv/etnaviv_screen.c | 1
src/gallium/drivers/radeon/r600_texture.c | 24 +
src/gallium/drivers/svga/svga_resource_texture.c | 15 -
src/gallium/drivers/svga/svga_screen.c | 13
src/gallium/drivers/svga/svga_screen_cache.c | 3
src/gallium/drivers/svga/svga_state_framebuffer.c | 2
src/gallium/drivers/swr/rasterizer/common/os.h | 6
src/gallium/drivers/swr/rasterizer/common/simd16intrin.h | 4
src/gallium/drivers/swr/rasterizer/core/api.cpp | 6
src/gallium/drivers/swr/rasterizer/core/threads.cpp | 4
src/gallium/drivers/swr/swr_screen.cpp | 6
src/gallium/state_trackers/va/subpicture.c | 1
src/gallium/state_trackers/wgl/stw_pixelformat.c | 36 ++
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2
src/intel/Makefile.common.am | 5
src/intel/isl/isl.c | 25 +
src/intel/isl/isl.h | 2
src/mesa/drivers/dri/i965/brw_sf_state.c | 2
src/mesa/drivers/dri/i965/gen6_sf_state.c | 3
src/mesa/main/blit.c | 12
src/mesa/state_tracker/st_cb_eglimage.c | 1
41 files changed, 556 insertions(+), 133 deletions(-)
New commits:
commit 539c65c9cdab0d2000d66faac1eddb7c2f81399e
Author: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat Jul 15 00:35:51 2017 -0700
debian/changelog: Use team upload for lintian changelog-should-mention-nmu
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
diff --git a/debian/changelog b/debian/changelog
index 1e96ca9..da32935 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,8 @@
mesa (17.1.5-1) UNRELEASED; urgency=medium
+ * Team upload.
+
+ [ Jordan Justen ]
* New upstream release.
* Update Standards-Version to 4.0.0 for lintian
out-of-date-standards-version
commit 95b6b7ccb004a5cb4335c0b094fb72d6bfae7c98
Author: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat Jul 15 00:29:14 2017 -0700
debian: Update Standards-Version to 4.0.0 for lintian out-of-date-standards-version
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
diff --git a/debian/changelog b/debian/changelog
index 7cef0e8..1e96ca9 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,8 @@
mesa (17.1.5-1) UNRELEASED; urgency=medium
* New upstream release.
+ * Update Standards-Version to 4.0.0 for lintian
+ out-of-date-standards-version
-- Jordan Justen <jordan.l.justen@intel.com> Sat, 15 Jul 2017 00:22:19 -0700
diff --git a/debian/control b/debian/control
index 74d63b9..41f3394 100644
--- a/debian/control
+++ b/debian/control
@@ -3,7 +3,7 @@ Section: graphics
Priority: optional
Maintainer: Debian X Strike Force <debian-x@lists.debian.org>
Uploaders: Andreas Boll <andreas.boll.dev@gmail.com>
-Standards-Version: 3.9.8
+Standards-Version: 4.0.0
Build-Depends:
debhelper (>= 9),
dh-autoreconf,
commit a613d703a6a5a940dbfe05c03ef6b599792bc481
Author: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat Jul 15 00:24:07 2017 -0700
debian: Start new 17.1.5-1 changelog entry
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
diff --git a/debian/changelog b/debian/changelog
index 099fc96..7cef0e8 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.1.5-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Jordan Justen <jordan.l.justen@intel.com> Sat, 15 Jul 2017 00:22:19 -0700
+
mesa (17.1.4-1) unstable; urgency=medium
* New upstream release.
commit 2542ddd4dcf2e7029120982d15f787e525b1d45f
Author: Andres Gomez <agomez@igalia.com>
Date: Fri Jul 14 21:58:05 2017 +0300
docs: add release notes for 17.1.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/docs/relnotes/17.1.5.html b/docs/relnotes/17.1.5.html
new file mode 100644
index 0000000..3dd79b0
--- /dev/null
+++ b/docs/relnotes/17.1.5.html
@@ -0,0 +1,202 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.5 Release Notes / July 14, 2017</h1>
+
+<p>
+Mesa 17.1.5 is a bug fix release which fixes bugs found since the 17.1.4 release.
+</p>
+<p>
+Mesa 17.1.5 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100242";>Bug 100242</a> - radeon buffer allocation failure during startup of Factorio</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101657";>Bug 101657</a> - strtod.c:32:10: fatal error: xlocale.h: No such file or directory</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101666";>Bug 101666</a> - bitfieldExtract is marked as a built-in function on OpenGL ES 3.0, but was added in OpenGL ES 3.1</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101703";>Bug 101703</a> - No stencil buffer allocated when requested by GLUT</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Aaron Watry (1):</p>
+<ul>
+ <li>radeon/winsys: Limit max allocation size to 70% of VRAM</li>
+</ul>
+
+<p>Aleksander Morgado (2):</p>
+<ul>
+ <li>etnaviv: fix refcnt initialization in etna_screen</li>
+ <li>etnaviv: don't dereference etna_resource pointer if allocation fails</li>
+</ul>
+
+<p>Alex Smith (2):</p>
+<ul>
+ <li>ac/nir: Use correct LLVM intrinsics for atomic ops on imageBuffers</li>
+ <li>ac/nir: Fix ordering of parameters for image atomic cmpswap intrinsics</li>
+</ul>
+
+<p>Andres Gomez (3):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.1.4</li>
+ <li>cherry-ignore: i965: Fix anisotropic filtering for mag filter</li>
+ <li>Update version to 17.1.5</li>
+</ul>
+
+<p>Anuj Phogat (2):</p>
+<ul>
+ <li>intel/isl: Use uint64_t to store total surface size</li>
+ <li>intel/isl: Add the maximum surface size limit</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+ <li>draw: check for line_width != 1.0f in validate_pipeline()</li>
+ <li>svga: clamp device line width to at least 1 to fix HWv8 line stippling</li>
+ <li>svga: fix PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE value</li>
+</ul>
+
+<p>Bruce Cherniak (1):</p>
+<ul>
+ <li>swr: Limit memory held by defer deleted resources.</li>
+</ul>
+
+<p>Chandu Babu N (1):</p>
+<ul>
+ <li>st/va: Fix leak in VAAPI subpictures</li>
+</ul>
+
+<p>Charmaine Lee (1):</p>
+<ul>
+ <li>svga: fixed surface size to include array size</li>
+</ul>
+
+<p>Connor Abbott (2):</p>
+<ul>
+ <li>spirv: fix OpBitcast when the src and dst bitsize are different (v3)</li>
+ <li>ac/nir: implement 64-bit packing and unpacking</li>
+</ul>
+
+<p>Iago Toral Quiroga (1):</p>
+<ul>
+ <li>glsl: gl_Max{Vertex,Fragment}UniformComponents exist in all desktop GL versions</li>
+</ul>
+
+<p>Ilia Mirkin (1):</p>
+<ul>
+ <li>glsl: check if any of the named builtins are available first</li>
+</ul>
+
+<p>James Legg (2):</p>
+<ul>
+ <li>ac/nir: Make intrinsic_name buffer long enough</li>
+ <li>spirv: Fix reaching unreachable for compare exchange on images</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+ <li>nir/spirv: Use the type from the deref for atomics</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+ <li>glsl: do not call link_xfb_stride_layout_qualifiers() for fragment shaders</li>
+</ul>
+
+<p>Kenneth Graunke (2):</p>
+<ul>
+ <li>i965: Use true AA line distance on G45/Ironlake.</li>
+ <li>i965: Always set AALINEDISTANCE_TRUE on Sandybridge.</li>
+</ul>
+
+<p>Lucas Stach (1):</p>
+<ul>
+ <li>etnaviv: fix shader miscompilation with more than 16 labels</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+ <li>gallium/radeon: fix a possible crash for buffer exports</li>
+</ul>
+
+<p>Neha Bhende (1):</p>
+<ul>
+ <li>svga: loop over box.depth for ReadBack_image on each slice</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+ <li>winsys/radeon: only call pb_slabs_reclaim when slabs are actually used</li>
+</ul>
+
+<p>Olivier Lauffenburger (1):</p>
+<ul>
+ <li>st/wgl: improve selection of pixel format</li>
+</ul>
+
+<p>Philipp Zabel (1):</p>
+<ul>
+ <li>st/mesa: release EGLImage on EGLImageTarget* error</li>
+</ul>
+
+<p>Plamena Manolova (1):</p>
+<ul>
+ <li>mesa/main: Move NULL pointer check.</li>
+</ul>
+
+<p>Tim Rowley (2):</p>
+<ul>
+ <li>swr/rast: _mm*_undefined_* implementations for gcc<4.9</li>
+ <li>swr/rast: Correctly allocate SWR_STATS memory as cacheline aligned</li>
+</ul>
+
+<p>Tomasz Figa (1):</p>
+<ul>
+ <li>intel: common: Fix link failure with standalone Android build</li>
+</ul>
+
+<p>Vinson Lee (1):</p>
+<ul>
+ <li>scons: Check for xlocale.h before defining HAVE_XLOCALE_H.</li>
+</ul>
+
+</div>
+</body>
+</html>
commit 3a8cc82fefdcb567bde4bb2eca3ff610b5696bde
Author: Andres Gomez <agomez@igalia.com>
Date: Fri Jul 14 21:53:00 2017 +0300
Update version to 17.1.5
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/VERSION b/VERSION
index e7bcd48..6729eea 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.1.4
+17.1.5
commit 8164345b77a8e1538a070796c659a07539b5ab7f
Author: James Legg <jlegg@feralinteractive.com>
Date: Mon Jun 26 10:46:23 2017 +0100
spirv: Fix reaching unreachable for compare exchange on images
We were hitting the
unreachable("Invalid image opcode")
near the end of vtn_handle_image when parsing the
SpvOpAtomicCompareExchange opcode.
v2: Add stable CC.
v3: Ignore SpvOpAtomicCompareExchangeWeak. It requires the Kernel
capability which is not exposed in Vulkan, and spirv_to_nir is not used
for OpenCL which does support it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit b117f59710e62f4afa5781c554f8113e2b0df9cc)
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 1398184..2a13636 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1977,6 +1977,7 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
intrin->src[2] = nir_src_for_ssa(vtn_ssa_value(b, w[3])->def);
break;
+ case SpvOpAtomicCompareExchange:
case SpvOpAtomicIIncrement:
case SpvOpAtomicIDecrement:
case SpvOpAtomicExchange:
commit 8d0fa95bf222153cb5c8919c93a5011e0ca59ddc
Author: Brian Paul <brianp@vmware.com>
Date: Mon Jul 10 08:36:15 2017 -0600
svga: fix PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE value
This query is supposed to return the max texture buffer size/width in
texels, not size in bytes. Divide by 16 (the largest format size) to
return texels.
Fixes Piglit arb_texture_buffer_object-max-size test.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by :Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit 3b28eaabf603657c388caa72bc92b1b660d00b2a)
diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
index 9be806d..07f3346 100644
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -303,7 +303,10 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
return svgascreen->ms_samples ? 1 : 0;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- return SVGA3D_DX_MAX_RESOURCE_SIZE;
+ /* convert bytes to texels for the case of the largest texel
+ * size: float[4].
+ */
+ return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
case PIPE_CAP_MIN_TEXEL_OFFSET:
return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
commit 82aff6ad188db4703e55593e136e45824f7e9ad9
Author: Olivier Lauffenburger <o.lauffenburger@topsolid.com>
Date: Thu Jul 6 09:08:00 2017 -0600
st/wgl: improve selection of pixel format
Current selection of pixel format does not enforce the request of
stencil or depth buffer if the color depth is not the same as
requested.
For instance, GLUT requests a 32-bit color buffer with an 8-bit
stencil buffer, but because color buffers are only 24-bit, no
priority is given to creating a stencil buffer.
This patch gives more priority to the creation of requested buffers
and less priority to the difference in bit depth.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101703
Signed-off-by: Olivier Lauffenburger <o.lauffenburger@topsolid.com>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 80c6598cdba36edb43d618f97175103e560d61a1)
diff --git a/src/gallium/state_trackers/wgl/stw_pixelformat.c b/src/gallium/state_trackers/wgl/stw_pixelformat.c
index 8407b9e..c924f76 100644
--- a/src/gallium/state_trackers/wgl/stw_pixelformat.c
+++ b/src/gallium/state_trackers/wgl/stw_pixelformat.c
@@ -442,17 +442,39 @@ int stw_pixelformat_choose( HDC hdc,
!!(pfi->pfd.dwFlags & PFD_DOUBLEBUFFER))
continue;
- /* FIXME: Take in account individual channel bits */
- if (ppfd->cColorBits != pfi->pfd.cColorBits)
- delta += 8;
+ /* Selection logic:
+ * - Enabling a feature (depth, stencil...) is given highest priority.
+ * - Giving as many bits as requested is given medium priority.
+ * - Giving no more bits than requested is given lowest priority.
+ */
- if (ppfd->cDepthBits != pfi->pfd.cDepthBits)
- delta += 4;
+ /* FIXME: Take in account individual channel bits */
+ if (ppfd->cColorBits && !pfi->pfd.cColorBits)
+ delta += 10000;
+ else if (ppfd->cColorBits > pfi->pfd.cColorBits)
+ delta += 100;
+ else if (ppfd->cColorBits < pfi->pfd.cColorBits)
+ delta++;
- if (ppfd->cStencilBits != pfi->pfd.cStencilBits)
+ if (ppfd->cDepthBits && !pfi->pfd.cDepthBits)
+ delta += 10000;
+ else if (ppfd->cDepthBits > pfi->pfd.cDepthBits)
+ delta += 200;
+ else if (ppfd->cDepthBits < pfi->pfd.cDepthBits)
delta += 2;
- if (ppfd->cAlphaBits != pfi->pfd.cAlphaBits)
+ if (ppfd->cStencilBits && !pfi->pfd.cStencilBits)
+ delta += 10000;
+ else if (ppfd->cStencilBits > pfi->pfd.cStencilBits)
+ delta += 400;
+ else if (ppfd->cStencilBits < pfi->pfd.cStencilBits)
+ delta++;
+
+ if (ppfd->cAlphaBits && !pfi->pfd.cAlphaBits)
+ delta += 10000;
+ else if (ppfd->cAlphaBits > pfi->pfd.cAlphaBits)
+ delta += 100;
+ else if (ppfd->cAlphaBits < pfi->pfd.cAlphaBits)
delta++;
if (delta < bestdelta) {
commit 729b999e351283b398e17d042dc1ef91ed4155cb
Author: Charmaine Lee <charmainel@vmware.com>
Date: Tue Jun 6 11:52:50 2017 -0700
svga: fixed surface size to include array size
This patch fixes the total surface size in surface cache
to include array size as well.
Tested with MTT glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit adead35320c0afe95f3f170a6047905179f8c6c3)
diff --git a/src/gallium/drivers/svga/svga_screen_cache.c b/src/gallium/drivers/svga/svga_screen_cache.c
index d0255fa..86c9798 100644
--- a/src/gallium/drivers/svga/svga_screen_cache.c
+++ b/src/gallium/drivers/svga/svga_screen_cache.c
@@ -48,6 +48,7 @@ surface_size(const struct svga_host_surface_cache_key *key)
assert(key->numMipLevels > 0);
assert(key->numFaces > 0);
+ assert(key->arraySize > 0);
if (key->format == SVGA3D_BUFFER) {
/* Special case: we don't want to count vertex/index buffers
@@ -68,7 +69,7 @@ surface_size(const struct svga_host_surface_cache_key *key)
total_size += img_size;
}
- total_size *= key->numFaces;
+ total_size *= key->numFaces * key->arraySize;
return total_size;
}
commit 759d84177e87cc82afadeca7953c47848668fda0
Author: Neha Bhende <bhenden@vmware.com>
Date: Thu Oct 27 12:35:03 2016 -0700
svga: loop over box.depth for ReadBack_image on each slice
piglit test ext_texture_array-gen-mipmap is fixed with this patch.
Tested with mtt piglit, glretrace, viewperf and conform. No regression.
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 31fe1d10b291bcd1b9ee376d53db05028719831d)
diff --git a/src/gallium/drivers/svga/svga_resource_texture.c b/src/gallium/drivers/svga/svga_resource_texture.c
index 20580e9..11a8749 100644
--- a/src/gallium/drivers/svga/svga_resource_texture.c
+++ b/src/gallium/drivers/svga/svga_resource_texture.c
@@ -410,7 +410,7 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
struct svga_texture *tex = svga_texture(texture);
struct svga_winsys_surface *surf = tex->handle;
unsigned level = st->base.level;
- unsigned w, h, nblocksx, nblocksy;
+ unsigned w, h, nblocksx, nblocksy, i;
unsigned usage = st->base.usage;
if (need_tex_readback(transfer)) {
@@ -418,13 +418,14 @@ svga_texture_transfer_map_direct(struct svga_context *svga,
svga_surfaces_flush(svga);
- if (svga_have_vgpu10(svga)) {
- ret = readback_image_vgpu10(svga, surf, st->slice, level,
- tex->b.b.last_level + 1);
- } else {
- ret = readback_image_vgpu9(svga, surf, st->slice, level);
+ for (i = 0; i < st->base.box.depth; i++) {
+ if (svga_have_vgpu10(svga)) {
+ ret = readback_image_vgpu10(svga, surf, st->slice + i, level,
+ tex->b.b.last_level + 1);
+ } else {
+ ret = readback_image_vgpu9(svga, surf, st->slice + i, level);
+ }
}
-
svga->hud.num_readbacks++;
SVGA_STATS_COUNT_INC(sws, SVGA_STATS_COUNT_TEXREADBACK);
commit c36c8ec52808eb55bf1517a7beaaacc955c1e612
Author: Juan A. Suarez Romero <jasuarez@igalia.com>
Date: Thu Jun 22 12:47:57 2017 +0200
glsl: do not call link_xfb_stride_layout_qualifiers() for fragment shaders
xfb only applies to the latest stage before the fragment shader, so
there is no need to invoke it in the fragment shader.
Fixes:
KHR-GL45.enhanced_layouts.xfb_stride_of_empty_list
KHR-GL45.enhanced_layouts.xfb_stride_of_empty_list_and_api
v2: do reset only if shaders provide an explicit stride
v3: do not call link_xfb_stride_layout_qualifiers() for fragment shaders
(Timothy)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 860919a3b237386cba5b2951ae520bf6734fd17e)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 7ace01d..97eca76 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -2221,8 +2221,10 @@ link_intrastage_shaders(void *mem_ctx,
link_tes_in_layout_qualifiers(prog, gl_prog, shader_list, num_shaders);
link_gs_inout_layout_qualifiers(prog, gl_prog, shader_list, num_shaders);
link_cs_input_layout_qualifiers(prog, gl_prog, shader_list, num_shaders);
- link_xfb_stride_layout_qualifiers(ctx, prog, linked, shader_list,
- num_shaders);
+
+ if (linked->Stage != MESA_SHADER_FRAGMENT)
+ link_xfb_stride_layout_qualifiers(ctx, prog, linked, shader_list,
+ num_shaders);
populate_symbol_table(linked);
commit 7bcb63457ba9a696ff023a3871baf61c3d1bbd05
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Fri May 19 12:09:22 2017 -0700
intel/isl: Add the maximum surface size limit
V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and
2^38 bytes for gen9+.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit c07271fef095164c8bcfb54fdc95567c3774a866)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 32aa698..8cb139c 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1398,6 +1398,28 @@ isl_surf_init_s(const struct isl_device *dev,
base_alignment = MAX(info->min_alignment, tile_size);
}
+ if (ISL_DEV_GEN(dev) < 9) {
+ /* From the Broadwell PRM Vol 5, Surface Layout:
+ *
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size in bytes. This
+ * maximum is 2 GB for all products and all surface types."
+ *
+ * This comment is applicable to all Pre-gen9 platforms.
+ */
+ if (size > (uint64_t) 1 << 31)
+ return false;
+ } else {
+ /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size of 2^38 bytes.
+ * All pixels within the surface must be contained within 2^38 bytes
+ * of the base address."
+ */
+ if (size > (uint64_t) 1 << 38)
+ return false;
+ }
+
*surf = (struct isl_surf) {
.dim = info->dim,
.dim_layout = dim_layout,
commit 7fc94625cca0d9f5997252b0598bc4e0e6b9597a
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Fri May 19 13:47:12 2017 -0700
intel/isl: Use uint64_t to store total surface size
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit 70229782370c7ed9a63e05689f4d8bfc80128dd9)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f89f351..32aa698 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1362,7 +1362,8 @@ isl_surf_init_s(const struct isl_device *dev,
&phys_slice0_sa, &row_pitch))
return false;
- uint32_t size, base_alignment;
+ uint32_t base_alignment;
+ uint64_t size;
if (tiling == ISL_TILING_LINEAR) {
size = row_pitch * total_h_el + pad_bytes;
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 7778551..c9970bc 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -868,7 +868,7 @@ struct isl_surf {
uint32_t samples;
/** Total size of the surface, in bytes. */
- uint32_t size;
+ uint64_t size;
/** Required alignment for the surface's base address. */
uint32_t alignment;
commit 9e0ef936918f3a6b940f0a1509c1b7dd09bdc3d9
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Jun 27 19:24:20 2017 +0200
gallium/radeon: fix a possible crash for buffer exports
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit e6dbe975eff8e23992c9d9a72ce302896b5fecfc)
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 3ee1a20..4b20825 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -590,16 +590,22 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
res->external_usage = usage;
}
- if (rscreen->chip_class >= GFX9) {
- offset = rtex->surface.u.gfx9.surf_offset;
- stride = rtex->surface.u.gfx9.surf_pitch *
- rtex->surface.bpe;
- slice_size = rtex->surface.u.gfx9.surf_slice_size;
+ if (res->b.b.target == PIPE_BUFFER) {
+ offset = 0;
+ stride = 0;
+ slice_size = 0;
} else {
- offset = rtex->surface.u.legacy.level[0].offset;
- stride = rtex->surface.u.legacy.level[0].nblk_x *
- rtex->surface.bpe;
- slice_size = rtex->surface.u.legacy.level[0].slice_size;
+ if (rscreen->chip_class >= GFX9) {
+ offset = rtex->surface.u.gfx9.surf_offset;
+ stride = rtex->surface.u.gfx9.surf_pitch *
+ rtex->surface.bpe;
+ slice_size = rtex->surface.u.gfx9.surf_slice_size;
+ } else {
+ offset = rtex->surface.u.legacy.level[0].offset;
+ stride = rtex->surface.u.legacy.level[0].nblk_x *
+ rtex->surface.bpe;
+ slice_size = rtex->surface.u.legacy.level[0].slice_size;
+ }
}
return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
slice_size, whandle);
commit 914a26d549aa5f5e28fc6a45292c225e663aa644
Author: Aleksander Morgado <aleksander@aleksander.es>
Date: Thu Jul 6 11:35:37 2017 +0200
etnaviv: don't dereference etna_resource pointer if allocation fails
The check for the pointer being non-NULL was being done too late.
Signed-off-by: Aleksander Morgado <aleksander@aleksander.es>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit a6893a50c8ae5b68e4175366dac718ee9f6fa9d1)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c
index f3d73a8..2bb849a 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -323,9 +323,9 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
struct winsys_handle *handle, unsigned usage)
{
struct etna_screen *screen = etna_screen(pscreen);
- struct etna_resource *rsc = CALLOC_STRUCT(etna_resource);
- struct etna_resource_level *level = &rsc->levels[0];
- struct pipe_resource *prsc = &rsc->base;
+ struct etna_resource *rsc;
+ struct etna_resource_level *level;
+ struct pipe_resource *prsc;
struct pipe_resource *ptiled = NULL;
DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
@@ -334,9 +334,13 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
tmpl->height0, tmpl->depth0, tmpl->array_size, tmpl->last_level,
tmpl->nr_samples, tmpl->usage, tmpl->bind, tmpl->flags);
+ rsc = CALLOC_STRUCT(etna_resource);
if (!rsc)
return NULL;
+ level = &rsc->levels[0];
+ prsc = &rsc->base;
+
*prsc = *tmpl;
pipe_reference_init(&prsc->reference, 1);
commit c6e841667f27f7c97f80f9b447d22b1610372353
Author: Brian Paul <brianp@vmware.com>
Date: Thu Jun 15 11:31:53 2017 -0600
svga: clamp device line width to at least 1 to fix HWv8 line stippling
The line stipple fallback code for virtual HW version 8 didn't work.
With HW version 8, we were getting zero when querying the max line
widths (AA and non-AA). This means we were setting the draw module's
wide line threshold to zero. This caused the wide line stage to always
get enabled. That caused the line stipple module to fall because the
wide line stage was clobbering the rasterization state with a state
object setting the line stipple pattern to 0xffff.
Now the wide_lines variable in draw's validate_pipeline() will not
be incorrectly set.
Also improve debug output.
BTW, also this fixes several other piglit tests: polygon-mode,
primitive- restart-draw-mode, and line-flat-clip-color since they
all use the draw module fallback.
See VMware bug 1895811.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit c2b92dada076afc303e31e3d029256d234254c27)
Squashed with:
svga: adjust line subpixel position for HWv8
This fixes two regressions on HWv8:
Piglit gl-1.0-ortho-pos
Piglit/glean fbo
This was caused by commit c2b92dada076a "svga: clamp device line width
to at least 1 to fix HWv8 line stippling"
This also fixes two conform tests: Vertex Order and Polygon Face
No Piglit/conform changes with HWv9 or later.
VMware bug 1905053
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit 5b8d33acefa9adbf1f0c9ff10f1933a0b3a5c66b)
diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
index 5e303c8..9be806d 100644
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -1090,18 +1090,18 @@ svga_screen_create(struct svga_winsys_screen *sws)
get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
svgascreen->maxLineWidth =
- get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
+ MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
svgascreen->maxLineWidthAA =
- get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
+ MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
if (0) {
debug_printf("svga: haveProvokingVertex %u\n",
svgascreen->haveProvokingVertex);
debug_printf("svga: haveLineStip %u "
- "haveLineSmooth %u maxLineWidth %f\n",
+ "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
- svgascreen->maxLineWidth);
+ svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
}
diff --git a/src/gallium/drivers/svga/svga_state_framebuffer.c b/src/gallium/drivers/svga/svga_state_framebuffer.c
index 146d9dc..ee767bd 100644
--- a/src/gallium/drivers/svga/svga_state_framebuffer.c
+++ b/src/gallium/drivers/svga/svga_state_framebuffer.c
@@ -535,7 +535,7 @@ emit_viewport( struct svga_context *svga,
break;
case PIPE_PRIM_LINES:
adjust_x = -0.5;
- adjust_y = 0;
+ adjust_y = -0.125;
break;
case PIPE_PRIM_TRIANGLES:
adjust_x = -0.5;
commit 49b5da785f52a092bebef32dde6536c9d898a7d5
Author: Alex Smith <asmith@feralinteractive.com>
Date: Fri Jun 30 11:15:42 2017 +0100
ac/nir: Fix ordering of parameters for image atomic cmpswap intrinsics
The NIR parameters are ordered "compare, data", matching GLSL, but both
the image and buffer LLVM intrinsics take them the other way around.
This is already handled correctly for SSBO atomics.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
(cherry picked from commit c2a5cb64272da3cd8d97b0a58da6c6992b0417d3)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1008145..62b7598 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3370,9 +3370,9 @@ static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
abort();
}
- params[param_count++] = get_src(ctx, instr->src[2]);
if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
params[param_count++] = get_src(ctx, instr->src[3]);
+ params[param_count++] = get_src(ctx, instr->src[2]);
if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
commit 401c37f500f351272dede9e7464d836183dafac4
Author: Aleksander Morgado <aleksander@aleksander.es>
Date: Thu Jul 6 23:18:57 2017 +0200
etnaviv: fix refcnt initialization in etna_screen
Despite being a member of the etna_screen struct, 'refcnt' is used by
the winsys-specific logic to track the reference count of the object
managed in a hash table. When the count reaches zero, the pipe screen
is removed from the table and destroyed.
Fix the logic by initializing the refcnt to 1 when screen created.
This initialization is done in etna_screen_create(), to follow the
same logic as in freedreno and virgl.
Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Aleksander Morgado <aleksander@aleksander.es>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
(cherry picked from commit 5d8514de14bd27170293bb373e06f5ff43c708ad)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 8b25146..5f1d280 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -752,6 +752,7 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
screen->dev = dev;
screen->gpu = gpu;
screen->ro = renderonly_dup(ro);
+ screen->refcnt = 1;
if (!screen->ro) {
DBG("could not create renderonly object");
commit d856e97d928c97c159964f1edd07f95909f572f0
Author: Tim Rowley <timothy.o.rowley@intel.com>
Date: Thu Jul 6 13:16:18 2017 -0500
swr/rast: Correctly allocate SWR_STATS memory as cacheline aligned
Cacheline alignment of SWR_STATS to prevent sharing of cachelines
between threads (performance).
Gets rid of gcc-7.1 warning about using c++17's over-aligned new
feature.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit bab03c06fc79ec5624982777684d0c5f123c127c)
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 5c3225d..2423aa7 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -108,7 +108,7 @@ HANDLE SwrCreateContext(
CreateThreadPool(pContext, &pContext->threadPool);
pContext->ppScratch = new uint8_t*[pContext->NumWorkerThreads];
- pContext->pStats = new SWR_STATS[pContext->NumWorkerThreads];
+ pContext->pStats = (SWR_STATS*)AlignedMalloc(sizeof(SWR_STATS) * pContext->NumWorkerThreads, 64);
#if defined(KNOB_ENABLE_AR)
// Setup ArchRast thread contexts which includes +1 for API thread.
@@ -367,7 +367,7 @@ void SwrDestroyContext(HANDLE hContext)
// free the fifos
for (uint32_t i = 0; i < KNOB_MAX_DRAWS_IN_FLIGHT; ++i)
{
- delete[] pContext->dcRing[i].dynState.pStats;
+ AlignedFree(pContext->dcRing[i].dynState.pStats);
delete pContext->dcRing[i].pArena;
delete pContext->dsRing[i].pArena;
pContext->pMacroTileManagerArray[i].~MacroTileMgr();
@@ -392,7 +392,7 @@ void SwrDestroyContext(HANDLE hContext)
}
delete[] pContext->ppScratch;
- delete[] pContext->pStats;
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