mesa: Changes to 'debian-experimental'
VERSION | 2
configure.ac | 10 -
debian/changelog | 6
docs/relnotes/17.1.2.html | 3
docs/relnotes/17.1.3.html | 155 ++++++++++++++++++++++++
src/amd/vulkan/radv_cmd_buffer.c | 73 ++++++-----
src/amd/vulkan/radv_device.c | 2
src/amd/vulkan/radv_image.c | 3
src/amd/vulkan/radv_meta.c | 5
src/amd/vulkan/radv_query.c | 5
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 14 +-
src/compiler/glsl/lower_distance.cpp | 2
src/egl/drivers/dri2/platform_android.c | 4
src/egl/drivers/dri2/platform_drm.c | 2
src/egl/drivers/dri2/platform_wayland.c | 2
src/egl/main/eglsurface.c | 6
src/gallium/drivers/etnaviv/etnaviv_transfer.c | 9 -
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 19 ++
src/gallium/drivers/radeonsi/si_pipe.h | 1
src/gallium/drivers/radeonsi/si_state_draw.c | 41 +++---
src/gallium/drivers/swr/Makefile.am | 4
src/gallium/drivers/swr/SConscript | 2
src/gallium/drivers/swr/rasterizer/core/state.h | 27 ++--
src/gallium/targets/libgl-xlib/Makefile.am | 1
src/glx/dri3_glx.c | 6
src/mesa/drivers/dri/i965/brw_blorp.c | 84 ++++++++++++-
src/mesa/drivers/dri/i965/brw_blorp.h | 3
src/mesa/drivers/dri/i965/brw_clear.c | 66 ----------
src/mesa/drivers/dri/i965/intel_blit.c | 2
src/mesa/drivers/dri/i965/intel_fbo.c | 6
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4
src/mesa/drivers/x11/Makefile.am | 1
src/mesa/drivers/x11/glxapi.c | 8 -
src/mesa/drivers/x11/glxapi.h | 1
src/mesa/drivers/x11/xm_api.c | 8 +
src/mesa/drivers/x11/xmesa.h | 6
src/mesa/state_tracker/st_shader_cache.c | 7 -
src/util/rand_xor.c | 1
39 files changed, 420 insertions(+), 185 deletions(-)
New commits:
commit 679e5c21d728af2af494e7ecc5157f286033b716
Author: Emilio Pozuelo Monfort <pochu27@gmail.com>
Date: Mon Jun 26 00:04:04 2017 +0200
Upload to experimental
diff --git a/debian/changelog b/debian/changelog
index e452929..c129a31 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,8 @@
-mesa (17.1.3-1) UNRELEASED; urgency=medium
+mesa (17.1.3-1) experimental; urgency=medium
* New upstream release.
- -- Emilio Pozuelo Monfort <pochu@debian.org> Thu, 22 Jun 2017 22:30:02 +0200
+ -- Emilio Pozuelo Monfort <pochu@debian.org> Mon, 26 Jun 2017 00:03:57 +0200
mesa (17.1.2-2) experimental; urgency=medium
commit 67b0da6c46cb44acc84dab14e226ea4c68b11aa4
Author: Emilio Pozuelo Monfort <pochu27@gmail.com>
Date: Thu Jun 22 22:30:21 2017 +0200
New upstream release
diff --git a/debian/changelog b/debian/changelog
index 96619c7..e452929 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.1.3-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Emilio Pozuelo Monfort <pochu@debian.org> Thu, 22 Jun 2017 22:30:02 +0200
+
mesa (17.1.2-2) experimental; urgency=medium
* rules: --with-egl-platforms is deprecated, use --with-platforms
commit f60875e211388e299724063af40c01738cc5d819
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Jun 19 12:13:25 2017 +0100
docs: add release notes for 17.1.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/17.1.3.html b/docs/relnotes/17.1.3.html
new file mode 100644
index 0000000..3ac4e40
--- /dev/null
+++ b/docs/relnotes/17.1.3.html
@@ -0,0 +1,155 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.3 Release Notes / June 19, 2017</h1>
+
+<p>
+Mesa 17.1.3 is a bug fix release which fixes bugs found since the 17.1.2 release.
+</p>
+<p>
+Mesa 17.1.3 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100988";>Bug 100988</a> - glXGetCurrentDisplay() no longer works for FakeGLX contexts?</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+ <li>radv: Set both compute and graphics SGPRS on descriptor set flush.</li>
+ <li>radv: Dirty all descriptors sets when changing the pipeline.</li>
+ <li>radv: Remove SI num RB override for occlusion queries.</li>
+</ul>
+
+<p>Brian Paul (1):</p>
+<ul>
+ <li>xlib: fix glXGetCurrentDisplay() failure</li>
+</ul>
+
+<p>Chad Versace (1):</p>
+<ul>
+ <li>i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer()</li>
+</ul>
+
+<p>Chuck Atkins (1):</p>
+<ul>
+ <li>configure.ac: Reduce zlib requirement from 1.2.8 to 1.2.3.</li>
+</ul>
+
+<p>Dave Airlie (3):</p>
+<ul>
+ <li>radv: expose integrated device type for APUs.</li>
+ <li>radv: set fmask state to all 0s when no fmask. (v2)</li>
+ <li>glsl/lower_distance: only set max_array_access for 1D clip dist arrays</li>
+</ul>
+
+<p>Emil Velikov (1):</p>
+<ul>
+ <li>Update version to 17.1.3</li>
+</ul>
+
+<p>Grazvydas Ignotas (1):</p>
+<ul>
+ <li>radv: fix trace dumping for !use_ib_bos</li>
+</ul>
+
+<p>Jason Ekstrand (4):</p>
+<ul>
+ <li>i965/blorp: Take a layer range in intel_hiz_exec</li>
+ <li>i965: Move the pre-depth-clear flush/stalls to intel_hiz_exec</li>
+ <li>i965: Perform HiZ flush/stall prior to HiZ resolves</li>
+ <li>i965: Mark depth surfaces as needing a HiZ resolve after blitting</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+ <li>automake: Link all libGL.so variants with -Bsymbolic.</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.1.2</li>
+</ul>
+
+<p>Lucas Stach (1):</p>
+<ul>
+ <li>etnaviv: always do cpu_fini in transfer_unmap</li>
+</ul>
+
+<p>Lyude (1):</p>
+<ul>
+ <li>nvc0: disable BGRA8 images on Fermi</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+ <li>st/mesa: don't load cached TGSI shaders on demand</li>
+ <li>radeonsi: fix a GPU hang with tessellation on 2-CU configs</li>
+ <li>radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2)</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+ <li>radv: fewer than 8 RBs are possible</li>
+</ul>
+
+<p>Nicolas Dechesne (1):</p>
+<ul>
+ <li>util/rand_xor: add missing include statements</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+ <li>egl: fix _eglQuerySurface in EGL_BUFFER_AGE_EXT case</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+ <li>dri3/GLX: Fix drawable invalidation v2</li>
+</ul>
+
+<p>Tim Rowley (1):</p>
+<ul>
+ <li>swr: relax c++ requirement from c++14 to c++11</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 5ab872d64a49cd9f92d3c0803038ba5bd817ebb7
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Jun 19 12:10:00 2017 +0100
Update version to 17.1.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 59a7513..0558d32 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.1.2
+17.1.3
commit 9bc4ee1c8e0ae9775ff357630e20df68424070cf
Author: Chuck Atkins <chuck.atkins@kitware.com>
Date: Thu Jun 8 13:11:32 2017 -0400
configure.ac: Reduce zlib requirement from 1.2.8 to 1.2.3.
Testing with zlib versions 1.2.{3,4,5,6,7,8} showed no difference in
functionality, correctness, or zlib API usage and 1.2.3 is the oldest
version available in still actively deployed production Linux
distributions (RHEL/CentOS 6 and SuSE 11).
Build 17.1.1 against the system supplied zlib-devel packages for 1.2.3
in EL6 and 1.2.7 on EL7. I then swapped out the zlib version at runtime
via LD_LIBRARY_PATH with ones build from the release tarballs from
zlib.net
Testwise - I ran the piglit shader profile with --quick addded to the
tests since I figured that would exercise the shader cache, which would
in turn use zlib.
Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
[Emil Velikov: add hunk about version/piglit testing]
Acked-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit ad69b037b1ca38390fad440189541e49b3f48f14)
diff --git a/configure.ac b/configure.ac
index 7b85748..b069f54 100644
--- a/configure.ac
+++ b/configure.ac
@@ -97,7 +97,7 @@ XSHMFENCE_REQUIRED=1.1
XVMC_REQUIRED=1.0.6
PYTHON_MAKO_REQUIRED=0.8.0
LIBSENSORS_REQUIRED=4.0.0
-ZLIB_REQUIRED=1.2.8
+ZLIB_REQUIRED=1.2.3
dnl LLVM versions
LLVM_REQUIRED_GALLIUM=3.3.0
commit b708c2961e1eb1fec3e7380bd35c50d64a9f76f7
Author: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Date: Thu Jun 1 12:13:18 2017 +0200
util/rand_xor: add missing include statements
Fixes for:
src/util/rand_xor.c:60:13: error: implicit declaration of function 'open' [-Werror=implicit-function-declaration]
int fd = open("/dev/urandom", O_RDONLY);
^~~~
src/util/rand_xor.c:60:34: error: 'O_RDONLY' undeclared (first use in this function)
int fd = open("/dev/urandom", O_RDONLY);
^~~~~~~~
Signed-off-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit adadadc151fa8232ecd78649a10496661b98e40d)
diff --git a/src/util/rand_xor.c b/src/util/rand_xor.c
index de05fa6..de04bbc 100644
--- a/src/util/rand_xor.c
+++ b/src/util/rand_xor.c
@@ -25,6 +25,7 @@
#if defined(__linux__)
#include <sys/file.h>
#include <unistd.h>
+#include <fcntl.h>
#else
#include <time.h>
#endif
commit 538975fdf8c2224d286599905fc9b5566fff092b
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Jun 12 00:45:36 2017 +0100
glsl/lower_distance: only set max_array_access for 1D clip dist arrays
The max_array_access field applies to the first dimension, which means
we only want to set it for the 1D clip dist arrays.
This fixes an ir_validate assert seen with
KHR-GL44.cull_distance.functional
on nouveau and radeon with debug builds.
Fixes: a08c4ebbe (glsl: rewrite clip/cull distance lowering pass)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 53587b7105aaf10ecf7e5dcb8ed63265af688738)
diff --git a/src/compiler/glsl/lower_distance.cpp b/src/compiler/glsl/lower_distance.cpp
index 9858503..ff04e9a 100644
--- a/src/compiler/glsl/lower_distance.cpp
+++ b/src/compiler/glsl/lower_distance.cpp
@@ -167,7 +167,6 @@ lower_distance_visitor::visit(ir_variable *ir)
/* Clone the old var so that we inherit all of its properties */
*new_var = ir->clone(ralloc_parent(ir), NULL);
(*new_var)->name = ralloc_strdup(*new_var, GLSL_CLIP_VAR_NAME);
- (*new_var)->data.max_array_access = new_size - 1;
(*new_var)->data.location = VARYING_SLOT_CLIP_DIST0;
if (!ir->type->fields.array->is_array()) {
@@ -182,6 +181,7 @@ lower_distance_visitor::visit(ir_variable *ir)
this->shader_stage == MESA_SHADER_GEOMETRY)));
assert (ir->type->fields.array == glsl_type::float_type);
+ (*new_var)->data.max_array_access = new_size - 1;
/* And change the properties that we need to change */
(*new_var)->type = glsl_type::get_array_instance(glsl_type::vec4_type,
commit 3734a7de6c6daca154db448cad8723bd16e4943d
Author: Grazvydas Ignotas <notasas@gmail.com>
Date: Sun Jun 11 16:46:17 2017 +0300
radv: fix trace dumping for !use_ib_bos
Fixes trace dumping crash for SI or when RADV_DEBUG=noibs is set.
Fixes: 97dfff5410 "radv: Dump command buffer on hang."
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit fae3b139055f32c4d076c170726393995be96d1b)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 8430df4..ca7d647 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -931,6 +931,9 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
{
struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
void *ret = NULL;
+
+ if (!cs->ib_buffer)
+ return NULL;
for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
struct radv_amdgpu_winsys_bo *bo;
@@ -949,10 +952,15 @@ static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs,
uint32_t trace_id)
{
struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
+ void *ib = cs->base.buf;
+ int num_dw = cs->base.cdw;
- ac_parse_ib(file,
- radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address),
- cs->ib.size, trace_id, "main IB", cs->ws->info.chip_class,
+ if (cs->ws->use_ib_bos) {
+ ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
+ num_dw = cs->ib.size;
+ }
+ assert(ib);
+ ac_parse_ib(file, ib, num_dw, trace_id, "main IB", cs->ws->info.chip_class,
radv_amdgpu_winsys_get_cpu_addr, cs);
}
commit 423dab9d324e774c807403549c8e67d826af7bd4
Author: Dave Airlie <airlied@redhat.com>
Date: Fri Jun 9 02:11:29 2017 +0100
radv: set fmask state to all 0s when no fmask. (v2)
The shader reads the descriptor to decide if it should take the
fmask value, however we weren't initing it always, which meant
random crap, esp with MSAA depth textures.
Fixes random hangs with:
dEQP-VK.glsl.builtin_var.fragdepth.*
v2: check fmask_state is not NULL
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 51553c0beaeb91b1f2cb3292ac55573309b1d86f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/vulkan/radv_image.c
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 3586e4c..4e6453c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -382,7 +382,8 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F24_LAST_ARRAY(last_layer);
fmask_state[6] = 0;
fmask_state[7] = 0;
- }
+ } else if (fmask_state)
+ memset(fmask_state, 0, 8 * 4);
}
static void
commit 18fd7249c515634bfe23fcf468239add5d5f4cc9
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Tue Jun 6 22:03:49 2017 +0200
radv: Remove SI num RB override for occlusion queries.
radeonsi doesn't have it anymore either.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 59c2e2a061736a981819c3cb217e92e1509d9852)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 04e5e38..d581ea5 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -44,9 +44,6 @@ static unsigned get_max_db(struct radv_device *device)
unsigned num_db = device->physical_device->rad_info.num_render_backends;
MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
- if (device->physical_device->rad_info.chip_class == SI)
- num_db = 8;
-
/* Otherwise we need to change the query reset procedure */
assert(rb_mask == ((1ull << num_db) - 1));
commit f66de22af451cf9d834ff251888c91590443f238
Author: Nicolai Hähnle <nicolai.haehnle@amd.com>
Date: Tue May 16 17:05:02 2017 +0200
radv: fewer than 8 RBs are possible
This fixes the subsequent assertion on Bonaire.
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 388d36dfd180bc16b9d2803d9a213aa5e5ee011f)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 7e0fd1d..04e5e38 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -46,8 +46,6 @@ static unsigned get_max_db(struct radv_device *device)
if (device->physical_device->rad_info.chip_class == SI)
num_db = 8;
- else
- num_db = MAX2(8, num_db);
/* Otherwise we need to change the query reset procedure */
assert(rb_mask == ((1ull << num_db) - 1));
commit 8bd7d8c042e4b19972677a3d42853c97741fd061
Author: Dave Airlie <airlied@redhat.com>
Date: Mon May 15 11:27:10 2017 +1000
radv: expose integrated device type for APUs.
This just sets the vulkan device type depending on whether
this is an APU or GPU.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
(cherry picked from commit 2890a711587e03f906530919056275b599f5f03e)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4649005..10783eb 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -676,7 +676,7 @@ void radv_GetPhysicalDeviceProperties(
.driverVersion = radv_get_driver_version(),
.vendorID = 0x1002,
.deviceID = pdevice->rad_info.pci_id,
- .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
+ .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
.limits = limits,
.sparseProperties = {0},
};
commit ffb46c88261a2443a17740d491374266c62aea67
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sat Jun 3 00:01:36 2017 +0200
radv: Dirty all descriptors sets when changing the pipeline.
Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
(cherry picked from commit 4415a46be2cbb752b94b62bdf5bc7d4d4bbe9fab)
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
src/amd/vulkan/radv_meta.c
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index efeb34c..fd15541 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2152,6 +2152,13 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
assert(cmd_buffer->cs->cdw <= cdw_max);
}
+static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
+{
+ for (unsigned i = 0; i < MAX_SETS; i++) {
+ if (cmd_buffer->state.descriptors[i])
+ cmd_buffer->state.descriptors_dirty |= (1u << i);
+ }
+}
void radv_CmdBindPipeline(
VkCommandBuffer commandBuffer,
@@ -2161,10 +2168,7 @@ void radv_CmdBindPipeline(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
- for (unsigned i = 0; i < MAX_SETS; i++) {
- if (cmd_buffer->state.descriptors[i])
- cmd_buffer->state.descriptors_dirty |= (1 << i);
- }
+ radv_mark_descriptor_sets_dirty(cmd_buffer);
switch (pipelineBindPoint) {
case VK_PIPELINE_BIND_POINT_COMPUTE:
@@ -2173,6 +2177,9 @@ void radv_CmdBindPipeline(
break;
case VK_PIPELINE_BIND_POINT_GRAPHICS:
cmd_buffer->state.pipeline = pipeline;
+ if (!pipeline)
+ break;
+
cmd_buffer->state.vertex_descriptors_dirty = true;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
cmd_buffer->push_constant_stages |= pipeline->active_stages;
@@ -2335,7 +2342,6 @@ void radv_CmdSetStencilReference(
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
}
-
void radv_CmdExecuteCommands(
VkCommandBuffer commandBuffer,
uint32_t commandBufferCount,
@@ -2380,6 +2386,7 @@ void radv_CmdExecuteCommands(
primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
primary->state.last_primitive_reset_en = -1;
primary->state.last_primitive_reset_index = 0;
+ radv_mark_descriptor_sets_dirty(primary);
}
}
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index d8d2568..fac0dcf 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -51,10 +51,10 @@ void
radv_meta_restore(const struct radv_meta_saved_state *state,
struct radv_cmd_buffer *cmd_buffer)
{
- cmd_buffer->state.pipeline = state->old_pipeline;
+ radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
+ radv_pipeline_to_handle(state->old_pipeline));
cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
- cmd_buffer->state.descriptors_dirty |= (1u << 0);
memcpy(cmd_buffer->state.vertex_bindings, state->old_vertex_bindings,
sizeof(state->old_vertex_bindings));
@@ -114,7 +114,6 @@ radv_meta_restore_compute(const struct radv_meta_saved_compute_state *state,
radv_pipeline_to_handle(state->old_pipeline));
cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
- cmd_buffer->state.descriptors_dirty |= (1u << 0);
if (push_constant_size) {
memcpy(cmd_buffer->push_constants, state->push_constants, push_constant_size);
commit c8226d37829051b949913867e21341f4707321e9
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Fri Jun 2 23:51:50 2017 +0200
radv: Set both compute and graphics SGPRS on descriptor set flush.
We clear the descriptors_dirty array afterwards, so the SGPRs for
the other pipeline don't get updated on the flush for that other
draw/dispatch, so we have to make sure we do it immediately.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
(cherry picked from commit 5fb8bb306534d633ceb4e33d89984718326773ba)
[Emil Velikov: drop radv_flush_indirect_descriptor_sets hunk - missing
in branch]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index bd15416..efeb34c 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1268,38 +1268,39 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
static void
radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
VkShaderStageFlags stages,
struct radv_descriptor_set *set,
unsigned idx)
{
- if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_FRAGMENT);
+ if (cmd_buffer->state.pipeline) {
+ if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_FRAGMENT);
- if (stages & VK_SHADER_STAGE_VERTEX_BIT)
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_VERTEX);
+ if (stages & VK_SHADER_STAGE_VERTEX_BIT)
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_VERTEX);
- if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_GEOMETRY);
+ if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(cmd_buffer->state.pipeline))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_GEOMETRY);
- if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_TESS_CTRL);
+ if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_TESS_CTRL);
- if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_TESS_EVAL);
+ if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_TESS_EVAL);
+ }
- if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
+ if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
idx, set->va,
MESA_SHADER_COMPUTE);
}
@@ -1324,7 +1325,6 @@ radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
static void
radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
VkShaderStageFlags stages)
{
unsigned i;
@@ -1345,7 +1345,7 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
if (!set)
continue;
- radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
+ radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
}
cmd_buffer->state.descriptors_dirty = 0;
cmd_buffer->state.push_descriptors_dirty = false;
@@ -1515,8 +1515,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
- radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
- VK_SHADER_STAGE_ALL_GRAPHICS);
+ radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
VK_SHADER_STAGE_ALL_GRAPHICS);
@@ -2757,8 +2756,7 @@ static void
radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
{
radv_emit_compute_pipeline(cmd_buffer);
- radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
- VK_SHADER_STAGE_COMPUTE_BIT);
+ radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
VK_SHADER_STAGE_COMPUTE_BIT);
si_emit_cache_flush(cmd_buffer);
commit 6f062ba8931eb8f35c31807cf336ef29c95b2cd5
Author: Tapani Pälli <tapani.palli@intel.com>
Date: Thu Jun 8 12:24:24 2017 +0300
egl: fix _eglQuerySurface in EGL_BUFFER_AGE_EXT case
Specification states that in case of error, value should not be
written, patch changes buffer age queries to return -1 in case of
error so that we can skip changing the value.
In addition, small change to droid_query_buffer_age to return 0
in case buffer does not have a back buffer available.
Fixes:
dEQP-EGL.functional.negative_partial_update.not_postable_surface
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8fac894f9b8e4e2cb93061fdd25f3aecbfb3bbb7)
diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c
index 5d2768d..2713b1f 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -609,10 +609,10 @@ droid_query_buffer_age(_EGLDriver *drv,
if (update_buffers(dri2_surf) < 0) {
_eglError(EGL_BAD_ALLOC, "droid_query_buffer_age");
- return 0;
+ return -1;
}
- return dri2_surf->back->age;
+ return dri2_surf->back ? dri2_surf->back->age : 0;
}
static EGLBoolean
diff --git a/src/egl/drivers/dri2/platform_drm.c b/src/egl/drivers/dri2/platform_drm.c
index 9431d95..be0b8a4 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -463,7 +463,7 @@ dri2_drm_query_buffer_age(_EGLDriver *drv,
if (get_back_bo(dri2_surf) < 0) {
_eglError(EGL_BAD_ALLOC, "dri2_query_buffer_age");
- return 0;
+ return -1;
}
return dri2_surf->back->age;
diff --git a/src/egl/drivers/dri2/platform_wayland.c b/src/egl/drivers/dri2/platform_wayland.c
index e028267..7a8c194 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -808,7 +808,7 @@ dri2_wl_query_buffer_age(_EGLDriver *drv,
if (get_back_bo(dri2_surf) < 0) {
_eglError(EGL_BAD_ALLOC, "dri2_query_buffer_age");
- return 0;
+ return -1;
}
return dri2_surf->back->age;
diff --git a/src/egl/main/eglsurface.c b/src/egl/main/eglsurface.c
index e935c83..5b3e83e 100644
--- a/src/egl/main/eglsurface.c
+++ b/src/egl/main/eglsurface.c
@@ -409,7 +409,11 @@ _eglQuerySurface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surface,
_eglError(EGL_BAD_ATTRIBUTE, "eglQuerySurface");
return EGL_FALSE;
}
- *value = drv->API.QueryBufferAge(drv, dpy, surface);
+ EGLint result = drv->API.QueryBufferAge(drv, dpy, surface);
+ /* error happened */
+ if (result < 0)
+ return EGL_FALSE;
+ *value = result;
break;
default:
_eglError(EGL_BAD_ATTRIBUTE, "eglQuerySurface");
commit 891dafc8e7ccf1489e072df889aee9c6596eda84
Author: Tim Rowley <timothy.o.rowley@intel.com>
Date: Thu Jun 8 10:38:52 2017 -0500
swr: relax c++ requirement from c++14 to c++11
Remove c++14 generic lambda to keep compiler requirement at c++11.
No regressions on piglit or vtk test suites.
Tested-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0b80b025021f97d27520390867c20336dc891a16)
diff --git a/configure.ac b/configure.ac
index 60ce75a..7b85748 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2476,10 +2476,10 @@ if test -n "$with_gallium_drivers"; then
xswr)
llvm_require_version $LLVM_REQUIRED_SWR "swr"
- swr_require_cxx_feature_flags "C++14" "__cplusplus >= 201402L" \
- "-std=c++14" \
- SWR_CXX14_CXXFLAGS
- AC_SUBST([SWR_CXX14_CXXFLAGS])
+ swr_require_cxx_feature_flags "C++11" "__cplusplus >= 201103L" \
+ ",-std=c++11" \
+ SWR_CXX11_CXXFLAGS
+ AC_SUBST([SWR_CXX11_CXXFLAGS])
swr_require_cxx_feature_flags "AVX" "defined(__AVX__)" \
",-mavx,-march=core-avx" \
diff --git a/src/gallium/drivers/swr/Makefile.am b/src/gallium/drivers/swr/Makefile.am
index 7b2da07..6650abd 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -22,7 +22,7 @@
include Makefile.sources
include $(top_srcdir)/src/gallium/Automake.inc
-AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(SWR_CXX14_CXXFLAGS)
+AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(SWR_CXX11_CXXFLAGS)
noinst_LTLIBRARIES = libmesaswr.la
@@ -32,7 +32,7 @@ COMMON_CXXFLAGS = \
-fno-strict-aliasing \
$(GALLIUM_DRIVER_CFLAGS) \
$(LLVM_CXXFLAGS) \
- $(SWR_CXX14_CXXFLAGS) \
+ $(SWR_CXX11_CXXFLAGS) \
-I$(builddir)/rasterizer/codegen \
-I$(builddir)/rasterizer/jitter \
-I$(builddir)/rasterizer/archrast \
diff --git a/src/gallium/drivers/swr/SConscript b/src/gallium/drivers/swr/SConscript
index 5e3784b..cdb85e2 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -38,7 +38,7 @@ loadersource = env.ParseSourceList('Makefile.sources', [
if not env['msvc'] :
env.Append(CCFLAGS = [
- '-std=c++14',
+ '-std=c++11',
])
swrroot = '#src/gallium/drivers/swr/'
diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h b/src/gallium/drivers/swr/rasterizer/core/state.h
index 535b85e..396c19e 100644
--- a/src/gallium/drivers/swr/rasterizer/core/state.h
+++ b/src/gallium/drivers/swr/rasterizer/core/state.h
@@ -953,26 +953,27 @@ public:
private:
+ template <typename MaskT>
+ INLINE __m128i expandThenBlend4(uint32_t* min, uint32_t* max) // @llvm_func_start
+ {
+ __m128i vMin = _mm_set1_epi32(*min);
+ __m128i vMax = _mm_set1_epi32(*max);
+ return _simd_blend4_epi32<MaskT::value>(vMin, vMax);
+ } // @llvm_func_end
+
INLINE void CalcTileSampleOffsets(int numSamples) // @llvm_func_start
- {
- auto expandThenBlend4 = [](uint32_t* min, uint32_t* max, auto mask)
- {
- __m128i vMin = _mm_set1_epi32(*min);
- __m128i vMax = _mm_set1_epi32(*max);
- return _simd_blend4_epi32<decltype(mask)::value>(vMin, vMax);
- };
-
+ {
auto minXi = std::min_element(std::begin(_xi), &_xi[numSamples]);
auto maxXi = std::max_element(std::begin(_xi), &_xi[numSamples]);
- std::integral_constant<int, 0xA> xMask;
+ using xMask = std::integral_constant<int, 0xA>;
// BR(max), BL(min), UR(max), UL(min)
- tileSampleOffsetsX = expandThenBlend4(minXi, maxXi, xMask);
-
+ tileSampleOffsetsX = expandThenBlend4<xMask>(minXi, maxXi);
+
auto minYi = std::min_element(std::begin(_yi), &_yi[numSamples]);
auto maxYi = std::max_element(std::begin(_yi), &_yi[numSamples]);
- std::integral_constant<int, 0xC> yMask;
+ using yMask = std::integral_constant<int, 0xC>;
// BR(max), BL(min), UR(max), UL(min)
- tileSampleOffsetsY = expandThenBlend4(minYi, maxYi, yMask);
+ tileSampleOffsetsY = expandThenBlend4<yMask>(minYi, maxYi);
}; // @llvm_func_end
// scalar sample values
uint32_t _xi[SWR_MAX_NUM_MULTISAMPLES];
commit 2a7279fa8f28ea99b2786e33f7678f92b41f69eb
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Jun 6 15:23:42 2017 +0200
radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2)
The workaround causes a massive performance decrease on 1-SE parts.
(Cape Verde, Hainan, Oland)
The performance regression is already part of 17.0 and 17.1.
v2: check tess_uses_prim_id
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908)
[Emil Velikov: s/tcs_tes_uses_prim_id/tess_uses_prim_id/]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 0978831..529e1e3 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
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