mesa: Changes to 'upstream-experimental'
.travis.yml | 7
Android.common.mk | 4
VERSION | 2
bin/.cherry-ignore | 4
bin/get-extra-pick-list.sh | 10
bin/get-fixes-pick-list.sh | 59 +-
configure.ac | 290 +++++-----
docs/egl.html | 12
docs/releasing.html | 2
docs/relnotes/17.1.0.html | 3
docs/relnotes/17.1.1.html | 188 ++++++
docs/relnotes/17.1.2.html | 186 ++++++
include/pci_ids/radeonsi_pci_ids.h | 4
src/amd/Makefile.common.am | 2
src/amd/addrlib/gfx9/gfx9addrlib.cpp | 57 +
src/amd/addrlib/gfx9/gfx9addrlib.h | 8
src/amd/common/amd_family.h | 1
src/amd/common/amdgpu_id.h | 10
src/amd/vulkan/Makefile.am | 38 -
src/amd/vulkan/radv_cmd_buffer.c | 8
src/compiler/glsl/shader_cache.cpp | 2
src/compiler/nir/nir_lower_tex.c | 6
src/egl/Makefile.am | 14
src/egl/drivers/dri2/egl_dri2.h | 4
src/egl/drivers/dri2/platform_android.c | 13
src/egl/drivers/dri2/platform_wayland.c | 130 ++--
src/egl/main/eglapi.c | 19
src/egl/main/egldisplay.c | 2
src/gallium/auxiliary/Makefile.am | 20
src/gallium/auxiliary/Makefile.sources | 10
src/gallium/auxiliary/gallivm/lp_bld_init.c | 34 -
src/gallium/auxiliary/renderonly/renderonly.c | 1
src/gallium/auxiliary/vl/vl_winsys.h | 21
src/gallium/drivers/etnaviv/etnaviv_resource.c | 2
src/gallium/drivers/etnaviv/etnaviv_translate.h | 2
src/gallium/drivers/freedreno/freedreno_context.c | 8
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2
src/gallium/drivers/radeon/Makefile.am | 6
src/gallium/drivers/radeon/r600_pipe_common.c | 2
src/gallium/drivers/radeon/r600_texture.c | 16
src/gallium/drivers/radeonsi/si_pipe.c | 20
src/gallium/drivers/radeonsi/si_state.c | 3
src/gallium/drivers/radeonsi/si_state_draw.c | 14
src/gallium/drivers/radeonsi/si_state_shaders.c | 29 -
src/gallium/drivers/swr/Makefile.am | 41 -
src/gallium/drivers/swr/rasterizer/memory/StoreTile.h | 75 ++
src/gallium/drivers/swr/swr_context.cpp | 77 --
src/gallium/drivers/swr/swr_screen.cpp | 10
src/gallium/drivers/vc4/vc4_resource.c | 3
src/gallium/state_trackers/omx/Makefile.am | 1
src/gallium/state_trackers/omx/entrypoint.c | 6
src/gallium/state_trackers/omx/vid_dec.h | 2
src/gallium/state_trackers/va/Makefile.am | 1
src/gallium/state_trackers/va/context.c | 4
src/gallium/state_trackers/vdpau/Makefile.am | 1
src/gallium/state_trackers/vdpau/device.c | 2
src/gallium/state_trackers/xvmc/Makefile.am | 3
src/gallium/targets/dri/Android.mk | 3
src/gallium/targets/omx/Makefile.am | 7
src/gallium/targets/va/Makefile.am | 7
src/gallium/targets/vdpau/Makefile.am | 1
src/gallium/targets/xvmc/Makefile.am | 1
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 4
src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 14
src/gbm/Makefile.am | 1
src/gbm/backends/dri/gbm_dri.c | 2
src/glx/g_glxglvnddispatchfuncs.c | 14
src/glx/g_glxglvnddispatchindices.h | 1
src/intel/Android.vulkan.mk | 2
src/intel/Makefile.vulkan.am | 34 -
src/intel/compiler/brw_vec4.cpp | 107 ++-
src/intel/compiler/brw_vec4_gs_visitor.cpp | 26
src/intel/compiler/brw_vec4_nir.cpp | 15
src/intel/isl/isl_gen7.c | 28
src/intel/vulkan/anv_allocator.c | 14
src/intel/vulkan/anv_blorp.c | 67 ++
src/intel/vulkan/anv_device.c | 203 +++++--
src/intel/vulkan/anv_formats.c | 4
src/intel/vulkan/anv_image.c | 52 -
src/intel/vulkan/anv_private.h | 39 +
src/intel/vulkan/anv_wsi.c | 1
src/intel/vulkan/genX_cmd_buffer.c | 51 +
src/intel/vulkan/genX_query.c | 7
src/intel/vulkan/tests/block_pool_no_free.c | 5
src/intel/vulkan/tests/state_pool.c | 5
src/intel/vulkan/tests/state_pool_free_list_only.c | 5
src/intel/vulkan/tests/state_pool_no_free.c | 5
src/loader/Makefile.am | 2
src/mesa/drivers/dri/Android.mk | 3
src/mesa/drivers/dri/i965/brw_blorp.c | 67 +-
src/mesa/drivers/dri/i965/brw_surface_formats.c | 15
src/mesa/drivers/dri/i965/brw_tex_layout.c | 100 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4
src/mesa/drivers/dri/i965/gen6_depth_state.c | 4
src/mesa/drivers/dri/i965/intel_blit.c | 4
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 37 +
src/mesa/drivers/dri/r200/r200_context.c | 1
src/mesa/drivers/dri/radeon/radeon_common_context.c | 2
src/mesa/drivers/dri/radeon/radeon_context.c | 1
src/mesa/drivers/dri/radeon/radeon_fbo.c | 2
src/mesa/drivers/dri/radeon/radeon_texstate.c | 14
src/mesa/main/context.c | 10
src/mesa/main/mtypes.h | 7
src/mesa/state_tracker/st_cb_eglimage.c | 32 +
src/mesa/state_tracker/st_cb_viewport.c | 4
src/mesa/state_tracker/st_manager.c | 9
src/mesa/state_tracker/st_shader_cache.c | 2
src/util/Android.mk | 1
src/vulkan/Makefile.am | 3
src/vulkan/wsi/wsi_common_wayland.c | 119 ++--
111 files changed, 1898 insertions(+), 782 deletions(-)
New commits:
commit 97f6404e50212fb65fe047e467f5497bcba5b8ac
Author: Juan A. Suarez Romero <jasuarez@igalia.com>
Date: Mon Jun 5 20:27:24 2017 +0000
docs: add release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
diff --git a/docs/relnotes/17.1.2.html b/docs/relnotes/17.1.2.html
new file mode 100644
index 0000000..6f59e18
--- /dev/null
+++ b/docs/relnotes/17.1.2.html
@@ -0,0 +1,186 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.2 Release Notes / June 5, 2017</h1>
+
+<p>
+Mesa 17.1.2 is a bug fix release which fixes bugs found since the 17.1.1 release.
+</p>
+<p>
+Mesa 17.1.2 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=98833";>Bug 98833</a> - [REGRESSION, bisected] Wayland revert commit breaks non-Vsync fullscreen frame updates</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100741";>Bug 100741</a> - Chromium - Memory leak</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100877";>Bug 100877</a> - vulkan/tests/block_pool_no_free regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101110";>Bug 101110</a> - Build failure in GNOME Continuous</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Bartosz Tomczyk (1):</p>
+<ul>
+ <li>mesa: Avoid leaking surface in st_renderbuffer_delete</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (1):</p>
+<ul>
+ <li>radv: Reserve space for descriptor and push constant user SGPR setting.</li>
+</ul>
+
+<p>Daniel Stone (7):</p>
+<ul>
+ <li>vulkan: Fix Wayland uninitialised registry</li>
+ <li>vulkan/wsi/wayland: Remove roundtrip when creating image</li>
+ <li>vulkan/wsi/wayland: Use per-display event queue</li>
+ <li>vulkan/wsi/wayland: Use proxy wrappers for swapchain</li>
+ <li>egl/wayland: Don't open-code roundtrip</li>
+ <li>egl/wayland: Use per-surface event queues</li>
+ <li>egl/wayland: Ensure we get a back buffer</li>
+</ul>
+
+<p>Emil Velikov (24):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.1.1</li>
+ <li>configure: move platform handling further up</li>
+ <li>configure: rename remaining HAVE_EGL_PLATFORM_* guards</li>
+ <li>configure: update remaining --with-egl-platforms references</li>
+ <li>configure: loosen --with-platforms heuristics</li>
+ <li>configure: enable the surfaceless platform by default</li>
+ <li>configure: set HAVE_foo_PLATFORM as applicable</li>
+ <li>configure: error out when building GLX w/o the X11 platform</li>
+ <li>configure: check once for DRI3 dependencies</li>
+ <li>loader: build libloader_dri3_helper.la only with HAVE_PLATFORM_X11</li>
+ <li>configure: error out when building X11 Vulkan without DRI3</li>
+ <li>auxiliary/vl: use vl_*_screen_create stubs when building w/o platform</li>
+ <li>st/va: fix misplaced closing bracket</li>
+ <li>st/omx: remove unneeded X11 include</li>
+ <li>st/omx: fix building against X11-less setups</li>
+ <li>gallium/targets: link against XCB only as needed</li>
+ <li>configure: error out if building VA w/o supported platform</li>
+ <li>configure: error out if building OMX w/o supported platform</li>
+ <li>configure: error out if building VDPAU w/o supported platform</li>
+ <li>configure: error out if building XVMC w/o supported platform</li>
+ <li>travis: remove workarounds for the Vulkan target</li>
+ <li>anv: automake: list shared libraries after the static ones</li>
+ <li>radv: automake: list shared libraries after the static ones</li>
+ <li>egl/wayland: select the format based on the interface used</li>
+</ul>
+
+<p>Ian Romanick (3):</p>
+<ul>
+ <li>r100: Don't assume that the base mipmap of a texture exists</li>
+ <li>r100,r200: Don't assume glVisual is non-NULL during context creation</li>
+ <li>r100: Use _mesa_get_format_base_format in radeon_update_wrapper</li>
+</ul>
+
+<p>Jason Ekstrand (17):</p>
+<ul>
+ <li>anv: Handle color layout transitions from the UNINITIALIZED layout</li>
+ <li>anv: Handle transitioning depth from UNDEFINED to other layouts</li>
+ <li>anv/image: Get rid of the memset(aux, 0, sizeof(aux)) hack</li>
+ <li>anv: Predicate 48bit support on gen >= 8</li>
+ <li>anv: Set up memory types and heaps during physical device init</li>
+ <li>anv: Set image memory types based on the type count</li>
+ <li>i965/blorp: Do and end-of-pipe sync on both sides of fast-clear ops</li>
+ <li>i965: Round copy size to the nearest block in intel_miptree_copy</li>
+ <li>anv: Set EXEC_OBJECT_ASYNC when available</li>
+ <li>anv: Determine the type of mapping based on type metadata</li>
+ <li>anv: Add valid_bufer_usage to the memory type metadata</li>
+ <li>anv: Stop setting BO flags in bo_init_new</li>
+ <li>anv: Make supports_48bit_addresses a heap property</li>
+ <li>anv: Refactor memory type setup</li>
+ <li>anv: Advertise both 32-bit and 48-bit heaps when we have enough memory</li>
+ <li>i965: Rework Sandy Bridge HiZ and stencil layouts</li>
+ <li>anv: Require vertex buffers to come from a 32-bit heap</li>
+</ul>
+
+<p>Juan A. Suarez Romero (13):</p>
+<ul>
+ <li>Revert "android: fix segfault within swap_buffers"</li>
+ <li>cherry-ignore: radeonsi: load patch_id for TES-as-ES when exporting for PS</li>
+ <li>cherry-ignore: anv: Determine the type of mapping based on type metadata</li>
+ <li>cherry-ignore: anv: Stop setting BO flags in bo_init_new</li>
+ <li>cherry-ignore: anv: Make supports_48bit_addresses a heap property</li>
+ <li>cherry-ignore: anv: Advertise both 32-bit and 48-bit heaps when we have enough memory</li>
+ <li>cherry-ignore: anv: Require vertex buffers to come from a 32-bit heap</li>
+ <li>cherry-ignore: radv: fix regression in descriptor set freeing</li>
+ <li>cherry-ignore: anv: Add valid_bufer_usage to the memory type metadata</li>
+ <li>cherry-ignore: anv: Refactor memory type setup</li>
+ <li>Revert "cherry-ignore: anv: [...]"</li>
+ <li>Revert "cherry-ignore: anv: Require vertex buffers to come from a 32-bit heap"</li>
+ <li>Update version to 17.1.2</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+ <li>radeonsi/gfx9: compile shaders with +xnack</li>
+</ul>
+
+<p>Nicolai Hähnle (1):</p>
+<ul>
+ <li>st/mesa: remove redundant stfb->iface checks</li>
+</ul>
+
+<p>Nicolas Boichat (1):</p>
+<ul>
+ <li>configure.ac: Also match -androideabi tuple</li>
+</ul>
+
+<p>Rob Clark (1):</p>
+<ul>
+ <li>freedreno: fix fence creation fail if no rendering</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+ <li>egl/android: fix segfault within swap_buffers</li>
+</ul>
+
+<p>Timothy Arceri (1):</p>
+<ul>
+ <li>st/mesa: don't mark the program as in cache_fallback when there is cache miss</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit eada8963c1917d4de7c2f2f975362eda7673d89e
Author: Juan A. Suarez Romero <jasuarez@igalia.com>
Date: Mon Jun 5 20:15:30 2017 +0000
Update version to 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
diff --git a/VERSION b/VERSION
index 6f9c209..59a7513 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.1.1
+17.1.2
commit ae55ab84b5e2faf35e42bf8ab03cbcc69f3fef04
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed May 17 11:54:24 2017 -0700
anv: Require vertex buffers to come from a 32-bit heap
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 39adea9330376a64a4b5e8da98f5e055ebd3331e)
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 726ccce..5bfbf84 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -153,6 +153,18 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) {
uint32_t valid_buffer_usage = ~0;
+ /* There appears to be a hardware issue in the VF cache where it only
+ * considers the bottom 32 bits of memory addresses. If you happen to
+ * have two vertex buffers which get placed exactly 4 GiB apart and use
+ * them in back-to-back draw calls, you can get collisions. In order to
+ * solve this problem, we require vertex and index buffers be bound to
+ * memory allocated out of the 32-bit heap.
+ */
+ if (device->memory.heaps[heap].supports_48bit_addresses) {
+ valid_buffer_usage &= ~(VK_BUFFER_USAGE_INDEX_BUFFER_BIT |
+ VK_BUFFER_USAGE_VERTEX_BUFFER_BIT);
+ }
+
if (device->info.has_llc) {
/* Big core GPUs share LLC with the CPU and thus one memory type can be
* both cached and coherent at the same time.
commit 57cdaa3dcc0f0b9dd89bf8586a95b5f3f99b6eb9
Author: Juan A. Suarez Romero <jasuarez@igalia.com>
Date: Sat Jun 3 20:36:43 2017 +0200
Revert "cherry-ignore: anv: Require vertex buffers to come from a 32-bit heap"
This reverts commit b3e48a07c0bb0c58e73ec6d82f3a3104ec26aacb.
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 209c0ec..fc9bf36 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -1,6 +1,4 @@
# This commit depends on 9fd9a7d0ba3 and 678d568c7b2, neither of which is in branch.
b84b631c6381d9b36bca5d0e7cc67dd23af188c1 radeonsi: load patch_id for TES-as-ES when exporting for PS
-# This commit causes regressions in the crucible testsuite
-39adea9330376a64a4b5e8da98f5e055ebd3331e anv: Require vertex buffers to come from a 32-bit heap
# This commit addressed an earlier commit 126d5ad which did not land in branch.
9da104593386f6e8ddec8f0d9d288aceb8908fe1 radv: fix regression in descriptor set freeing.
commit 2c2338992224b683457a18dd3a026a7686dd1e95
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sat May 27 10:36:23 2017 -0700
i965: Rework Sandy Bridge HiZ and stencil layouts
Sandy Bridge does not technically support mipmapped depth/stencil. In
order to work around this, we allocate what are effectively completely
separate images for each miplevel, ensure that they are page-aligned,
and manually offset to them. Prior to layered rendering, this was a
simple matter of setting a large enough halign/valign.
With the advent of layered rendering, however, things got more
complicated. Now, things weren't as simple as just handing a surface
off to the hardware. Any miplevel of a normally mipmapped surface can
be considered as just an array surface given the right qpitch. However,
the hardware gives us no capability to specify qpitch so this won't
work. Instead, the chosen solution was to use a new "all slices at each
LOD" layout which laid things out as a mipmap of arrays rather than an
array of mipmaps. This way you can easily offset to any of the
miplevels and each is a valid array.
Unfortunately, the "all slices at each lod" concept missed one
fundamental thing about SNB HiZ and stencil hardware: It doesn't just
always act as if you're always working with a non-mipmapped surface, it
acts as if you're always working on a non-mipmapped surface of the same
size as LOD0. In other words, even though it may only write the
upper-left corner of each array slice, the qpitch for the array is for a
surface the size of LOD0 of the depth surface. This mistake causes us
to under-allocate HiZ and stencil in some cases and also to accidentally
allow different miplevels to overlap. Sadly, piglit test coverage
didn't quite catch this until I started making changes to the resolve
code that caused additional HiZ resolves in certain tests.
This commit switches Sandy Bridge HiZ and stencil over to a new scheme
that lays out the non-zero miplevels horizontally below LOD0. This way
they can all have the same qpitch without interfering with each other.
Technically, the miplevels still overlap, but things are spaced out
enough that each page is only in the "written area" of one LOD.
Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit 10903d228919085cdb160c563c481ed1cc09e34c)
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index ebc4612..423ce1f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -113,7 +113,7 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
uint32_t lod,
uint32_t *offset)
{
- assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+ assert(mt->array_layout == GEN6_HIZ_STENCIL);
if (mt->format == MESA_FORMAT_S_UINT8) {
/* Note: we can't compute the stencil offset using
@@ -172,12 +172,12 @@ blorp_surf_for_miptree(struct brw_context *brw,
};
if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
- mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
+ mt->array_layout == GEN6_HIZ_STENCIL) {
+ /* Sandy bridge stencil and HiZ use this GEN6_HIZ_STENCIL hack in
* order to allow for layered rendering. The hack makes each LOD of the
* stencil or HiZ buffer a single tightly packed array surface at some
* offset into the surface. Since ISL doesn't know how to deal with the
- * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
+ * crazy GEN6_HIZ_STENCIL layout and since we have to do a manual
* offset of it anyway, we might as well do the offset here and keep the
* hacks inside the i965 driver.
*
@@ -251,8 +251,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
if (hiz_mt) {
- assert(brw->gen == 6 &&
- hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+ assert(brw->gen == 6 && hiz_mt->array_layout == GEN6_HIZ_STENCIL);
/* gen6 requires the HiZ buffer to be manually offset to the
* right location. We could fixup the surf but it doesn't
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index bfa8afa..1f0a1e9 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -216,6 +216,8 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
mt->total_height = MAX2(mt->total_height, y + img_height);
/* Layout_below: step right after second mipmap.
+ *
+ * For Sandy Bridge HiZ and stencil, we always step down.
*/
if (level == mt->first_level + 1) {
x += ALIGN_NPOT(width, mt->halign) / bw;
@@ -231,6 +233,67 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
}
+static void
+brw_miptree_layout_gen6_hiz_stencil(struct intel_mipmap_tree *mt)
+{
+ unsigned x = 0;
+ unsigned y = 0;
+ unsigned width = mt->physical_width0;
+ unsigned height = mt->physical_height0;
+ /* Number of layers of array texture. */
+ unsigned depth = mt->physical_depth0;
+ unsigned tile_width, tile_height, bw, bh;
+
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ bw = bh = 1;
+ /* W-tiled */
+ tile_width = 64;
+ tile_height = 64;
+ } else {
+ assert(_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT ||
+ _mesa_get_format_base_format(mt->format) == GL_DEPTH_STENCIL);
+ /* Each 128-bit HiZ block corresponds to a region of of 8x4 depth
+ * samples. Each cache line in the Y-Tiled HiZ image contains 2x2 HiZ
+ * blocks. Therefore, each Y-tiled cache line corresponds to an 16x8
+ * region in the depth surface. Since we're representing it as
+ * RGBA_FLOAT32, the miptree calculations will think that each cache
+ * line is 1x4 pixels. Therefore, we need a scale-down factor of 16x2
+ * and a vertical alignment of 2.
+ */
+ mt->cpp = 16;
+ bw = 16;
+ bh = 2;
+ /* Y-tiled */
+ tile_width = 128 / mt->cpp;
+ tile_height = 32;
+ }
+
+ mt->total_width = 0;
+ mt->total_height = 0;
+
+ for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
+ intel_miptree_set_level_info(mt, level, x, y, depth);
+
+ const unsigned img_width = ALIGN(DIV_ROUND_UP(width, bw), mt->halign);
+ const unsigned img_height =
+ ALIGN(DIV_ROUND_UP(height, bh), mt->valign) * depth;
+
+ mt->total_width = MAX2(mt->total_width, x + img_width);
+ mt->total_height = MAX2(mt->total_height, y + img_height);
+
+ if (level == mt->first_level) {
+ y += ALIGN(img_height, tile_height);
+ } else {
+ x += ALIGN(img_width, tile_width);
+ }
+
+ /* We only minify the width. We want qpitch to match for all miplevels
+ * because the hardware doesn't know we aren't on LOD0.
+ */
+ width = minify(width, 1);
+ }
+}
+
unsigned
brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
@@ -249,6 +312,8 @@ brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
const struct intel_mipmap_tree *mt,
unsigned level)
{
+ assert(mt->array_layout != GEN6_HIZ_STENCIL || brw->gen == 6);
+
if (brw->gen >= 9) {
/* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
* effectively end up with a packed qpitch anyway whenever
@@ -281,6 +346,15 @@ brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
return ALIGN_NPOT(minify(mt->physical_height0, level), mt->valign);
+ } else if (mt->array_layout == GEN6_HIZ_STENCIL) {
+ /* For HiZ and stencil on Sandy Bridge, we don't minify the height. */
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ return ALIGN(mt->physical_height0, mt->valign);
+ } else {
+ /* HiZ has a vertical scale factor of 2. */
+ return ALIGN(DIV_ROUND_UP(mt->physical_height0, 2), mt->valign);
+ }
+
} else {
const unsigned h0 = ALIGN_NPOT(mt->physical_height0, mt->valign);
const unsigned h1 = ALIGN_NPOT(minify(mt->physical_height0, 1), mt->valign);
@@ -333,6 +407,8 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
if (layout_1d)
gen9_miptree_layout_1d(mt);
+ else if (mt->array_layout == GEN6_HIZ_STENCIL)
+ brw_miptree_layout_gen6_hiz_stencil(mt);
else
brw_miptree_layout_2d(mt);
@@ -556,6 +632,8 @@ intel_miptree_set_total_width_height(struct brw_context *brw,
case INTEL_MSAA_LAYOUT_IMS:
if (gen9_use_linear_1d_layout(brw, mt))
gen9_miptree_layout_1d(mt);
+ else if (mt->array_layout == GEN6_HIZ_STENCIL)
+ brw_miptree_layout_gen6_hiz_stencil(mt);
else
brw_miptree_layout_2d(mt);
break;
@@ -579,15 +657,9 @@ intel_miptree_set_alignment(struct brw_context *brw,
* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
* - BSpec (for Ivybridge and slight variations in separate stencil)
*/
- bool gen6_hiz_or_stencil = false;
- if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- const GLenum base_format = _mesa_get_format_base_format(mt->format);
- gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
- }
-
- if (gen6_hiz_or_stencil) {
- /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
+ if (mt->array_layout == GEN6_HIZ_STENCIL) {
+ /* On gen6, we use GEN6_HIZ_STENCIL for stencil/hiz because the
* hardware doesn't support multiple mip levels on stencil/hiz.
*
* PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
@@ -600,15 +672,13 @@ intel_miptree_set_alignment(struct brw_context *brw,
/* Stencil uses W tiling, so we force W tiling alignment for the
* ALL_SLICES_AT_EACH_LOD miptree layout.
*/
- mt->halign = 64;
- mt->valign = 64;
+ mt->halign = 4;
+ mt->valign = 2;
assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
} else {
- /* Depth uses Y tiling, so we force need Y tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->halign = 128 / mt->cpp;
- mt->valign = 32;
+ /* See brw_miptree_layout_gen6_hiz_stencil() */
+ mt->halign = 1;
+ mt->valign = 2;
}
} else if (mt->compressed) {
/* The hardware alignment requirements for compressed textures
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 0ff2407..a77e461 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -164,7 +164,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
uint32_t offset = 0;
- if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+ if (hiz_mt->array_layout == GEN6_HIZ_STENCIL) {
offset = intel_miptree_get_aligned_offset(
hiz_mt,
hiz_mt->level[lod].level_x,
@@ -190,7 +190,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
if (separate_stencil) {
uint32_t offset = 0;
- if (stencil_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+ if (stencil_mt->array_layout == GEN6_HIZ_STENCIL) {
assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
/* Note: we can't compute the stencil offset using
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index db0a397..609413b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -463,7 +463,7 @@ intel_miptree_create_layout(struct brw_context *brw,
intel_miptree_wants_hiz_buffer(brw, mt)))) {
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
- stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD |
+ stencil_flags |= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL |
MIPTREE_LAYOUT_TILING_ANY;
}
@@ -496,8 +496,8 @@ intel_miptree_create_layout(struct brw_context *brw,
}
}
- if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
- mt->array_layout = ALL_SLICES_AT_EACH_LOD;
+ if (layout_flags & MIPTREE_LAYOUT_GEN6_HIZ_STENCIL)
+ mt->array_layout = GEN6_HIZ_STENCIL;
/*
* Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
@@ -1789,7 +1789,7 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6)
- layout_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD;
+ layout_flags |= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL;
if (!buf)
return NULL;
@@ -2379,7 +2379,7 @@ intel_update_r8stencil(struct brw_context *brw,
const uint32_t r8stencil_flags =
MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
MIPTREE_LAYOUT_DISABLE_AUX;
- assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
+ assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
mt->r8stencil_mt = intel_miptree_create(brw,
src->target,
MESA_FORMAT_R_UINT8,
@@ -3297,6 +3297,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_FULL;
break;
case ALL_SLICES_AT_EACH_LOD:
+ case GEN6_HIZ_STENCIL:
surf->array_pitch_span = ISL_ARRAY_PITCH_SPAN_COMPACT;
break;
default:
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7aabac0..be460f3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -251,6 +251,41 @@ enum miptree_array_layout {
* +---+
*/
ALL_SLICES_AT_EACH_LOD,
+
+ /* On Sandy Bridge, HiZ and stencil buffers work the same as on Ivy Bridge
+ * except that they don't technically support mipmapping. That does not,
+ * however, stop us from doing it. As far as Sandy Bridge hardware is
+ * concerned, HiZ and stencil always operates on a single miplevel 2D
+ * (possibly array) image. The dimensions of that image are NOT minified.
+ *
+ * In order to implement HiZ and stencil on Sandy Bridge, we create one
+ * full-sized 2D (possibly array) image for every LOD with every image
+ * aligned to a page boundary. In order to save memory, we pretend that
+ * the width of each miplevel is minified and we place LOD1 and above below
+ * LOD0 but horizontally adjacent to each other. When considered as
+ * full-sized images, LOD1 and above technically overlap. However, since
+ * we only write to part of that image, the hardware will never notice the
+ * overlap.
+ *
+ * This layout looks something like this:
+ *
+ * +---------+
+ * | |
+ * | |
+ * +---------+
+ * | |
+ * | |
+ * +---------+
+ *
+ * +----+ +-+ .
+ * | | +-+
+ * +----+
+ *
+ * +----+ +-+ .
+ * | | +-+
+ * +----+
+ */
+ GEN6_HIZ_STENCIL,
};
enum intel_aux_disable {
@@ -672,7 +707,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
enum {
MIPTREE_LAYOUT_ACCELERATED_UPLOAD = 1 << 0,
- MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD = 1 << 1,
+ MIPTREE_LAYOUT_GEN6_HIZ_STENCIL = 1 << 1,
MIPTREE_LAYOUT_FOR_BO = 1 << 2,
MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
commit f967ae7b3f6e6e685c23ac1eec658bec3a81078e
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed May 17 11:54:12 2017 -0700
anv: Advertise both 32-bit and 48-bit heaps when we have enough memory
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 50d0eb5096bd9514821a641f25c0b3455c0f8a88)
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 52181f1..726ccce 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -112,12 +112,42 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
if (result != VK_SUCCESS)
return result;
- device->memory.heap_count = 1;
- device->memory.heaps[0] = (struct anv_memory_heap) {
- .size = heap_size,
- .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
- .supports_48bit_addresses = device->supports_48bit_addresses,
- };
+ if (heap_size <= 3ull * (1ull << 30)) {
+ /* In this case, everything fits nicely into the 32-bit address space,
+ * so there's no need for supporting 48bit addresses on client-allocated
+ * memory objects.
+ */
+ device->memory.heap_count = 1;
+ device->memory.heaps[0] = (struct anv_memory_heap) {
+ .size = heap_size,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = false,
+ };
+ } else {
+ /* Not everything will fit nicely into a 32-bit address space. In this
+ * case we need a 64-bit heap. Advertise a small 32-bit heap and a
+ * larger 48-bit heap. If we're in this case, then we have a total heap
+ * size larger than 3GiB which most likely means they have 8 GiB of
+ * video memory and so carving off 1 GiB for the 32-bit heap should be
+ * reasonable.
+ */
+ const uint64_t heap_size_32bit = 1ull << 30;
+ const uint64_t heap_size_48bit = heap_size - heap_size_32bit;
+
+ assert(device->supports_48bit_addresses);
+
+ device->memory.heap_count = 2;
+ device->memory.heaps[0] = (struct anv_memory_heap) {
+ .size = heap_size_48bit,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = true,
+ };
+ device->memory.heaps[1] = (struct anv_memory_heap) {
+ .size = heap_size_32bit,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = false,
+ };
+ }
uint32_t type_count = 0;
for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) {
commit de8ebbcf1e4730fe34461dbe1813a48a4f1687df
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed May 17 11:42:36 2017 -0700
anv: Refactor memory type setup
This makes us walk over the heaps one at a time and add the types for
LLC and !LLC to each heap.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 34581fdd4f149894dfa51777a2f7eb289bd08b71)
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 95a29ab..52181f1 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -112,42 +112,6 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
if (result != VK_SUCCESS)
return result;
- if (device->info.has_llc) {
- /* Big core GPUs share LLC with the CPU and thus one memory type can be
- * both cached and coherent at the same time.
- */
- device->memory.type_count = 1;
- device->memory.types[0] = (struct anv_memory_type) {
- .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
- VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
- VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
- .heapIndex = 0,
- .valid_buffer_usage = ~0,
- };
- } else {
- /* The spec requires that we expose a host-visible, coherent memory
- * type, but Atom GPUs don't share LLC. Thus we offer two memory types
- * to give the application a choice between cached, but not coherent and
- * coherent but uncached (WC though).
- */
- device->memory.type_count = 2;
- device->memory.types[0] = (struct anv_memory_type) {
- .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
- VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
- .heapIndex = 0,
- .valid_buffer_usage = ~0,
- };
- device->memory.types[1] = (struct anv_memory_type) {
- .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
- VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
- .heapIndex = 0,
- .valid_buffer_usage = ~0,
- };
- }
-
device->memory.heap_count = 1;
device->memory.heaps[0] = (struct anv_memory_heap) {
.size = heap_size,
@@ -155,6 +119,46 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
.supports_48bit_addresses = device->supports_48bit_addresses,
};
+ uint32_t type_count = 0;
+ for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) {
+ uint32_t valid_buffer_usage = ~0;
+
+ if (device->info.has_llc) {
+ /* Big core GPUs share LLC with the CPU and thus one memory type can be
+ * both cached and coherent at the same time.
+ */
+ device->memory.types[type_count++] = (struct anv_memory_type) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
+ VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
+ VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
+ .heapIndex = heap,
+ .valid_buffer_usage = valid_buffer_usage,
+ };
+ } else {
+ /* The spec requires that we expose a host-visible, coherent memory
+ * type, but Atom GPUs don't share LLC. Thus we offer two memory types
+ * to give the application a choice between cached, but not coherent and
+ * coherent but uncached (WC though).
+ */
+ device->memory.types[type_count++] = (struct anv_memory_type) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
+ VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
+ .heapIndex = heap,
+ .valid_buffer_usage = valid_buffer_usage,
+ };
+ device->memory.types[type_count++] = (struct anv_memory_type) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
+ VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
+ .heapIndex = heap,
+ .valid_buffer_usage = valid_buffer_usage,
+ };
+ }
+ }
+ device->memory.type_count = type_count;
+
return VK_SUCCESS;
}
commit 2562b3252b63f2e938d6e6614e1f9a2fa2064140
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed May 17 11:38:16 2017 -0700
anv: Make supports_48bit_addresses a heap property
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit b83b1af6f6936f36db42a8f8b8e0854d0f9491fd)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Conflicts:
src/intel/vulkan/anv_device.c
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index b07def9..95a29ab 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -149,9 +149,10 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
}
device->memory.heap_count = 1;
- device->memory.heaps[0] = (VkMemoryHeap) {
+ device->memory.heaps[0] = (struct anv_memory_heap) {
.size = heap_size,
.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = device->supports_48bit_addresses,
};
return VK_SUCCESS;
@@ -1621,7 +1622,8 @@ VkResult anv_AllocateMemory(
mem->map = NULL;
mem->map_size = 0;
- if (pdevice->supports_48bit_addresses)
+ assert(mem->type->heapIndex < pdevice->memory.heap_count);
+ if (pdevice->memory.heaps[mem->type->heapIndex].supports_48bit_addresses)
mem->bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
if (pdevice->has_exec_async)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 61f90ea..ad82c77 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -613,6 +613,15 @@ struct anv_memory_type {
VkBufferUsageFlags valid_buffer_usage;
};
+struct anv_memory_heap {
+ /* Standard bits passed on to the client */
+ VkDeviceSize size;
+ VkMemoryHeapFlags flags;
+
+ /* Driver-internal book-keeping */
+ bool supports_48bit_addresses;
+};
+
struct anv_physical_device {
VK_LOADER_DATA _loader_data;
@@ -644,7 +653,7 @@ struct anv_physical_device {
uint32_t type_count;
struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
uint32_t heap_count;
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