mesa: Changes to 'ubuntu'
VERSION | 2
bin/.cherry-ignore | 3
debian/changelog | 12
docs/relnotes/17.0.3.html | 3
docs/relnotes/17.0.4.html | 148 ++++++++++++
include/pci_ids/radeonsi_pci_ids.h | 1
src/amd/vulkan/radv_cmd_buffer.c | 3
src/gallium/auxiliary/util/u_debug.h | 4
src/gallium/drivers/freedreno/freedreno_draw.c | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 23 +
src/gallium/drivers/nouveau/nouveau_buffer.c | 6
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2
src/gallium/state_trackers/dri/dri2.c | 2
src/gallium/targets/omx/omx.sym | 5
src/gallium/targets/pipe-loader/pipe.sym | 5
src/gallium/targets/va/va.sym | 5
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 11
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 27 +-
src/gallium/winsys/sw/hgl/hgl_sw_winsys.c | 3
src/gbm/backends/dri/gbm_dri.c | 8
src/intel/vulkan/anv_cmd_buffer.c | 10
src/intel/vulkan/genX_blorp_exec.c | 15 +
src/intel/vulkan/genX_pipeline.c | 27 +-
src/loader/loader.c | 2
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 18 -
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 16 +
src/mesa/drivers/dri/i965/intel_screen.c | 172 +++++++++++---
src/mesa/state_tracker/st_atom_image.c | 2
src/mesa/state_tracker/st_atom_texture.c | 2
src/mesa/state_tracker/st_cb_fbo.c | 2
src/mesa/state_tracker/st_cb_texture.c | 5
src/mesa/state_tracker/st_cb_texture.h | 3
src/mesa/state_tracker/st_gen_mipmap.c | 2
33 files changed, 454 insertions(+), 97 deletions(-)
New commits:
commit 7a57b3633ff4230134ae9fdd3793d3becda27858
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Wed Apr 26 11:02:07 2017 +0300
release to artful
diff --git a/debian/changelog b/debian/changelog
index 972af57..20f7f55 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.0.4-1ubuntu1) artful; urgency=medium
+
+ * Merge from Debian.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Wed, 26 Apr 2017 11:01:18 +0300
+
mesa (17.0.4-1) experimental; urgency=medium
* New upstrem release.
commit 7af911e5db3e664e8f0290f7d6260d82e8aeaea8
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Wed Apr 19 16:16:51 2017 +0300
upload to experimental
diff --git a/debian/changelog b/debian/changelog
index 5761be2..8687382 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,8 @@
-mesa (17.0.4-1) UNRELEASED; urgency=medium
+mesa (17.0.4-1) experimental; urgency=medium
* New upstrem release.
- -- Timo Aaltonen <tjaalton@debian.org> Wed, 19 Apr 2017 14:22:13 +0300
+ -- Timo Aaltonen <tjaalton@debian.org> Wed, 19 Apr 2017 16:14:20 +0300
mesa (17.0.3-1) experimental; urgency=medium
commit e14c595cee5d711244331d257c9a41ab6b600080
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Wed Apr 19 14:23:00 2017 +0300
update changelog
diff --git a/debian/changelog b/debian/changelog
index 0c014d1..5761be2 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.0.4-1) UNRELEASED; urgency=medium
+
+ * New upstrem release.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Wed, 19 Apr 2017 14:22:13 +0300
+
mesa (17.0.3-1) experimental; urgency=medium
* New upstream release.
commit 367bafc7c153611b39bb41145a9601e5f1cb4934
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Apr 17 14:38:04 2017 +0100
docs: add release notes for 17.0.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/17.0.4.html b/docs/relnotes/17.0.4.html
new file mode 100644
index 0000000..ccc3864
--- /dev/null
+++ b/docs/relnotes/17.0.4.html
@@ -0,0 +1,148 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.0.4 Release Notes / April 17, 2017</h1>
+
+<p>
+Mesa 17.0.4 is a bug fix release which fixes bugs found since the 17.0.3 release.
+</p>
+<p>
+Mesa 17.0.4 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99515";>Bug 99515</a> - SIGSEGV MAPERR on Android nougat-x86 with mesa 17.0.0rc</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100391";>Bug 100391</a> - SachaWillems deferredmultisampling asserts</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100452";>Bug 100452</a> - push_constants host memory leak when resetting command buffer</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100582";>Bug 100582</a> - [GEN8+] piglit.spec.arb_stencil_texturing.glblitframebuffer corrupts state.gl_texture* assertions</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alex Deucher (1):</p>
+<ul>
+ <li>radeonsi: add new polaris10 pci id</li>
+</ul>
+
+<p>Alex Smith (1):</p>
+<ul>
+ <li>radv: Invalidate L2 for TRANSFER_WRITE barriers</li>
+</ul>
+
+<p>Andres Gomez (1):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.0.3</li>
+</ul>
+
+<p>Craig Stout (1):</p>
+<ul>
+ <li>anv/cmd_buffer: fix host memory leak</li>
+</ul>
+
+<p>Emil Velikov (3):</p>
+<ul>
+ <li>Revert "cherry-ignore: add the Flush after unmap in gbm/dri fix"</li>
+ <li>Revert "freedreno: fix memory leak"</li>
+ <li>Update version to 17.0.4</li>
+</ul>
+
+<p>Fabio Estevam (1):</p>
+<ul>
+ <li>loader: Move non-error message to debug level</li>
+</ul>
+
+<p>Ilia Mirkin (4):</p>
+<ul>
+ <li>nvc0/ir: fix LSB/BFE/BFI implementations</li>
+ <li>nvc0/ir: fix overwriting of offset register with interpolateAtOffset</li>
+ <li>nvc0: increase texture buffer object alignment to 256 for pre-GM107</li>
+ <li>nouveau: when mapping a persistent buffer, synchronize on former xfers</li>
+</ul>
+
+<p>Jason Ekstrand (5):</p>
+<ul>
+ <li>i965/fs: Always provide a default LOD of 0 for TXS and TXL</li>
+ <li>anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndex</li>
+ <li>anv/blorp: Align vertex buffers to 64B</li>
+ <li>i965/blorp: Align vertex buffers to 64B</li>
+ <li>i965/blorp: Bump the batch space estimate</li>
+</ul>
+
+<p>Jerome Duval (2):</p>
+<ul>
+ <li>haiku: build fixes around debug defines</li>
+ <li>haiku/winsys: fix dt prototype args</li>
+</ul>
+
+<p>Julien Isorce (4):</p>
+<ul>
+ <li>winsys/radeon: check null in radeon_cs_create_fence</li>
+ <li>winsys/radeon: check null return from radeon_cs_create_fence in cs_flush</li>
+ <li>radeon: initialize hole variable before calling container_of</li>
+ <li>radeon_drm_bo: explicitly check return value of drmCommandWriteRead</li>
+</ul>
+
+<p>Kenneth Graunke (4):</p>
+<ul>
+ <li>i965: Document the sad story of the kernel command parser.</li>
+ <li>i965: Set screen->cmd_parser_version to 0 if we can't write registers.</li>
+ <li>i965: Skip register write detection when possible.</li>
+ <li>i965: Set kernel features before computing max GL version.</li>
+</ul>
+
+<p>Marek Olšák (1):</p>
+<ul>
+ <li>targets: export radeon winsys_create functions to silence LLVM warning</li>
+</ul>
+
+<p>Michal Srb (1):</p>
+<ul>
+ <li>st: Add cubeMapFace parameter to st_finalize_texture.</li>
+</ul>
+
+<p>Thomas Hellstrom (1):</p>
+<ul>
+ <li>gbm/dri: Flush after unmap</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 0feeceb11c35bbd9da3f7ed0b18119e124a6d6cf
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Apr 17 14:33:57 2017 +0100
Update version to 17.0.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index cc64c91..ea2195e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.0.3
+17.0.4
commit 0e032a434fab936d9f9c47d52f3a8e0fcd50ae0f
Author: Fabio Estevam <festevam@gmail.com>
Date: Sat Mar 4 19:07:27 2017 -0300
loader: Move non-error message to debug level
Currently when running mesa on imx6 the following loader warnings
are seen:
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
Using display 0x1920948 with EGL version 1.4
As this is not an error message, change it to debug level in
order to have a cleaner log output.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 78c57726335fe22cb4579bcf562d2394adc234b5)
Nominated-by: Rob Clark <robdclark@gmail.com> (IRC)
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 449ff54..b758216 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -282,7 +282,7 @@ drm_get_pci_id_for_fd(int fd, int *vendor_id, int *chip_id)
ret = 1;
}
else {
- log_(_LOADER_WARNING, "MESA-LOADER: device is not located on the PCI bus\n");
+ log_(_LOADER_DEBUG, "MESA-LOADER: device is not located on the PCI bus\n");
ret = 0;
}
drmFreeDevice(&device);
commit b7d3c71d649348e0454c9a1a180cfeefcbea6452
Author: Alex Smith <asmith@feralinteractive.com>
Date: Thu Mar 30 21:03:58 2017 +0200
radv: Invalidate L2 for TRANSFER_WRITE barriers
CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write
through L2. Therefore, to make these writes visible to later accesses
we must invalidate L2 rather than just writing it back, to avoid the
possibility that stale data is read through L2.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
[Bas: patch is a backport for 17.0 of the cherry-pick below]
(cherry picked from commit bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 628737c..3aa415b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2580,7 +2580,8 @@ void radv_CmdPipelineBarrier(
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
break;
case VK_ACCESS_TRANSFER_WRITE_BIT:
- flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
+ flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+ RADV_CMD_FLAG_INV_GLOBAL_L2;
break;
default:
break;
commit a6114f0c4e619a1192062dc8dce91a67032faeb1
Author: Julien Isorce <jisorce@oblong.com>
Date: Wed Mar 15 17:40:25 2017 +0000
radeon_drm_bo: explicitly check return value of drmCommandWriteRead
CID 1313492
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 521860b2a92bab6394546e6af8709c07e2292033)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index cefb51f..6c6b790 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -186,8 +186,13 @@ static enum radeon_bo_domain radeon_bo_get_initial_domain(
args.handle = bo->handle;
args.op = RADEON_GEM_OP_GET_INITIAL_DOMAIN;
- drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_OP,
- &args, sizeof(args));
+ if (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_OP,
+ &args, sizeof(args))) {
+ fprintf(stderr, "radeon: failed to get initial domain: %p 0x%08X\n",
+ bo, bo->handle);
+ /* Default domain as returned by get_valid_domain. */
+ return RADEON_DOMAIN_VRAM_GTT;
+ }
/* GEM domains and winsys domains are defined the same. */
return get_valid_domain(args.value);
commit 0f51d37f733f8b6ecbe444fbf2536cd403d3f285
Author: Julien Isorce <jisorce@oblong.com>
Date: Mon Feb 27 13:42:17 2017 +0000
radeon: initialize hole variable before calling container_of
Like in a few other places in that radeon_drm_bo.c file.
CID 715739.
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit ce27b27c38acd5a92cf45e7ddc2434f2c04191ee)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99515
Nominated-by: Mauro Rossi <issor.oruam@gmail.com>
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index a15d559..cefb51f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -258,7 +258,7 @@ static uint64_t radeon_bomgr_find_va(struct radeon_drm_winsys *rws,
static void radeon_bomgr_free_va(struct radeon_drm_winsys *rws,
uint64_t va, uint64_t size)
{
- struct radeon_bo_va_hole *hole;
+ struct radeon_bo_va_hole *hole = NULL;
size = align(size, rws->info.gart_page_size);
commit 1b2bcb6826ff8855e96117c9523821336a3be88a
Author: Julien Isorce <julien.isorce@gmail.com>
Date: Fri Mar 10 17:20:56 2017 +0000
winsys/radeon: check null return from radeon_cs_create_fence in cs_flush
Follow-up of patch:
"radeon_cs_create_fence: check null return from radeon_winsys_bo_create"
radeon_drm_cs_flush
radeon_cs_create_fence
radeon_winsys_bo_create
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit d08c0930af8aaef5bdf80df618bb906e0b349830)
[Emil Velikov: resolve trivial conflicts]
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index fd52a40..2ca0950 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -593,18 +593,20 @@ static int radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
fence = radeon_cs_create_fence(rcs);
}
- if (pfence)
- radeon_fence_reference(pfence, fence);
-
- pipe_mutex_lock(cs->ws->bo_fence_lock);
- for (unsigned i = 0; i < cs->csc->num_slab_buffers; ++i) {
- struct radeon_bo *bo = cs->csc->slab_buffers[i].bo;
- p_atomic_inc(&bo->num_active_ioctls);
- radeon_bo_slab_fence(bo, (struct radeon_bo *)fence);
- }
- pipe_mutex_unlock(cs->ws->bo_fence_lock);
+ if (fence) {
+ if (pfence)
+ radeon_fence_reference(pfence, fence);
+
+ pipe_mutex_lock(cs->ws->bo_fence_lock);
+ for (unsigned i = 0; i < cs->csc->num_slab_buffers; ++i) {
+ struct radeon_bo *bo = cs->csc->slab_buffers[i].bo;
+ p_atomic_inc(&bo->num_active_ioctls);
+ radeon_bo_slab_fence(bo, (struct radeon_bo *)fence);
+ }
+ pipe_mutex_unlock(cs->ws->bo_fence_lock);
- radeon_fence_reference(&fence, NULL);
+ radeon_fence_reference(&fence, NULL);
+ }
} else {
radeon_fence_reference(&cs->next_fence, NULL);
}
commit 99468c236f09211fcc4716efd400c039079c9a40
Author: Julien Isorce <julien.isorce@gmail.com>
Date: Fri Mar 10 17:16:05 2017 +0000
winsys/radeon: check null in radeon_cs_create_fence
Fixes the following segmentation fault:
radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
-> if (!bo->handle)
(gdb) bt
0 radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
1 0x00007fffe73575de in radeon_cs_create_fence radeon_drm_cs.c
2 0x00007fffe7358c48 in radeon_drm_cs_flush radeon_drm_cs.c
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit d09edb01468ca385b6a8ffe29ac434dc42a78d07)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 8f9e8a6..fd52a40 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -750,6 +750,9 @@ radeon_cs_create_fence(struct radeon_winsys_cs *rcs)
/* Create a fence, which is a dummy BO. */
fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1,
RADEON_DOMAIN_GTT, RADEON_FLAG_HANDLE);
+ if (!fence)
+ return NULL;
+
/* Add the fence as a dummy relocation. */
cs->ws->base.cs_add_buffer(rcs, fence,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT,
commit c0a73ddda801c6cde0183735625dea95842f9c27
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Wed Apr 12 12:05:25 2017 +0100
Revert "freedreno: fix memory leak"
This reverts commit c57a03585052e3bd7d61d1307cae9a922e663c20.
As requested by Rob Clark
"This seems to be causing a performance regression (reported by
Nicolas).. and the leak it fixes is quite hypothetical. (Ie. hit by
apps that destroy/create context many times.)
On master, I think this can be solved by switching on 'reorder' by
default but that is probably too much of a behaviour change for
stable."
diff --git a/src/gallium/drivers/freedreno/freedreno_draw.c b/src/gallium/drivers/freedreno/freedreno_draw.c
index 319e2eb..cfe13cd 100644
--- a/src/gallium/drivers/freedreno/freedreno_draw.c
+++ b/src/gallium/drivers/freedreno/freedreno_draw.c
@@ -264,8 +264,6 @@ fd_blitter_clear(struct pipe_context *pctx, unsigned buffers,
util_blitter_restore_constant_buffer_state(blitter);
util_blitter_restore_vertex_states(blitter);
util_blitter_restore_fragment_states(blitter);
- util_blitter_restore_textures(blitter);
- util_blitter_restore_fb_state(blitter);
util_blitter_restore_render_cond(blitter);
util_blitter_unset_running_flag(blitter);
commit f3ae08bd44533aac51134dee4c8ed94a0a86a966
Author: Jerome Duval <jerome.duval@gmail.com>
Date: Wed Feb 22 16:02:51 2017 +0000
haiku/winsys: fix dt prototype args
Add the missing front_private, introduced with earlier commit.
(cherry picked from commit 62e27170a7f7a90091b4121002b7ce209ac7ccb0)
Fixes: 2b676570960 ("gallium/swrast: fix front buffer blitting. (v2)")
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/gallium/winsys/sw/hgl/hgl_sw_winsys.c b/src/gallium/winsys/sw/hgl/hgl_sw_winsys.c
index 89dd547..f7bc907 100644
--- a/src/gallium/winsys/sw/hgl/hgl_sw_winsys.c
+++ b/src/gallium/winsys/sw/hgl/hgl_sw_winsys.c
@@ -106,7 +106,8 @@ hgl_winsys_convert_cs(enum pipe_format format)
static struct sw_displaytarget*
hgl_winsys_displaytarget_create(struct sw_winsys* winsys,
unsigned textureUsage, enum pipe_format format, unsigned width,
- unsigned height, unsigned alignment, unsigned* stride)
+ unsigned height, unsigned alignment, const void *front_private,
+ unsigned* stride)
{
struct haiku_displaytarget* haikuDisplayTarget
= CALLOC_STRUCT(haiku_displaytarget);
commit c1c39334dac70cbb5bce2a274e538cd2977023a7
Author: Jerome Duval <jerome.duval@gmail.com>
Date: Wed Feb 22 16:01:24 2017 +0000
haiku: build fixes around debug defines
Move the os/os_misc.h include further up, since it's the one that
implicitly provides the PIPE_OS_HAIKU define.
(cherry picked from commit 40b0c8666c337fd0fdff42ce70703cd300abcf0c)
Fixes: 373f118c6c7 ("gallium: do not wrap header inclusion in")
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/src/gallium/auxiliary/util/u_debug.h b/src/gallium/auxiliary/util/u_debug.h
index 7da7f53..63940b7 100644
--- a/src/gallium/auxiliary/util/u_debug.h
+++ b/src/gallium/auxiliary/util/u_debug.h
@@ -39,13 +39,13 @@
#define U_DEBUG_H_
+#include "os/os_misc.h"
+
#if defined(PIPE_OS_HAIKU)
/* Haiku provides debug_printf in libroot with OS.h */
#include <OS.h>
#endif
-#include "os/os_misc.h"
-
#include "pipe/p_format.h"
#include "pipe/p_defines.h"
commit a8e217d057a25584949f57093684fe9b4978dbf0
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Apr 11 08:33:20 2017 -0700
i965: Set kernel features before computing max GL version.
We check these bitfields when computing the Haswell max GL version.
We need to set them ahead of time, or they won't exist, and all our
checks will fail. That sets the max core profile GL version to 4.2.
This introduces the bizarre situation where asking for a GL context
with version 4.3+ fails, but asking for a GL core profile context
with version <= 4.2 actually promotes you a 4.5 context.
GLX_MESA_query_renderer also reported the bogus 4.2 value.
Now it shows 4.5.
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reported-and-tested-by: Rafael Ristovski <rafael.ristovski@gmail.com>
(cherry picked from commit 02ccd8f52cffcc25e5fefdd0f900cf04230395f4)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_screen.c
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 5d1c768..9924dcb 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1858,6 +1858,30 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
}
+ if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 2)
+ screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
+
+ /* Haswell requires command parser version 4 in order to have L3
+ * atomic scratch1 and chicken3 bits
+ */
+ if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) {
+ screen->kernel_features |=
+ KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
+ }
+
+ /* Haswell requires command parser version 6 in order to write to the
+ * MI_MATH GPR registers, and version 7 in order to use
+ * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
+ */
+ if (screen->devinfo.gen >= 8 ||
+ (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) {
+ screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
+ }
+
+ /* Gen7 needs at least command parser version 5 to support compute */
+ if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5)
+ screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
+
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
screen->winsys_msaa_samples_override =
@@ -1889,30 +1913,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
(ret != -1 || errno != EINVAL);
}
- if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 2)
- screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
-
- /* Haswell requires command parser version 4 in order to have L3
- * atomic scratch1 and chicken3 bits
- */
- if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) {
- screen->kernel_features |=
- KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
- }
-
- /* Haswell requires command parser version 6 in order to write to the
- * MI_MATH GPR registers, and version 7 in order to use
- * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
- */
- if (screen->devinfo.gen >= 8 ||
- (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) {
- screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
- }
-
- /* Gen7 needs at least command parser version 5 to support compute */
- if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5)
- screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
-
dri_screen->extensions = !screen->has_context_reset_notification
? screenExtensions : intelRobustScreenExtensions;
commit 05eb1c7f5935733ffc24e373e8ad9d94c14a737a
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Mar 2 18:27:32 2017 -0800
i965: Skip register write detection when possible.
Detecting register write support by trial and error introduces a
stall at screen creation time, which it would be nice to avoid.
Certain command parser versions guarantee this will work (see the
giant comment in intelInitScreen2 below, or a few commits ago):
- Ivybridge: version >= 1 (kernel v3.16)
- Baytrail: version >= 2 (kernel v3.19)
- Haswell: version >= 7 (kernel v4.8)
For simplicity, we don't bother with version 1 in this patch.
This assumes that the user hasn't disabled aliasing PPGTT via a kernel
command line parameter. Don't do that - you're only breaking things.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 5e29af5f772c1e1b02a4cc46d2f7d3b5d2151ad8)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 61b001e..5d1c768 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1346,13 +1346,19 @@ err:
static bool
intel_detect_pipelined_so(struct intel_screen *screen)
{
+ const struct gen_device_info *devinfo = &screen->devinfo;
+
/* Supposedly, Broadwell just works. */
- if (screen->devinfo.gen >= 8)
+ if (devinfo->gen >= 8)
return true;
- if (screen->devinfo.gen <= 6)
+ if (devinfo->gen <= 6)
return false;
+ /* See the big explanation about command parser versions below */
+ if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2))
+ return true;
+
/* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
* statistics registers), and we already reset it to zero before using it.
*/
commit e7f872f7b8a897e188cf7b0462867c8f0b5d9397
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Mar 2 18:21:31 2017 -0800
i965: Set screen->cmd_parser_version to 0 if we can't write registers.
If we can't write registers, then the effective command parser version
is 0 - it may exist, but it's not usefully enabling anything.
See kernel commit 1ca3712ca3429a617ed6c5f87718e4f6fe4ae0c6 (in v4.8)
where the kernel starts doing this for us. This makes us do more or
less the same thing on older kernels.
This should preserve a bit of sanity by allowing us to perform a
screen->cmd_parser_version > N check to determine that we really can
use the features promised by command parser version N.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 31693a13f8fbc52d4f19f1e8800a4edabeecbe19)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_screen.c
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 47c7806..61b001e 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1839,8 +1839,18 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
* means that we can no longer use it as an indicator of the
* age of the kernel.
*/
- if (intel_detect_pipelined_so(screen))
+ if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
+ &screen->cmd_parser_version) < 0) {
+ /* Command parser does not exist - getparam is unrecognized */
+ screen->cmd_parser_version = 0;
+ }
+
+ if (!intel_detect_pipelined_so(screen)) {
+ /* We can't do anything, so the effective version is 0. */
+ screen->cmd_parser_version = 0;
+ } else {
screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
+ }
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
@@ -1873,11 +1883,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
(ret != -1 || errno != EINVAL);
}
- if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
- &screen->cmd_parser_version) < 0) {
- screen->cmd_parser_version = 0;
- }
-
if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 2)
screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
commit 20319f5e88837bdd4561724dbf0bfdf6da4060f1
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Mar 2 18:12:28 2017 -0800
i965: Document the sad story of the kernel command parser.
This should help us figure out the complexities of which kernel
versions we need to get various features on various platforms.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 4a2ad6b145b4dd0d19a8e5e0ee6bed09e08ce0eb)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 3450039..47c7806 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1742,6 +1742,103 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
screen->subslice_total = 1 << (screen->devinfo.gt - 1);
}
+ /* Gen7-7.5 kernel requirements / command parser saga:
+ *
+ * - pre-v3.16:
+ * Haswell and Baytrail cannot use any privileged batchbuffer features.
+ *
+ * Ivybridge has aliasing PPGTT on by default, which accidentally marks
+ * all batches secure, allowing them to use any feature with no checking.
+ * This is effectively equivalent to a command parser version of
+ * \infinity - everything is possible.
+ *
+ * The command parser does not exist, and querying the version will
+ * return -EINVAL.
+ *
+ * - v3.16:
+ * The kernel enables the command parser by default, for systems with
+ * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
+ * hardware checker is still enabled, so Haswell and Baytrail cannot
+ * do anything.
+ *
+ * Ivybridge goes from "everything is possible" to "only what the
+ * command parser allows" (if the user boots with i915.cmd_parser=0,
+ * then everything is possible again). We can only safely use features
+ * allowed by the supported command parser version.
+ *
+ * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
+ * implemented by the kernel, even if it's turned off. So, checking
+ * for version > 0 does not mean that you can write registers. We have
+ * to try it and see. The version does, however, indicate the age of
+ * the kernel.
+ *
+ * Instead of matching the hardware checker's behavior of converting
+ * privileged commands to MI_NOOP, it makes execbuf2 start returning
+ * -EINVAL, making it dangerous to try and use privileged features.
+ *
+ * Effective command parser versions:
+ * - Haswell: 0 (reporting 1, writes don't work)
+ * - Baytrail: 0 (reporting 1, writes don't work)
+ * - Ivybridge: 1 (enabled) or infinite (disabled)
+ *
+ * - v3.17:
+ * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
+ * effectively version 1 (enabled) or infinite (disabled).
+ *
+ * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
+ * Command parser v2 supports predicate writes.
+ *
+ * - Haswell: 0 (reporting 1, writes don't work)
+ * - Baytrail: 2 (enabled) or infinite (disabled)
+ * - Ivybridge: 2 (enabled) or infinite (disabled)
+ *
+ * So version >= 2 is enough to know that Ivybridge and Baytrail
+ * will work. Haswell still can't do anything.
+ *
+ * - v4.0: Version 3 happened. Largely not relevant.
+ *
+ * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
+ * L3 config registers are properly saved and restored as part
+ * of the hardware context. We can approximately detect this point
+ * in time by checking if I915_PARAM_REVISION is recognized - it
+ * landed in a later commit, but in the same release cycle.
+ *
+ * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
+ * Command parser finally gains secure batch promotion. On Haswell,
+ * the hardware checker gets disabled, which finally allows it to do
+ * privileged commands.
+ *
+ * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
+ * - Haswell: 3 (enabled) or 0 (disabled)
+ * - Baytrail: 3 (enabled) or infinite (disabled)
+ * - Ivybridge: 3 (enabled) or infinite (disabled)
+ *
+ * Unfortunately, detecting this point in time is tricky, because
+ * no version bump happened when this important change occurred.
+ * On Haswell, if we can write any register, then the kernel is at
+ * least this new, and we can start trusting the version number.
+ *
+ * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
+ * Command parser reaches version 4, allowing access to Haswell
+ * atomic scratch and chicken3 registers. If version >= 4, we know
+ * the kernel is new enough to support privileged features on all
+ * hardware. However, the user might have disabled it...and the
+ * kernel will still report version 4. So we still have to guess
+ * and check.
+ *
+ * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
+ * Command parser v5 whitelists indirect compute shader dispatch
+ * registers, needed for OpenGL 4.3 and later.
+ *
+ * - v4.8:
+ * Command parser v7 lets us use MI_MATH on Haswell.
+ *
+ * Additionally, the kernel begins reporting version 0 when
+ * the command parser is disabled, allowing us to skip the
+ * guess-and-check step on Haswell. Unfortunately, this also
+ * means that we can no longer use it as an indicator of the
+ * age of the kernel.
+ */
if (intel_detect_pipelined_so(screen))
screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
commit a0a48b641dd15607bed7b0c735a280067dca0e93
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat Apr 8 18:31:35 2017 -0400
nouveau: when mapping a persistent buffer, synchronize on former xfers
If the buffer is being used, we should wait for those uses to be
complete before returning the map.
Fixes: GL45-CTS.direct_state_access.buffers_functional
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d9cc58d6ec56e676b1285508a4118a83f5325833)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c b/src/gallium/drivers/nouveau/nouveau_buffer.c
index 17052b2..2c60441 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -406,9 +406,6 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe,
!util_ranges_intersect(&buf->valid_buffer_range, box->x, box->x + box->width))
usage |= PIPE_TRANSFER_DISCARD_RANGE | PIPE_TRANSFER_UNSYNCHRONIZED;
- if (usage & PIPE_TRANSFER_PERSISTENT)
- usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
-
if (buf->domain == NOUVEAU_BO_VRAM) {
if (usage & NOUVEAU_TRANSFER_DISCARD) {
/* Set up a staging area for the user to write to. It will be copied
@@ -476,7 +473,8 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe,
* complete its operation, or set up a staging area to perform our work in.
*/
if (nouveau_buffer_busy(buf, usage & PIPE_TRANSFER_READ_WRITE)) {
- if (unlikely(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)) {
+ if (unlikely(usage & (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
+ PIPE_TRANSFER_PERSISTENT))) {
/* Discarding was not possible, must sync because
* subsequent transfers might use UNSYNCHRONIZED. */
nouveau_buffer_sync(nv, buf, usage & PIPE_TRANSFER_READ_WRITE);
commit b6168c3b83d750cb0db2d6a4ae6ee52e2e520292
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat Apr 8 14:56:16 2017 -0400
nvc0: increase texture buffer object alignment to 256 for pre-GM107
We currently don't pass the low byte of the address via the surface
info, so in order to work with images, these have to implicitly be
aligned to 256. The proprietary driver also doesn't go out of its way to
provide lower alignment.
Fixes GL45-CTS.texture_buffer.texture_buffer_texture_buffer_range
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 8036809799c453b02f4c8fedbb5faaeb19af90c2)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 8aef7c9..8477d66 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -147,7 +147,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- if (class_3d < NVE4_3D_CLASS)
+ if (class_3d < GM107_3D_CLASS)
return 256; /* IMAGE bindings require alignment to 256 */
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