mesa: Changes to 'ubuntu'
VERSION | 2
bin/.cherry-ignore | 2
debian/changelog | 18 +
debian/control | 14 -
debian/rules | 4
docs/relnotes/17.0.1.html | 3
docs/relnotes/17.0.2.html | 184 ++++++++++++++++++++
src/amd/common/ac_nir_to_llvm.c | 17 +
src/amd/common/ac_nir_to_llvm.h | 4
src/amd/vulkan/radv_cmd_buffer.c | 5
src/amd/vulkan/radv_device.c | 2
src/amd/vulkan/radv_formats.c | 3
src/amd/vulkan/radv_image.c | 3
src/amd/vulkan/radv_meta_buffer.c | 2
src/compiler/nir/nir_intrinsics.h | 4
src/egl/drivers/dri2/egl_dri2.c | 14 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 4
src/gallium/drivers/radeonsi/si_descriptors.c | 3
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 10 +
src/intel/vulkan/anv_blorp.c | 35 ++-
src/intel/vulkan/anv_device.c | 10 -
src/intel/vulkan/anv_image.c | 9
src/intel/vulkan/anv_pass.c | 22 +-
src/mapi/glapi/gen/gl_API.xml | 2
src/mesa/drivers/dri/i965/brw_defines.h | 6
src/mesa/drivers/dri/i965/brw_fs.cpp | 47 +++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 47 ++---
src/mesa/main/fbobject.c | 2
src/mesa/state_tracker/st_atom.c | 10 -
src/mesa/state_tracker/st_cb_readpixels.c | 13 +
src/mesa/state_tracker/st_cb_texture.c | 6
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 11 -
src/util/ralloc.c | 15 +
src/vulkan/wsi/wsi_common_x11.c | 51 ++++-
36 files changed, 486 insertions(+), 104 deletions(-)
New commits:
commit 12a04e733dd81df7b57a51a9e814f5d9134c2f44
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Mar 21 16:20:07 2017 +0200
upload to zesty
diff --git a/debian/changelog b/debian/changelog
index 4853fd0..38ee0c7 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.0.2-1ubuntu1) zesty; urgency=medium
+
+ * Merge from Debian experimental.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 21 Mar 2017 13:36:51 +0200
+
mesa (17.0.2-1) experimental; urgency=medium
[ Timo Aaltonen ]
commit c639f2f27663d635464079b852592d1f68bb9e6b
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Tue Mar 21 11:35:20 2017 +0100
Upload to experimental.
diff --git a/debian/changelog b/debian/changelog
index 85317ef..3959bee 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (17.0.2-1) UNRELEASED; urgency=medium
+mesa (17.0.2-1) experimental; urgency=medium
[ Timo Aaltonen ]
* New upstream release.
@@ -8,7 +8,7 @@ mesa (17.0.2-1) UNRELEASED; urgency=medium
- Enables radeonsi, llvmpipe and radv drivers.
- Enables OpenCL support.
- -- Timo Aaltonen <tjaalton@debian.org> Tue, 21 Mar 2017 09:30:52 +0200
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Tue, 21 Mar 2017 11:35:09 +0100
mesa (17.0.1-1) experimental; urgency=medium
commit df9a7e6e71925c3a9ddd426302a3e9bb4e5fc34d
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Tue Mar 21 10:46:40 2017 +0100
Require LLVM on sparc64
- Enables radeonsi, llvmpipe and radv drivers.
- Enables OpenCL support.
diff --git a/debian/changelog b/debian/changelog
index 7688c5a..85317ef 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,7 +1,13 @@
mesa (17.0.2-1) UNRELEASED; urgency=medium
+ [ Timo Aaltonen ]
* New upstream release.
+ [ Andreas Boll ]
+ * Require LLVM on sparc64:
+ - Enables radeonsi, llvmpipe and radv drivers.
+ - Enables OpenCL support.
+
-- Timo Aaltonen <tjaalton@debian.org> Tue, 21 Mar 2017 09:30:52 +0200
mesa (17.0.1-1) experimental; urgency=medium
diff --git a/debian/control b/debian/control
index 26a3ba1..bbbd6ef 100644
--- a/debian/control
+++ b/debian/control
@@ -20,7 +20,7 @@ Build-Depends:
libxext-dev,
libva-dev (>= 1.6.0) [linux-any kfreebsd-any],
libvdpau-dev (>= 1.1.1) [linux-any kfreebsd-any],
- libvulkan-dev [amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el x32],
+ libvulkan-dev [amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el sparc64 x32],
autoconf,
automake,
libtool,
@@ -41,11 +41,11 @@ Build-Depends:
python-mako,
flex,
bison,
- llvm-4.0-dev (>= 1:4.0~) [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el],
- libelf-dev [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el],
+ llvm-4.0-dev (>= 1:4.0~) [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el],
+ libelf-dev [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el],
libwayland-dev (>= 1.11.0) [linux-any],
- libclang-4.0-dev (>= 1:4.0~) [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el],
- libclc-dev (>= 0.2.0+git20170213) [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el],
+ libclang-4.0-dev (>= 1:4.0~) [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el],
+ libclc-dev (>= 0.2.0+git20170213) [amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el],
Vcs-Git: https://anonscm.debian.org/git/pkg-xorg/lib/mesa.git
Vcs-Browser: https://anonscm.debian.org/cgit/pkg-xorg/lib/mesa.git
Homepage: https://mesa3d.org/
@@ -410,7 +410,7 @@ Description: Mesa VDPAU video acceleration drivers
Package: mesa-vulkan-drivers
Section: libs
-Architecture: amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el x32
+Architecture: amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el sparc64 x32
Pre-Depends: ${misc:Pre-Depends}
Depends:
libvulkan1,
@@ -423,7 +423,7 @@ Description: Mesa Vulkan graphics drivers
Package: mesa-opencl-icd
Section: libs
-Architecture: amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el
+Architecture: amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el
Pre-Depends: ${misc:Pre-Depends}
Depends:
libclc-r600 (>= 0.2.0+git20170213),
diff --git a/debian/rules b/debian/rules
index 515e9c7..a0501e7 100755
--- a/debian/rules
+++ b/debian/rules
@@ -83,7 +83,7 @@ else
# LLVM is required for building r300g, radeonsi and llvmpipe drivers.
# It's also required for building OpenCL support.
- ifneq (,$(filter $(DEB_HOST_ARCH), amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 ppc64el))
+ ifneq (,$(filter $(DEB_HOST_ARCH), amd64 arm64 armel armhf i386 kfreebsd-amd64 kfreebsd-i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el))
GALLIUM_DRIVERS += radeonsi
confflags_GALLIUM += --enable-gallium-llvm
confflags_GALLIUM += --enable-opencl --enable-opencl-icd
@@ -96,7 +96,7 @@ else
# radv needs LLVM and the Vulkan loader, so only build on the subset of
# arches where we have LLVM enabled and where the Vulkan loader is built.
- ifneq (,$(filter $(DEB_HOST_ARCH), amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el))
+ ifneq (,$(filter $(DEB_HOST_ARCH), amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 sparc64 ppc64el))
VULKAN_DRIVERS += radeon
endif
commit b6cb4c55a05c0f4a1d16c999741958811faee3d1
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Mar 21 10:34:30 2017 +0200
update the changelog
diff --git a/debian/changelog b/debian/changelog
index bd49212..7688c5a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (17.0.2-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 21 Mar 2017 09:30:52 +0200
+
mesa (17.0.1-1) experimental; urgency=medium
[ Timo Aaltonen ]
commit 373d88a7117150de984510453e1c30a455987686
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Mar 20 14:07:38 2017 +0000
docs: add release notes for 17.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/17.0.2.html b/docs/relnotes/17.0.2.html
new file mode 100644
index 0000000..ed4c7db
--- /dev/null
+++ b/docs/relnotes/17.0.2.html
@@ -0,0 +1,184 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.0.2 Release Notes / March 20, 2017</h1>
+
+<p>
+Mesa 17.0.2 is a bug fix release which fixes bugs found since the 17.0.1 release.
+</p>
+<p>
+Mesa 17.0.2 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=68504";>Bug 68504</a> - 9.2-rc1 workaround for clover build failure on ppc/altivec: cannot convert 'bool' to '__vector(4) __bool int' in return</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97988";>Bug 97988</a> - [radeonsi] playing back videos with VDPAU exhibits deinterlacing/anti-aliasing issues not visible with VA-API</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99484";>Bug 99484</a> - Crusader Kings 2 - Loading bars, siege bars, morale bars, etc. do not render correctly</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=99715";>Bug 99715</a> - Don't print: "Note: Buggy applications may crash, if they do please report to vendor"</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=100049";>Bug 100049</a> - "ralloc: Make sure ralloc() allocations match malloc()'s alignment." causes seg fault in 32bit build</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alex Smith (3):</p>
+<ul>
+ <li>radv: Emit pending flushes before executing a secondary command buffer</li>
+ <li>radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer</li>
+ <li>radv/ac: Fix shared memory offset calculation</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (3):</p>
+<ul>
+ <li>radv: Disable HTILE for textures with multiple layers/levels.</li>
+ <li>radv: Emit cache flushes before CP DMA.</li>
+ <li>Revert "radv: Emit cache flushes before CP DMA."</li>
+</ul>
+
+<p>Dave Airlie (3):</p>
+<ul>
+ <li>radv: drop Z24 support.</li>
+ <li>radv: disable mip point pre clamping.</li>
+ <li>radv: setup llvm target data layout</li>
+</ul>
+
+<p>Emil Velikov (4):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.0.1</li>
+ <li>cherry-ignore: add the swizzle blorp_clear fix</li>
+ <li>i965: move brw_define.h ifndef guard to the top</li>
+ <li>Update version to 17.0.2</li>
+</ul>
+
+<p>Fredrik Höglund (2):</p>
+<ul>
+ <li>radv: fix the dynamic buffer index in vkCmdBindDescriptorSets</li>
+ <li>radv/ac: fix multiple descriptor sets with dynamic buffers</li>
+</ul>
+
+<p>Gregory Hainaut (1):</p>
+<ul>
+ <li>glapi: fix typo in count_scale</li>
+</ul>
+
+<p>Ilia Mirkin (2):</p>
+<ul>
+ <li>nvc0: take extra pushbuf space into account for pushbuf_space calls</li>
+ <li>nvc0: increase alignment to 256 for texture buffers on fermi</li>
+</ul>
+
+<p>Jacob Lifshay (1):</p>
+<ul>
+ <li>vulkan/wsi: Improve the DRI3 error message</li>
+</ul>
+
+<p>James Legg (1):</p>
+<ul>
+ <li>radv: Fix using more than 4 bound descriptor sets</li>
+</ul>
+
+<p>Jason Ekstrand (7):</p>
+<ul>
+ <li>anv/blorp/clear_subpass: Only set surface clear color for fast clears</li>
+ <li>anv: Accurately advertise dynamic descriptor limits</li>
+ <li>anv: Stall before fast-clear operations</li>
+ <li>anv: Properly handle destroying NULL devices and instances</li>
+ <li>anv/blorp: Turn off AUX after doing a CCS_D resolve</li>
+ <li>anv/blorp: Only set a clear color for resolves if fast-cleared</li>
+ <li>nir/intrinsics: Make load_barycentric_input take a 2-component coor</li>
+</ul>
+
+<p>Jonas Pfeil (1):</p>
+<ul>
+ <li>ralloc: Make sure ralloc() allocations match malloc()'s alignment.</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>egl: Ensure ResetNotificationStrategy matches for shared contexts.</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+ <li>st/mesa: reset sample_mask, min_sample, and render_condition for PBO ops</li>
+ <li>st/mesa: set blend state for PBO readbacks</li>
+ <li>radeonsi: mark all bound shader buffer ranges as initialized</li>
+</ul>
+
+<p>Matt Turner (1):</p>
+<ul>
+ <li>clover: Work around build failure with AltiVec.</li>
+</ul>
+
+<p>Nanley Chery (2):</p>
+<ul>
+ <li>anv/pass: Avoid accessing attachment array out of bounds</li>
+ <li>anv/image: Remove extra dependency on HiZ-specific variable</li>
+</ul>
+
+<p>Nicolai Hähnle (2):</p>
+<ul>
+ <li>st/glsl_to_tgsi: avoid iterating past the head of the instruction list</li>
+ <li>st/mesa: inform the driver of framebuffer changes before compute dispatches</li>
+</ul>
+
+<p>Robert Foss (1):</p>
+<ul>
+ <li>mesa: Avoid read of uninitialized variable</li>
+</ul>
+
+<p>Samuel Iglesias Gonsálvez (5):</p>
+<ul>
+ <li>i965/fs: mark last DF uniform array element as 64 bit live one</li>
+ <li>i965/fs: detect different bit size accesses to uniforms to push them in proper locations</li>
+ <li>i965/fs: fix indirect load DF uniforms on BSW/BXT</li>
+ <li>i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles</li>
+ <li>i965/fs: emit MOV_INDIRECT with the source with the right register type</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+ <li>radeonsi: disable sinking common instructions down to the end block</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit c60ae7b1611ddd43a0996583a1e3b86913d2a48b
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Mar 20 14:02:15 2017 +0000
Update version to 17.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 3e17df0..c57cf9a 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.0.1
+17.0.2
commit 07adc57fe07b3478566dbadab9b9595af3b46944
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Wed Mar 15 18:49:29 2017 +0100
Revert "radv: Emit cache flushes before CP DMA."
This reverts commit cce43f6d8c40222099badaf52344d6a0eed993f3.
Redundant, as the flush already happens at si_cp_dma_prepare.
Acked-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ad4dee521d7968a88393dc3685e7c593d27efba5)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 430ef13..5abb121 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -881,7 +881,6 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
uint64_t main_src_va, main_dest_va;
uint64_t skipped_size = 0, realign_size = 0;
- si_emit_cache_flush(cmd_buffer);
if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
@@ -945,8 +944,6 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
assert(va % 4 == 0 && size % 4 == 0);
- si_emit_cache_flush(cmd_buffer);
-
while (size) {
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
unsigned dma_flags = 0;
commit 13afc45f8fe61467e4e97fd3164308562c7c721f
Author: Alex Smith <asmith@feralinteractive.com>
Date: Thu Mar 16 16:40:07 2017 +0000
radv/ac: Fix shared memory offset calculation
The index passed to get_shared_memory_ptr is an attribute slot index,
i.e. the index of a vec4 within LDS. Therefore this must be scaled by
sizeof(vec4) to give the LDS byte offset.
Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit ce4058dafd2dd283addaa99e8d5b51e53f634f9b)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5b8ee72..496c5ed 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -264,7 +264,7 @@ static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
LLVMValueRef ptr;
int addr_space;
- offset = LLVMConstInt(ctx->i32, idx, false);
+ offset = LLVMConstInt(ctx->i32, idx * 16, false);
ptr = ctx->shared_memory;
ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
commit 06bdbe9f89fcbc1f59612da5658ff492ddb2c62a
Author: James Legg <jlegg@feralinteractive.com>
Date: Thu Mar 16 17:48:13 2017 +0000
radv: Fix using more than 4 bound descriptor sets
Avoid a buffer overflow in ac_nir_to_llvm.c's create_function when
using more than 4 descriptor sets. radv claims support for 8.
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit e88cac1df03d01a9e8a1de1a4a2ee888149e727a)
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index a57558e..2fc3efd 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -27,6 +27,7 @@
#include "llvm-c/Core.h"
#include "llvm-c/TargetMachine.h"
#include "amd_family.h"
+#include "../vulkan/radv_descriptor_set.h"
struct ac_shader_binary;
struct ac_shader_config;
@@ -76,7 +77,8 @@ enum ac_ud_index {
AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
};
-#define AC_UD_MAX_SETS 4
+// Match MAX_SETS from radv_descriptor_set.h
+#define AC_UD_MAX_SETS MAX_SETS
struct ac_userdata_locations {
struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
commit 74c39635b8a9341c2607c11373fac590eca0f689
Author: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Wed Mar 15 00:59:13 2017 +0100
radeonsi: disable sinking common instructions down to the end block
Initially this was a workaround for a bug introduced in LLVM 4.0
in the SimplifyCFG pass that caused image instrinsics to disappear
(because they were badly sunk). Finally, this is a win because it
decreases SGPR spilling and increases the number of waves a bit.
Although, shader-db results are good I think we might want to
remove it in the future once the issue is fixed. For now, enable
it for LLVM >= 4.0.
This also fixes a rendering issue with the speedometer in Dirt Rally.
More information can be found here https://reviews.llvm.org/D26348.
Thanks to Dave Airlie for the patch.
v2: - add a FIXME comment
- use if (HAVE_LLVM >= 0x0400) instead
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99484
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97988
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 7751ed39e40e08e5aa0633d018c9f25ad17f9bb0)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 8d19a4e..c2c0c06 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -41,6 +41,7 @@
#include <stdio.h>
#include <llvm-c/Transforms/IPO.h>
#include <llvm-c/Transforms/Scalar.h>
+#include <llvm-c/Support.h>
/* Data for if/else/endif and bgnloop/endloop control flow structures.
*/
@@ -133,6 +134,15 @@ static void init_amdgpu_target()
LLVMInitializeAMDGPUAsmPrinter();
#endif
+ if (HAVE_LLVM >= 0x0400) {
+ /*
+ * Workaround for bug in llvm 4.0 that causes image intrinsics
+ * to disappear.
+ * https://reviews.llvm.org/D26348
+ */
+ const char *argv[2] = {"mesa", "-simplifycfg-sink-common=false"};
+ LLVMParseCommandLineOptions(2, argv, NULL);
+ }
}
static once_flag init_amdgpu_target_once_flag = ONCE_FLAG_INIT;
commit f85a54a31bd7cfa0fe615eb7302b0787dbd792eb
Author: Alex Smith <asmith@feralinteractive.com>
Date: Tue Mar 14 15:26:32 2017 +0000
radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer
Need to flush before updating the buffer to ensure that the copy is
ordered after previous accesses (assuming the app has performed the
appropriate barriers).
This fixes potential issues due to draws prior to an update reading
the new buffer content, despite having the necessary barriers between
them.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e0cc32b85bd8cf5c2202037838a208983e2d793a)
diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index cd2973f..1e94f3b 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -524,6 +524,8 @@ void radv_CmdUpdateBuffer(
assert(!(va & 3));
if (dataSize < 4096) {
+ si_emit_cache_flush(cmd_buffer);
+
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);
commit 804e260859733b04aaf6d824a25d2ac047d9fc4e
Author: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Tue Mar 14 21:46:54 2017 +0100
radv: Emit cache flushes before CP DMA.
The flushes could be due to TRANSFER barriers.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit cce43f6d8c40222099badaf52344d6a0eed993f3)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 5abb121..430ef13 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -881,6 +881,7 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
uint64_t main_src_va, main_dest_va;
uint64_t skipped_size = 0, realign_size = 0;
+ si_emit_cache_flush(cmd_buffer);
if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
@@ -944,6 +945,8 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
assert(va % 4 == 0 && size % 4 == 0);
+ si_emit_cache_flush(cmd_buffer);
+
while (size) {
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
unsigned dma_flags = 0;
commit f5be65efb7b66894e055e4fce2311a71db730b12
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Mar 2 17:39:11 2017 -0800
nir/intrinsics: Make load_barycentric_input take a 2-component coor
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 60d1aac28a1f44ac166e72262e378e063155d6fd)
diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h
index f45bfe2..5c8f283 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -401,7 +401,9 @@ LOAD(input, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINS
/* src[] = { vertex, offset }. const_index[] = { base, component } */
LOAD(per_vertex_input, 2, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
/* src[] = { barycoord, offset }. const_index[] = { base, component } */
-LOAD(interpolated_input, 2, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
+INTRINSIC(load_interpolated_input, 2, ARR(2, 1), true, 0, 0,
+ 2, BASE, COMPONENT, xx,
+ NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
/* src[] = { buffer_index, offset }. No const_index */
LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
commit 3a4b70b38408ca3e0674a7046fac1c5b0bca84b7
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Mar 2 23:03:03 2017 -0800
anv/blorp: Only set a clear color for resolves if fast-cleared
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 678fd00f2f5b213d0317ba51a8163c4c5bd1f3dc)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 7a38a35..b1d2147 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1502,7 +1502,8 @@ ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
att_state->aux_usage, &surf);
- surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
+ if (att_state->fast_clear)
+ surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
/* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
*
commit 3428b4898dfaba7c5ef2bfacd27c4e9d2ccea298
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Mar 9 16:37:23 2017 -0800
anv/blorp: Turn off AUX after doing a CCS_D resolve
For render passes with multiple subpasses on gen7, we only fast-clear at
the top but an input attachment use can cause us to do a resolve in the
middle of the render pass. Once we've done so, we are no longer have a
fast-cleared surface so we can just set aux_usage to NONE.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 273b720310863c2084c55f1371b2d27c2d96dbda)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index c39fb44..7a38a35 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1531,6 +1531,8 @@ ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
/* Once we've done any sort of resolve, we're no longer fast-cleared */
att_state->fast_clear = false;
+ if (att_state->aux_usage == ISL_AUX_USAGE_CCS_D)
+ att_state->aux_usage = ISL_AUX_USAGE_NONE;
}
void
commit ce7f3521dee76c21e28c92ca8a8f0c09f2efdf96
Author: Matt Turner <mattst88@gmail.com>
Date: Thu Mar 2 04:43:21 2017 +0000
clover: Work around build failure with AltiVec.
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=587210
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68504
Acked-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 7d1195c1e4d071fe796bf5f210c468ea1cc86225)
diff --git a/configure.ac b/configure.ac
index bdcf14d..bd1ac23 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2030,6 +2030,20 @@ if test "x$enable_opencl" = xyes; then
AC_MSG_ERROR([Clover requires libelf])
fi
+ if test "x${ac_cv_cxx_compiler_gnu}" = xyes; then
+ altivec_enabled=no
+ AC_COMPILE_IFELSE([AC_LANG_SOURCE([
+ #if !defined(__VEC__) || !defined(__ALTIVEC__)
+ #error "AltiVec not enabled"
+ #endif
+ ])], altivec_enabled=yes)
+
+ if test "$altivec_enabled" = yes; then
+ CLOVER_STD_OVERRIDE="-std=gnu++11"
+ fi
+ AC_SUBST([CLOVER_STD_OVERRIDE])
+ fi
+
llvm_require_version $LLVM_REQUIRED_OPENCL "opencl"
llvm_add_default_components "opencl"
diff --git a/src/gallium/state_trackers/clover/Makefile.am b/src/gallium/state_trackers/clover/Makefile.am
index 8abcfec..edf1e26 100644
--- a/src/gallium/state_trackers/clover/Makefile.am
+++ b/src/gallium/state_trackers/clover/Makefile.am
@@ -33,6 +33,7 @@ noinst_LTLIBRARIES = libclover.la libcltgsi.la libclllvm.la
libcltgsi_la_CXXFLAGS = \
-std=c++11 \
+ $(CLOVER_STD_OVERRIDE) \
$(VISIBILITY_CXXFLAGS)
libcltgsi_la_SOURCES = $(TGSI_SOURCES)
@@ -41,6 +42,7 @@ libclllvm_la_CXXFLAGS = \
-std=c++11 \
$(VISIBILITY_CXXFLAGS) \
$(LLVM_CXXFLAGS) \
+ $(CLOVER_STD_OVERRIDE) \
$(DEFINES) \
$(LIBELF_CFLAGS) \
-DLIBCLC_INCLUDEDIR=\"$(LIBCLC_INCLUDEDIR)/\" \
@@ -51,6 +53,7 @@ libclllvm_la_SOURCES = $(LLVM_SOURCES)
libclover_la_CXXFLAGS = \
-std=c++11 \
+ $(CLOVER_STD_OVERRIDE) \
$(VISIBILITY_CXXFLAGS)
libclover_la_LIBADD = \
commit 5a11938585a7371548e96873010cb56c3ce186bb
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Wed Mar 1 11:09:30 2017 -0500
nvc0: increase alignment to 256 for texture buffers on fermi
When binding as textures, the alignment can be 16. However when binding
as an image, the address has to be aligned to 256. (Also when binding as
an RT, but that can't happen with GL or current gallium APIs.)
Reported-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 32dd8d59b6d1b6828e16e854d589d0f04536da14)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index ffbe733..8aef7c9 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -147,7 +147,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 16; /* 256 for binding as RT, but that's not possible in GL */
+ if (class_3d < NVE4_3D_CLASS)
+ return 256; /* IMAGE bindings require alignment to 256 */
+ return 16;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 16;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
commit 0b679090a2e1548a27deccc3e38998bbb9347ea2
Author: Gregory Hainaut <gregory.hainaut@gmail.com>
Date: Mon Mar 6 15:25:32 2017 +1100
glapi: fix typo in count_scale
2*4=8
Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 2ab5eccf5de4a68d0d8d2668f6c5244cc6a41846)
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 6e00363..861df7f 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -5858,7 +5858,7 @@
<param name="location" type="GLint"/>
<param name="count" type="GLsizei" counter="true"/>
<param name="transpose" type="GLboolean"/>
- <param name="value" type="const GLfloat *" count="count" count_scale="6"/>
+ <param name="value" type="const GLfloat *" count="count" count_scale="8"/>
<glx ignore="true"/>
</function>
<function name="UniformMatrix4x2fv" es2="3.0">
commit d74d7cc0ff517c67c3f2f55a1e625b04c4001591
Author: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue Feb 28 20:30:57 2017 -0800
vulkan/wsi: Improve the DRI3 error message
This commit improves the message by telling them that they could probably
enable DRI3. More importantly, it includes a little heuristic to check
to see if we're running on AMD or NVIDIA's proprietary X11 drivers and,
if we are, doesn't emit the warning. This way, users with both a discrete
card and Intel graphics don't get the warning when they're just running
on the discrete card.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99715
Co-authored-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Rene Lindsay <rjklindsay@hotmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Cc: "17.0" <mesa-dev@lists.freedesktop.org>
(cherry picked from commit 3d8feb38e8fdbc05b591164cb934b48a495adfbc)
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index 64ba921..323209c 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -49,6 +49,7 @@
struct wsi_x11_connection {
bool has_dri3;
bool has_present;
+ bool is_proprietary_x11;
};
struct wsi_x11 {
@@ -63,8 +64,8 @@ static struct wsi_x11_connection *
wsi_x11_connection_create(const VkAllocationCallbacks *alloc,
xcb_connection_t *conn)
{
- xcb_query_extension_cookie_t dri3_cookie, pres_cookie;
- xcb_query_extension_reply_t *dri3_reply, *pres_reply;
+ xcb_query_extension_cookie_t dri3_cookie, pres_cookie, amd_cookie, nv_cookie;
+ xcb_query_extension_reply_t *dri3_reply, *pres_reply, *amd_reply, *nv_reply;
struct wsi_x11_connection *wsi_conn =
vk_alloc(alloc, sizeof(*wsi_conn), 8,
@@ -75,20 +76,43 @@ wsi_x11_connection_create(const VkAllocationCallbacks *alloc,
dri3_cookie = xcb_query_extension(conn, 4, "DRI3");
pres_cookie = xcb_query_extension(conn, 7, "PRESENT");
+ /* We try to be nice to users and emit a warning if they try to use a
+ * Vulkan application on a system without DRI3 enabled. However, this ends
+ * up spewing the warning when a user has, for example, both Intel
+ * integrated graphics and a discrete card with proprietary drivers and are
+ * running on the discrete card with the proprietary DDX. In this case, we
+ * really don't want to print the warning because it just confuses users.
+ * As a heuristic to detect this case, we check for a couple of proprietary
+ * X11 extensions.
+ */
+ amd_cookie = xcb_query_extension(conn, 11, "ATIFGLRXDRI");
+ nv_cookie = xcb_query_extension(conn, 10, "NV-CONTROL");
+
dri3_reply = xcb_query_extension_reply(conn, dri3_cookie, NULL);
pres_reply = xcb_query_extension_reply(conn, pres_cookie, NULL);
- if (dri3_reply == NULL || pres_reply == NULL) {
+ amd_reply = xcb_query_extension_reply(conn, amd_cookie, NULL);
+ nv_reply = xcb_query_extension_reply(conn, nv_cookie, NULL);
+ if (!dri3_reply || !pres_reply) {
free(dri3_reply);
free(pres_reply);
+ free(amd_reply);
+ free(nv_reply);
vk_free(alloc, wsi_conn);
return NULL;
}
wsi_conn->has_dri3 = dri3_reply->present != 0;
wsi_conn->has_present = pres_reply->present != 0;
+ wsi_conn->is_proprietary_x11 = false;
+ if (amd_reply && amd_reply->present)
+ wsi_conn->is_proprietary_x11 = true;
+ if (nv_reply && nv_reply->present)
+ wsi_conn->is_proprietary_x11 = true;
free(dri3_reply);
free(pres_reply);
+ free(amd_reply);
+ free(nv_reply);
return wsi_conn;
}
@@ -100,6 +124,18 @@ wsi_x11_connection_destroy(const VkAllocationCallbacks *alloc,
vk_free(alloc, conn);
}
+static bool
+wsi_x11_check_for_dri3(struct wsi_x11_connection *wsi_conn)
+{
+ if (wsi_conn->has_dri3)
+ return true;
+ if (!wsi_conn->is_proprietary_x11) {
+ fprintf(stderr, "vulkan: No DRI3 support detected - required for presentation\n"
+ "Note: you can probably enable DRI3 in your Xorg config\n");
+ }
+ return false;
+}
+
static struct wsi_x11_connection *
wsi_x11_get_connection(struct wsi_device *wsi_dev,
const VkAllocationCallbacks *alloc,
@@ -264,11 +300,8 @@ VkBool32 wsi_get_physical_device_xcb_presentation_support(
if (!wsi_conn)
return false;
- if (!wsi_conn->has_dri3) {
- fprintf(stderr, "vulkan: No DRI3 support detected - required for presentation\n");
- fprintf(stderr, "Note: Buggy applications may crash, if they do please report to vendor\n");
+ if (!wsi_x11_check_for_dri3(wsi_conn))
return false;
- }
unsigned visual_depth;
if (!connection_get_visualtype(connection, visual_id, &visual_depth))
@@ -313,9 +346,7 @@ x11_surface_get_support(VkIcdSurfaceBase *icd_surface,
if (!wsi_conn)
return VK_ERROR_OUT_OF_HOST_MEMORY;
- if (!wsi_conn->has_dri3) {
- fprintf(stderr, "vulkan: No DRI3 support detected - required for presentation\n");
- fprintf(stderr, "Note: Buggy applications may crash, if they do please report to vendor\n");
+ if (!wsi_x11_check_for_dri3(wsi_conn)) {
*pSupported = false;
return VK_SUCCESS;
}
commit d1f01d89e177ec51056b819c0aa71d49443e9fb8
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Wed Mar 1 08:39:49 2017 -0800
anv: Properly handle destroying NULL devices and instances
Reply to: