xserver-xorg-video-nouveau: Changes to 'upstream-experimental'
.gitignore | 2
Makefile.am | 15
autogen.sh | 4
configure.ac | 49 ++
man/nouveau.man | 38 +
src/Makefile.am | 82 +++
src/compat-api.h | 9
src/drmmode_display.c | 577 +++++++++++++++++----------
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 ++++++++++++++++++++++++-----------------
src/nouveau_copy.c | 140 ++++++
src/nouveau_copy.h | 18
src/nouveau_copy85b5.c | 104 ++++
src/nouveau_copy90b5.c | 100 ++++
src/nouveau_copya0b5.c | 97 ++++
src/nouveau_dri2.c | 641 ++++++++++++++++++++++--------
src/nouveau_exa.c | 54 +-
src/nouveau_local.h | 2
src/nouveau_present.c | 302 ++++++++++++++
src/nouveau_present.h | 19
src/nouveau_sync.c | 117 +++++
src/nouveau_sync.h | 34 +
src/nouveau_wfb.c | 6
src/nouveau_xv.c | 166 ++++++-
src/nv04_exa.c | 5
src/nv10_exa.c | 22 -
src/nv30_exa.c | 20
src/nv40_exa.c | 8
src/nv50_accel.c | 265 +++++-------
src/nv50_accel.h | 1
src/nv50_exa.c | 115 +----
src/nv50_xv.c | 5
src/nv_accel_common.c | 186 +++++---
src/nv_const.h | 4
src/nv_dma.c | 139 ------
src/nv_driver.c | 444 ++++++++++++++------
src/nv_proto.h | 35 -
src/nv_type.h | 53 +-
src/nvc0_accel.c | 172 ++++++--
src/nvc0_accel.h | 59 ++
src/nvc0_exa.c | 231 +++-------
src/nvc0_shader.h | 444 --------------------
src/nvc0_xv.c | 115 +++--
src/nve0_shader.h | 440 --------------------
src/shader/.gitignore | 1
src/shader/Makefile | 57 ++
src/shader/exac8nv110.fp | 47 ++
src/shader/exac8nv110.fpc | 38 +
src/shader/exac8nvc0.fp | 41 +
src/shader/exac8nvc0.fpc | 22 +
src/shader/exac8nve0.fp | 42 +
src/shader/exac8nve0.fpc | 28 +
src/shader/exac8nvf0.fp | 42 +
src/shader/exac8nvf0.fpc | 28 +
src/shader/exacanv110.fp | 47 ++
src/shader/exacanv110.fpc | 38 +
src/shader/exacanvc0.fp | 41 +
src/shader/exacanvc0.fpc | 25 +
src/shader/exacanve0.fp | 42 +
src/shader/exacanve0.fpc | 28 +
src/shader/exacanvf0.fp | 42 +
src/shader/exacanvf0.fpc | 28 +
src/shader/exacmnv110.fp | 47 ++
src/shader/exacmnv110.fpc | 38 +
src/shader/exacmnvc0.fp | 41 +
src/shader/exacmnvc0.fpc | 25 +
src/shader/exacmnve0.fp | 42 +
src/shader/exacmnve0.fpc | 28 +
src/shader/exacmnvf0.fp | 42 +
src/shader/exacmnvf0.fpc | 28 +
src/shader/exas8nv110.fp | 42 +
src/shader/exas8nv110.fpc | 28 +
src/shader/exas8nvc0.fp | 37 +
src/shader/exas8nvc0.fpc | 14
src/shader/exas8nve0.fp | 38 +
src/shader/exas8nve0.fpc | 20
src/shader/exas8nvf0.fp | 38 +
src/shader/exas8nvf0.fpc | 20
src/shader/exasanv110.fp | 47 ++
src/shader/exasanv110.fpc | 38 +
src/shader/exasanvc0.fp | 41 +
src/shader/exasanvc0.fpc | 25 +
src/shader/exasanve0.fp | 42 +
src/shader/exasanve0.fpc | 28 +
src/shader/exasanvf0.fp | 42 +
src/shader/exasanvf0.fpc | 28 +
src/shader/exascnv110.fp | 38 +
src/shader/exascnv110.fpc | 20
src/shader/exascnvc0.fp | 34 +
src/shader/exascnvc0.fpc | 11
src/shader/exascnve0.fp | 35 +
src/shader/exascnve0.fpc | 14
src/shader/exascnvf0.fp | 35 +
src/shader/exascnvf0.fpc | 14
src/shader/videonv110.fp | 54 ++
src/shader/videonv110.fpc | 52 ++
src/shader/videonvc0.fp | 47 ++
src/shader/videonvc0.fpc | 37 +
src/shader/videonve0.fp | 50 ++
src/shader/videonve0.fpc | 44 ++
src/shader/videonvf0.fp | 47 ++
src/shader/videonvf0.fpc | 38 +
src/shader/xfrm2nv110.vp | 82 +++
src/shader/xfrm2nv110.vpc | 102 ++++
src/shader/xfrm2nvc0.vp | 63 ++
src/shader/xfrm2nvc0.vpc | 69 +++
src/shader/xfrm2nve0.vp | 63 ++
src/shader/xfrm2nve0.vpc | 70 +++
src/shader/xfrm2nvf0.vp | 82 +++
src/shader/xfrm2nvf0.vpc | 90 ++++
110 files changed, 6678 insertions(+), 2540 deletions(-)
New commits:
commit b71de83b7fae0abeb311251e6144294d319062cf
Author: Lyude <lyude@redhat.com>
Date: Tue Mar 7 18:44:43 2017 -0500
Bump version to 1.0.14
Signed-off-by: Lyude <lyude@redhat.com>
diff --git a/configure.ac b/configure.ac
index 0e004d7..e494300 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ([2.60])
AC_INIT([xf86-video-nouveau],
- [1.0.13],
+ [1.0.14],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-nouveau])
commit 924083938c8f209d8f6ff472caf8692a644f7e78
Author: Lyude <lyude@redhat.com>
Date: Fri Mar 3 18:27:42 2017 -0500
Consider CRTCs disabled when DPMS is off
It turns out there's a difference in X between a CRTC being "disabled"
and simply having it's DPMS turned off. This is problematic though,
because if DPMS is turned off you can't really use the CRTC as a normal
CRTC anyway since page flipping and vblanks will be non-functional. As a
result, we've been considering DPMS-on CRTCs as enabled and attempt to
perform pageflips, vblank waits, etc. on them which inevitably fails. and
usually breaks the display the first time any of the CRTCs have their
DPMS turned on.
This was a problem that didn't really show itself until kernel 4.10 when
atomic modesetting was added which caused nouveau to stop trying to
fulfill pageflips and vblank waits on disabled CRTCs. I'm not sure how
pageflipping disabled CRTCs ever worked in the first place, but since
not doing so is the proper behavior anyway I haven't investigated any
further.
So, copy the ms_crtc_on() function from the modesetting driver and add
it here as drmmode_crtc_on(), then use that in all of the places where
we should be checking for both DPMS off and disabled CRTCs.
This fixes issues with the X ceasing to function (usually) after the
first time a CRTC has it's DPMS turned on. Reproduction recipe:
- Load up gnome-shell on a machine
- Wait for the display to timeout from inactivity and turn itself off
- Shake the cursor or press something on the keyboard. Chances are the
monitor will come back on, but the display remains black until the
next time the X server is restarted.
Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index b6c9bb9..dd9fa27 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -65,6 +65,7 @@ typedef struct {
uint32_t rotate_fb_id;
Bool cursor_visible;
int scanout_pixmap_x;
+ int dpms_mode;
} drmmode_crtc_private_rec, *drmmode_crtc_private_ptr;
typedef struct {
@@ -114,6 +115,14 @@ drmmode_crtc(xf86CrtcPtr crtc)
return drmmode_crtc->mode_crtc->crtc_id;
}
+Bool
+drmmode_crtc_on(xf86CrtcPtr crtc)
+{
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+ return crtc->enabled && drmmode_crtc->dpms_mode == DPMSModeOn;
+}
+
int
drmmode_head(xf86CrtcPtr crtc)
{
@@ -313,9 +322,10 @@ drmmode_ConvertToKMode(ScrnInfoPtr scrn, drmModeModeInfo *kmode,
}
static void
-drmmode_crtc_dpms(xf86CrtcPtr drmmode_crtc, int mode)
+drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
-
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+ drmmode_crtc->dpms_mode = mode;
}
void
diff --git a/src/nouveau_dri2.c b/src/nouveau_dri2.c
index 81ee9be..cbb7b2a 100644
--- a/src/nouveau_dri2.c
+++ b/src/nouveau_dri2.c
@@ -279,23 +279,27 @@ can_exchange(DrawablePtr draw, PixmapPtr dst_pix, PixmapPtr src_pix)
ScrnInfoPtr scrn = xf86ScreenToScrn(draw->pScreen);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
NVPtr pNv = NVPTR(scrn);
- int i;
+ int i, active_crtc_count = 0;
if (!xf86_config->num_crtc)
return FALSE;
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
- if (crtc->enabled && crtc->rotatedData)
- return FALSE;
+ if (drmmode_crtc_on(crtc)) {
+ if (crtc->rotatedData)
+ return FALSE;
+ active_crtc_count++;
+ }
}
return ((DRI2CanFlip(draw) && pNv->has_pageflip)) &&
dst_pix->drawable.width == src_pix->drawable.width &&
dst_pix->drawable.height == src_pix->drawable.height &&
dst_pix->drawable.bitsPerPixel == src_pix->drawable.bitsPerPixel &&
- dst_pix->devKind == src_pix->devKind;
+ dst_pix->devKind == src_pix->devKind &&
+ active_crtc_count;
}
static Bool
@@ -475,7 +479,7 @@ dri2_page_flip(DrawablePtr draw, PixmapPtr back, void *priv,
int head = drmmode_crtc(config->crtc[i]);
void *token;
- if (!config->crtc[i]->enabled)
+ if (!drmmode_crtc_on(config->crtc[i]))
continue;
flipdata->flip_count++;
diff --git a/src/nouveau_present.c b/src/nouveau_present.c
index 482ac6e..ebd5fcf 100644
--- a/src/nouveau_present.c
+++ b/src/nouveau_present.c
@@ -152,7 +152,7 @@ nouveau_present_flip_check(RRCrtcPtr rrcrtc, WindowPtr window,
ScrnInfoPtr scrn = xf86ScreenToScrn(window->drawable.pScreen);
xf86CrtcPtr crtc = rrcrtc->devPrivate;
- if (!scrn->vtSema || !crtc->enabled)
+ if (!scrn->vtSema || !drmmode_crtc_on(crtc))
return FALSE;
return TRUE;
@@ -199,7 +199,7 @@ nouveau_present_flip_exec(ScrnInfoPtr scrn, uint64_t event_id, int sync,
flip->msc = target_msc;
for (i = 0; i < config->num_crtc; i++) {
- if (config->crtc[i]->enabled)
+ if (drmmode_crtc_on(config->crtc[i]))
last = i;
}
@@ -208,7 +208,7 @@ nouveau_present_flip_exec(ScrnInfoPtr scrn, uint64_t event_id, int sync,
int crtc = drmmode_crtc(config->crtc[i]);
void *user = NULL;
- if (!config->crtc[i]->enabled)
+ if (!drmmode_crtc_on(config->crtc[i]))
continue;
if (token && ((crtc == sync) || (i == last))) {
diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c
index 716b18d..4b939f7 100644
--- a/src/nouveau_xv.c
+++ b/src/nouveau_xv.c
@@ -299,7 +299,7 @@ nv_window_belongs_to_crtc(ScrnInfoPtr pScrn, int x, int y, int w, int h)
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
- if (!crtc->enabled)
+ if (!drmmode_crtc_on(crtc))
continue;
if ((x < (crtc->x + crtc->mode.HDisplay)) &&
diff --git a/src/nv_proto.h b/src/nv_proto.h
index 122ede5..4a57406 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -13,6 +13,7 @@ void drmmode_screen_init(ScreenPtr pScreen);
void drmmode_screen_fini(ScreenPtr pScreen);
int drmmode_crtc(xf86CrtcPtr crtc);
+Bool drmmode_crtc_on(xf86CrtcPtr crtc);
int drmmode_head(xf86CrtcPtr crtc);
void drmmode_swap(ScrnInfoPtr, uint32_t, uint32_t *);
commit 1516d35b06c9cda399bef01d992805d6e63dcbae
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Oct 16 15:10:10 2016 -0400
recognize and accelerate GM20x
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/nv_driver.c b/src/nv_driver.c
index fff83f8..61940a8 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct xf86_platform_device *platform_dev)
case 0xf0:
case 0x100:
case 0x110:
+ case 0x120:
break;
default:
xf86DrvMsg(-1, X_ERROR, "Unknown chipset: NV%02X\n", chipset);
@@ -941,6 +942,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
pNv->Architecture = NV_KEPLER;
break;
case 0x110:
+ case 0x120:
pNv->Architecture = NV_MAXWELL;
break;
default:
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index d0a835e..6c2bae8 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -244,9 +244,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
} else if (pNv->dev->chipset < 0x110) {
class = 0xa197;
handle = 0x0000906e;
- } else {
+ } else if (pNv->dev->chipset < 0x120) {
class = 0xb097;
handle = 0x0000906e;
+ } else if (pNv->dev->chipset < 0x130) {
+ class = 0xb197;
+ handle = 0x0000906e;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "No 3D acceleration support for NV%X\n",
+ pNv->dev->chipset);
+ return FALSE;
}
ret = nouveau_object_new(pNv->channel, class, class,
commit b00b73c3aa0da1d4cee5c9f580ca65a7bd344e0f
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Mon Oct 17 23:23:41 2016 -0400
copy: add maxwell/pascal copy engine classes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index c139de6..7118a7a 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);
} methods[] = {
+ { 0xc0b5, 0, nouveau_copya0b5_init },
+ { 0xb0b5, 0, nouveau_copya0b5_init },
{ 0xa0b5, 0, nouveau_copya0b5_init },
{ 0x90b8, 5, nouveau_copy90b5_init },
{ 0x90b5, 4, nouveau_copy90b5_init },
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 8da5051..d0a835e 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -156,9 +156,17 @@ NVAccelInitCOPY_NVE0(ScrnInfoPtr pScrn)
{
NVPtr pNv = NVPTR(pScrn);
struct nouveau_pushbuf *push = pNv->pushbuf;
+ uint32_t class;
int ret;
- ret = nouveau_object_new(pNv->channel, 0x0000a0b5, 0xa0b5,
+ if (pNv->dev->chipset < 0x110)
+ class = 0xa0b5;
+ else if (pNv->dev->chipset < 0x130)
+ class = 0xb0b5;
+ else
+ class = 0xc0b5;
+
+ ret = nouveau_object_new(pNv->channel, class, class,
NULL, 0, &pNv->NvCOPY);
if (ret)
return FALSE;
commit 5a3ada3b0ff3d89441faf35d331bb8b6cf5e51c0
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Oct 16 15:03:35 2016 -0400
nvc0: refactor TIC uploads to allow different specifics per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ PUSH_DATA (push, 0x88888888);
+ }
}
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 607e97b..959f67f 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -7,6 +7,7 @@
#include "hwdefs/nvc0_m2mf.xml.h"
#include "hwdefs/nv50_defs.xml.h"
#include "hwdefs/nv50_texture.h"
+#include "hwdefs/gm107_texture.xml.h"
#include "hwdefs/nv_3ddefs.xml.h"
/* subchannel assignments, compatible with kepler's fixed layout */
@@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo *bo,
}
}
+static __inline__ void
+PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset,
+ unsigned width, unsigned height, unsigned pitch, unsigned format)
+{
+ if (push->client->device->chipset < 0x110) {
+ unsigned tic2 = 0xd0001000;
+ if (pitch == 0)
+ tic2 |= 0x00004000;
+ else
+ tic2 |= 0x0005c000;
+ PUSH_DATA(push, format);
+ PUSH_DATA(push, bo->offset + offset);
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ (bo->config.nvc0.tile_mode << 18) |
+ tic2);
+ PUSH_DATA(push, 0x00300000);
+ PUSH_DATA(push, 0x80000000 | width);
+ PUSH_DATA(push, 0x00010000 | height);
+ PUSH_DATA(push, 0x03000000);
+ PUSH_DATA(push, 0x00000000);
+ } else {
+ unsigned tile_mode = bo->config.nvc0.tile_mode;
+ PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1));
+ PUSH_DATA(push, bo->offset + offset);
+ if (pitch == 0) {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ ((tile_mode & 0x007)) |
+ ((tile_mode & 0x070) >> (4 - 3)) |
+ ((tile_mode & 0x700) >> (8 - 6)));
+ PUSH_DATA(push, GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
+ GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
+ ((height - 1) & 0xffff));
+ PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
+ GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
+ PUSH_DATA(push, 0x00000000);
+ } else {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_PITCH);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
+ PUSH_DATA(push, 0x000000000);
+ PUSH_DATA(push, 0x000000000);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index d3fd316..b396079 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr pdpict, int op)
static Bool
NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
{
- uint64_t offset = pNv->scratch->offset + SOLID(unit);
struct nouveau_pushbuf *push = pNv->pushbuf;
PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
PUSH_DATA (push, ppict->pSourcePict->solidFill.color);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
- PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
- PUSH_DATA (push, offset);
- PUSH_DATA (push, (offset >> 32) | 0xd005d000);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, 0x00000001);
- PUSH_DATA (push, 0x00010001);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, pNv->scratch, SOLID(unit), 1, 1, 4,
+ _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT |
NV50TSC_1_0_WRAPT_REPEAT |
@@ -651,16 +644,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr ppict, unsigned unit)
PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
- PUSH_DATA (push, format);
- PUSH_DATA (push, bo->offset);
- PUSH_DATA (push, (bo->offset >> 32) |
- (bo->config.nvc0.tile_mode << 18) |
- 0xd0005000);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, (1 << 31) | ppix->drawable.width);
- PUSH_DATA (push, (1 << 16) | ppix->drawable.height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
+ format);
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
if (ppict->repeat) {
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 2d66fa8..5cecbf5 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y2;
BoxPtr pbox;
int nbox;
@@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
if (id == FOURCC_YV12 || id == FOURCC_I420) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, packed_y, width, height, 0,
+ NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8);
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,
+ NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
NV50TIC_0_0_FMT_8_8);
- PUSH_DATA (push, ((src->offset + uv)));
- PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width >> 1);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
} else {
- if (id == FOURCC_UYVY) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
+ unsigned format;
+ if (id == FOURCC_UYVY) {
+ format = NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8);
- } else {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8;
+ } else {
+ format = NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8);
- }
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, width);
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
- if (id == FOURCC_UYVY) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8;
+ }
+ PUSH_TIC(push, src, packed_y, width, height, 0, format);
+
+ if (id == FOURCC_UYVY) {
+ format = NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8_8_8);
- } else {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
+ NV50TIC_0_0_FMT_8_8_8_8;
+ } else {
+ format = NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
NV50TIC_0_0_MAPB_C1 | NV50TIC_0_0_TYPEB_UNORM |
NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
- NV50TIC_0_0_FMT_8_8_8_8);
- }
- PUSH_DATA (push, ((src->offset + packed_y)));
- PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
- PUSH_DATA (push, 0x00300000);
- PUSH_DATA (push, (width >> 1));
- PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
- PUSH_DATA (push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ NV50TIC_0_0_FMT_8_8_8_8;
+ }
+ PUSH_TIC(push, src, packed_y, width >> 1, height, 0, format);
}
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16);
commit 514441f32c5b948ce87668234ab9f01e8ec28dac
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Oct 16 12:42:18 2016 -0400
nvc0: rename BEGIN_IMC0 to IMMED_NVC0
For consistency with mesa. It wasn't used anywhere previously.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/nouveau_local.h b/src/nouveau_local.h
index 3de69a2..dd49395 100644
--- a/src/nouveau_local.h
+++ b/src/nouveau_local.h
@@ -237,7 +237,7 @@ BEGIN_NIC0(struct nouveau_pushbuf *push, int subc, int mthd, int size)
}
static inline void
-BEGIN_IMC0(struct nouveau_pushbuf *push, int subc, int mthd, int data)
+IMMED_NVC0(struct nouveau_pushbuf *push, int subc, int mthd, int data)
{
PUSH_DATA (push, 0x80000000 | (data << 16) | (subc << 13) | (mthd / 4));
}
commit 4459c04a6bc208924fac8082920f6786538bc5cd
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Oct 16 12:38:38 2016 -0400
nvc0: make use of the new hwdefs for TEX_CB_INDEX
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 52a17db..0682806 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0x00000001);
BEGIN_NVC0(push, NVC0_3D(CB_BIND(4)), 1);
PUSH_DATA (push, 0x11);
- BEGIN_NVC0(push, SUBC_3D(0x2608), 1);
+ BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
PUSH_DATA (push, 1);
}
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 4c3bb0f..607e97b 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -12,6 +12,7 @@
/* subchannel assignments, compatible with kepler's fixed layout */
#define SUBC_3D(mthd) 0, (mthd)
#define NVC0_3D(mthd) SUBC_3D(NVC0_3D_##mthd)
+#define NVE4_3D(mthd) SUBC_3D(NVE4_3D_##mthd)
#define SUBC_M2MF(mthd) 2, (mthd)
#define SUBC_P2MF(mthd) 2, (mthd)
#define NVC0_M2MF(mthd) SUBC_M2MF(NVC0_M2MF_##mthd)
commit ea6fd12ea059c6af832bd2180b26d75e00d4ea71
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Oct 16 12:38:02 2016 -0400
hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
diff --git a/src/Makefile.am b/src/Makefile.am
index 6ba8d87..d777fe5 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -71,6 +71,7 @@ EXTRA_DIST = hwdefs/nv_3ddefs.xml.h \
hwdefs/nv50_texture.h \
hwdefs/nvc0_3d.xml.h \
hwdefs/nvc0_m2mf.xml.h \
+ hwdefs/gm107_texture.xml.h \
shader/exac8nvc0.fp \
shader/exac8nvc0.fpc \
shader/exac8nve0.fp \
diff --git a/src/hwdefs/gm107_texture.xml.h b/src/hwdefs/gm107_texture.xml.h
new file mode 100644
index 0000000..a4bc380
--- /dev/null
+++ b/src/hwdefs/gm107_texture.xml.h
@@ -0,0 +1,365 @@
+#ifndef GM107_TEXTURE_XML
+#define GM107_TEXTURE_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/envytools/envytools/
+git clone https://github.com/envytools/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/skeggsb/git/envytools/rnndb/../rnndb/graph/gm107_texture.xml ( 22057 bytes, from 2016-02-12 03:01:43)
+- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6456 bytes, from 2015-09-10 02:57:40)
+- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 2908 bytes, from 2016-02-04 22:19:11)
+- /home/skeggsb/git/envytools/rnndb/g80_defs.xml ( 21739 bytes, from 2016-02-04 00:29:42)
+
+Copyright (C) 2006-2016 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define GM107_TIC2__SIZE 0x00000020
+#define GM107_TIC2_0 0x00000000
+#define GM107_TIC2_0_COMPONENTS_SIZES__MASK 0x0000007f
+#define GM107_TIC2_0_COMPONENTS_SIZES__SHIFT 0
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32 0x00000002
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32 0x00000004
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_B24G8 0x00000005
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8B8G8R8 0x00000007
+#define GM107_TIC2_0_COMPONENTS_SIZES_A8B8G8R8 0x00000008
+#define GM107_TIC2_0_COMPONENTS_SIZES_A2B10G10R10 0x00000009
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16 0x0000000c
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8R24 0x0000000d
+#define GM107_TIC2_0_COMPONENTS_SIZES_G24R8 0x0000000e
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32 0x0000000f
+#define GM107_TIC2_0_COMPONENTS_SIZES_A4B4G4R4 0x00000012
+#define GM107_TIC2_0_COMPONENTS_SIZES_A5B5G5R1 0x00000013
+#define GM107_TIC2_0_COMPONENTS_SIZES_A1B5G5R5 0x00000014
+#define GM107_TIC2_0_COMPONENTS_SIZES_B5G6R5 0x00000015
+#define GM107_TIC2_0_COMPONENTS_SIZES_B6G5R5 0x00000016
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8R8 0x00000018
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16 0x0000001b
+#define GM107_TIC2_0_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c
+#define GM107_TIC2_0_COMPONENTS_SIZES_R8 0x0000001d
+#define GM107_TIC2_0_COMPONENTS_SIZES_G4R4 0x0000001e
+#define GM107_TIC2_0_COMPONENTS_SIZES_R1 0x0000001f
+#define GM107_TIC2_0_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020
+#define GM107_TIC2_0_COMPONENTS_SIZES_BF10GF11RF11 0x00000021
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8B8G8R8 0x00000022
+#define GM107_TIC2_0_COMPONENTS_SIZES_B8G8R8G8 0x00000023
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXT1 0x00000024
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXT23 0x00000025
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXT45 0x00000026
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXN1 0x00000027
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXN2 0x00000028
+#define GM107_TIC2_0_COMPONENTS_SIZES_BC6H_SF16 0x00000010
+#define GM107_TIC2_0_COMPONENTS_SIZES_BC6H_UF16 0x00000011
+#define GM107_TIC2_0_COMPONENTS_SIZES_BC7U 0x00000017
+#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGB 0x00000006
+#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a
+#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b
+#define GM107_TIC2_0_COMPONENTS_SIZES_EAC 0x00000019
+#define GM107_TIC2_0_COMPONENTS_SIZES_EACX2 0x0000001a
+#define GM107_TIC2_0_COMPONENTS_SIZES_Z24S8 0x00000029
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24 0x0000002a
+#define GM107_TIC2_0_COMPONENTS_SIZES_S8Z24 0x0000002b
+#define GM107_TIC2_0_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c
+#define GM107_TIC2_0_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d
+#define GM107_TIC2_0_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32 0x0000002f
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X24S8 0x00000030
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039
+#define GM107_TIC2_0_COMPONENTS_SIZES_Z16 0x0000003a
+#define GM107_TIC2_0_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046
+#define GM107_TIC2_0_R_DATA_TYPE__MASK 0x00000380
+#define GM107_TIC2_0_R_DATA_TYPE__SHIFT 7
+#define GM107_TIC2_0_G_DATA_TYPE__MASK 0x00001c00
+#define GM107_TIC2_0_G_DATA_TYPE__SHIFT 10
+#define GM107_TIC2_0_B_DATA_TYPE__MASK 0x0000e000
+#define GM107_TIC2_0_B_DATA_TYPE__SHIFT 13
+#define GM107_TIC2_0_A_DATA_TYPE__MASK 0x00070000
+#define GM107_TIC2_0_A_DATA_TYPE__SHIFT 16
+#define GM107_TIC2_0_X_SOURCE__MASK 0x00380000
+#define GM107_TIC2_0_X_SOURCE__SHIFT 19
+#define GM107_TIC2_0_Y_SOURCE__MASK 0x01c00000
+#define GM107_TIC2_0_Y_SOURCE__SHIFT 22
+#define GM107_TIC2_0_Z_SOURCE__MASK 0x0e000000
+#define GM107_TIC2_0_Z_SOURCE__SHIFT 25
+#define GM107_TIC2_0_W_SOURCE__MASK 0x70000000
+#define GM107_TIC2_0_W_SOURCE__SHIFT 28
+#define GM107_TIC2_0_PACK_COMPONENTS 0x80000000
+
+#define GM107_TIC2_1 0x00000004
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_0__MASK 0xffffffff
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_0__SHIFT 0
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__MASK 0xffffffe0
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__SHIFT 5
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__SHR 5
+#define GM107_TIC2_1_GOB_DEPTH_OFFSET__MASK 0x00000060
+#define GM107_TIC2_1_GOB_DEPTH_OFFSET__SHIFT 5
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__MASK 0xfffffe00
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__SHIFT 9
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__SHR 9
+
+#define GM107_TIC2_2 0x00000008
+#define GM107_TIC2_2_ADDRESS_BITS_47_TO_32__MASK 0x0000ffff
+#define GM107_TIC2_2_ADDRESS_BITS_47_TO_32__SHIFT 0
+#define GM107_TIC2_2_HEADER_VERSION__MASK 0x00e00000
+#define GM107_TIC2_2_HEADER_VERSION__SHIFT 21
+#define GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER 0x00000000
+#define GM107_TIC2_2_HEADER_VERSION_PITCH_COLORKEY 0x00200000
+#define GM107_TIC2_2_HEADER_VERSION_PITCH 0x00400000
+#define GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR 0x00600000
+#define GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR_COLORKEY 0x00800000
+#define GM107_TIC2_2_RESOURCE_VIEW_COHERENCY_HASH__MASK 0x1e000000
+#define GM107_TIC2_2_RESOURCE_VIEW_COHERENCY_HASH__SHIFT 25
+
+#define GM107_TIC2_3 0x0000000c
+#define GM107_TIC2_3_WIDTH_MINUS_ONE_BITS_31_TO_16__MASK 0x0000ffff
+#define GM107_TIC2_3_WIDTH_MINUS_ONE_BITS_31_TO_16__SHIFT 0
+#define GM107_TIC2_3_PITCH_BITS_20_TO_5__MASK 0x0000ffff
+#define GM107_TIC2_3_PITCH_BITS_20_TO_5__SHIFT 0
+#define GM107_TIC2_3_PITCH_BITS_20_TO_5__SHR 5
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MASK 0x00000007
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__SHIFT 0
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MIN 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MAX 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_ONE 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_TWO 0x00000001
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_FOUR 0x00000002
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_EIGHT 0x00000003
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_SIXTEEN 0x00000004
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_THIRTYTWO 0x00000005
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT__MASK 0x00000038
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT__SHIFT 3
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_ONE 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_TWO 0x00000008
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_FOUR 0x00000010
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_EIGHT 0x00000018
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_SIXTEEN 0x00000020
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO 0x00000028
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH__MASK 0x000001c0
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH__SHIFT 6
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_ONE 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_TWO 0x00000040
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_FOUR 0x00000080
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_EIGHT 0x000000c0
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_SIXTEEN 0x00000100
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_THIRTYTWO 0x00000140
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS__MASK 0x00001c00
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS__SHIFT 10
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_ONE 0x00000000
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_TWO 0x00000400
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_FOUR 0x00000800
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_EIGHT 0x00000c00
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_SIXTEEN 0x00001000
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_THIRTYTWO 0x00001400
+#define GM107_TIC2_3_GOB_3D 0x00002000
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