mesa: Changes to 'upstream-experimental'
Android.common.mk | 14 +++++
VERSION | 2
configure.ac | 49 ++++++++++++-------
src/amd/Android.common.mk | 2
src/amd/common/ac_nir_to_llvm.c | 46 +++++++++++++----
src/amd/vulkan/Makefile.am | 4 -
src/amd/vulkan/radv_cmd_buffer.c | 4 +
src/compiler/glsl/link_uniforms.cpp | 2
src/compiler/spirv/spirv_to_nir.c | 54 +++++++++++++++------
src/compiler/spirv/vtn_variables.c | 6 ++
src/egl/Makefile.am | 2
src/gallium/Android.common.mk | 2
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 1
src/gallium/auxiliary/tgsi/tgsi_exec.c | 14 +++++
src/gallium/drivers/etnaviv/etnaviv_compiler.c | 39 ++++++++++++++-
src/gallium/drivers/etnaviv/etnaviv_emit.c | 17 ++++++
src/gallium/drivers/etnaviv/etnaviv_internal.h | 19 +++++++
src/gallium/drivers/etnaviv/etnaviv_resource.c | 5 +
src/gallium/drivers/etnaviv/etnaviv_screen.c | 9 ++-
src/gallium/drivers/etnaviv/etnaviv_state.c | 38 +++++++-------
src/gallium/drivers/freedreno/Makefile.am | 1
src/gallium/drivers/r600/r600_shader.c | 2
src/gallium/drivers/radeonsi/si_descriptors.c | 11 ++--
src/gallium/drivers/radeonsi/si_state.c | 6 +-
src/gallium/state_trackers/clover/Makefile.am | 2
src/gallium/state_trackers/dri/Makefile.am | 2
src/gallium/state_trackers/va/picture.c | 11 +++-
src/gallium/state_trackers/va/va_private.h | 1
src/gallium/state_trackers/vdpau/output.c | 7 ++
src/gallium/state_trackers/vdpau/presentation.c | 6 +-
src/gallium/state_trackers/vdpau/vdpau_private.h | 1
src/gallium/targets/d3dadapter9/Makefile.am | 2
src/glx/Makefile.am | 4 -
src/glx/apple/Makefile.am | 4 -
src/glx/windows/Makefile.am | 2
src/intel/blorp/blorp_clear.c | 23 ++++++++
src/intel/isl/isl_format.c | 5 +
src/intel/vulkan/anv_cmd_buffer.c | 5 +
src/intel/vulkan/anv_descriptor_set.c | 8 +--
src/intel/vulkan/anv_nir_lower_input_attachments.c | 5 -
src/intel/vulkan/genX_cmd_buffer.c | 19 +++----
src/loader/Makefile.am | 2
src/mapi/Makefile.am | 4 -
src/mesa/drivers/dri/i915/Makefile.am | 2
src/mesa/drivers/dri/i965/Makefile.am | 7 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 2
src/mesa/drivers/dri/i965/brw_context.c | 3 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2
src/mesa/drivers/dri/i965/brw_program.c | 43 ++++++++++++++++
src/mesa/drivers/dri/i965/gen8_depth_state.c | 12 ++++
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 4 +
src/mesa/drivers/dri/i965/intel_blit.c | 24 +++------
src/mesa/drivers/dri/i965/intel_blit.h | 4 -
src/mesa/drivers/dri/i965/intel_screen.c | 1
src/mesa/drivers/dri/r200/Makefile.am | 2
src/mesa/drivers/dri/radeon/Makefile.am | 2
src/mesa/drivers/dri/swrast/Makefile.am | 2
src/mesa/drivers/osmesa/Makefile.am | 2
src/mesa/main/extensions_table.h | 2
src/mesa/main/shaderapi.c | 4 -
src/mesa/main/tests/Makefile.am | 2
src/mesa/state_tracker/st_context.c | 13 ++---
src/vulkan/wsi/wsi_common_wayland.c | 27 ++++++----
src/vulkan/wsi/wsi_common_x11.c | 3 -
64 files changed, 450 insertions(+), 175 deletions(-)
New commits:
commit 07571cd8ccf8c19fe79e16055208059fe729d298
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Feb 6 13:18:13 2017 +0000
Update version to 17.0.0-rc3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 032c50c..0b34163 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.0.0-rc2
+17.0.0-rc3
commit 2fc362f14711981e98c920f2f278ad91bad89982
Author: Lucas Stach <l.stach@pengutronix.de>
Date: Mon Nov 21 11:54:25 2016 +0100
etnaviv: force vertex buffers through the MMU
This fixes a vertex data corruption issue if some of the vertex streams
go through the MMU and some don't.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit e158b7497103f145a9236a70183e07c37a9e13f7)
Nominated-by: Christian Gmeiner <christian.gmeiner@gmail.com>
diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c
index aefe65b..94a8a73 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -201,7 +201,10 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale);
- struct etna_bo *bo = etna_bo_new(screen->dev, size, DRM_ETNA_GEM_CACHE_WC);
+ uint32_t flags = DRM_ETNA_GEM_CACHE_WC;
+ if (templat->bind & PIPE_BIND_VERTEX_BUFFER)
+ flags |= DRM_ETNA_GEM_FORCE_MMU;
+ struct etna_bo *bo = etna_bo_new(screen->dev, size, flags);
if (unlikely(bo == NULL)) {
BUG("Problem allocating video memory for resource");
return NULL;
commit 89b51c7e432268d8f5b5b4ae1870332ac4a3f202
Author: Christian König <christian.koenig@amd.com>
Date: Thu Jan 19 13:44:34 2017 +0100
st/va: make sure that we call begin_frame() only once v2
This fixes "st/va: delay calling begin_frame until we have all parameters".
v2: call begin frame after decoder (re)creation as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
(cherry picked from commit 1338d912f52b69f76ef75d1ad313893db77d4da8)
diff --git a/src/gallium/state_trackers/va/picture.c b/src/gallium/state_trackers/va/picture.c
index dc7121c..82584ea 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -81,7 +81,7 @@ vlVaBeginPicture(VADriverContextP ctx, VAContextID context_id, VASurfaceID rende
}
if (context->decoder->entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE)
- context->decoder->begin_frame(context->decoder, context->target, &context->desc.base);
+ context->needs_begin_frame = true;
return VA_STATUS_SUCCESS;
}
@@ -178,6 +178,8 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext *context, vlVaBuffer *
if (!context->decoder)
return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+ context->needs_begin_frame = true;
}
return vaStatus;
@@ -308,8 +310,11 @@ handleVASliceDataBufferType(vlVaContext *context, vlVaBuffer *buf)
sizes[num_buffers] = buf->size;
++num_buffers;
- context->decoder->begin_frame(context->decoder, context->target,
- &context->desc.base);
+ if (context->needs_begin_frame) {
+ context->decoder->begin_frame(context->decoder, context->target,
+ &context->desc.base);
+ context->needs_begin_frame = false;
+ }
context->decoder->decode_bitstream(context->decoder, context->target, &context->desc.base,
num_buffers, (const void * const*)buffers, sizes);
}
diff --git a/src/gallium/state_trackers/va/va_private.h b/src/gallium/state_trackers/va/va_private.h
index 8faec10..0877236 100644
--- a/src/gallium/state_trackers/va/va_private.h
+++ b/src/gallium/state_trackers/va/va_private.h
@@ -261,6 +261,7 @@ typedef struct {
int target_id;
bool first_single_submitted;
int gop_coeff;
+ bool needs_begin_frame;
} vlVaContext;
typedef struct {
commit ac2337ee3836e9817c24c44cae520dedfa1ebeb2
Author: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Date: Thu Jan 19 14:59:28 2017 +0530
st/vdpau: only send buffers with B8G8R8A8 format to X
PresentPixmap only works if the pixmap depth matches with the
window depth, otherwise it returns a BadMatch protocol error.
Even if the depths match, the result won't look correctly
if the VDPAU RGB component order doesn't match the X11 one so
we only allow the X11 format.
For other buffers we copy them to a buffer which is send to X.
v2: only send buffers with format VDP_RGBA_FORMAT_B8G8R8A8
v3: reword commit message
v4: add comment explaining the code
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 31908d6a4a3309f4cd4b953d6eecdf41595b1299)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99637
Nominated-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Nominated-by: Michel Dänzer <michel.daenzer@amd.com> (IRC)
diff --git a/src/gallium/state_trackers/vdpau/output.c b/src/gallium/state_trackers/vdpau/output.c
index 98a8011..8b26f7a 100644
--- a/src/gallium/state_trackers/vdpau/output.c
+++ b/src/gallium/state_trackers/vdpau/output.c
@@ -75,6 +75,13 @@ vlVdpOutputSurfaceCreate(VdpDevice device,
memset(&res_tmpl, 0, sizeof(res_tmpl));
+ /*
+ * The output won't look correctly when this buffer is send to X,
+ * if the VDPAU RGB component order doesn't match the X11 one so
+ * we only allow the X11 format
+ */
+ vlsurface->send_to_X = rgba_format == VDP_RGBA_FORMAT_B8G8R8A8;
+
res_tmpl.target = PIPE_TEXTURE_2D;
res_tmpl.format = VdpFormatRGBAToPipe(rgba_format);
res_tmpl.width0 = width;
diff --git a/src/gallium/state_trackers/vdpau/presentation.c b/src/gallium/state_trackers/vdpau/presentation.c
index d479369..78cafc8 100644
--- a/src/gallium/state_trackers/vdpau/presentation.c
+++ b/src/gallium/state_trackers/vdpau/presentation.c
@@ -231,7 +231,7 @@ vlVdpPresentationQueueDisplay(VdpPresentationQueue presentation_queue,
vscreen = pq->device->vscreen;
pipe_mutex_lock(pq->device->mutex);
- if (vscreen->set_back_texture_from_output)
+ if (vscreen->set_back_texture_from_output && surf->send_to_X)
vscreen->set_back_texture_from_output(vscreen, surf->surface->texture, clip_width, clip_height);
tex = vscreen->texture_from_drawable(vscreen, (void *)pq->drawable);
if (!tex) {
@@ -239,7 +239,7 @@ vlVdpPresentationQueueDisplay(VdpPresentationQueue presentation_queue,
return VDP_STATUS_INVALID_HANDLE;
}
- if (!vscreen->set_back_texture_from_output) {
+ if (!vscreen->set_back_texture_from_output || !surf->send_to_X) {
dirty_area = vscreen->get_dirty_area(vscreen);
memset(&surf_templ, 0, sizeof(surf_templ));
@@ -289,7 +289,7 @@ vlVdpPresentationQueueDisplay(VdpPresentationQueue presentation_queue,
framenum++;
}
- if (!vscreen->set_back_texture_from_output) {
+ if (!vscreen->set_back_texture_from_output || !surf->send_to_X) {
pipe_resource_reference(&tex, NULL);
pipe_surface_reference(&surf_draw, NULL);
}
diff --git a/src/gallium/state_trackers/vdpau/vdpau_private.h b/src/gallium/state_trackers/vdpau/vdpau_private.h
index 490a0bd..8356608 100644
--- a/src/gallium/state_trackers/vdpau/vdpau_private.h
+++ b/src/gallium/state_trackers/vdpau/vdpau_private.h
@@ -415,6 +415,7 @@ typedef struct
struct pipe_fence_handle *fence;
struct vl_compositor_state cstate;
struct u_rect dirty_area;
+ bool send_to_X;
} vlVdpOutputSurface;
typedef struct
commit 77ec080710aa7f38c02f0d4a62f0a8780cfcc61e
Author: Mauro Rossi <issor.oruam@gmail.com>
Date: Mon Jan 30 20:57:30 2017 +0100
android: fix llvm, elf dependencies for M, N releases
These changes set the correct llvm version and elf include path
which differ for Marshmallow and Nougat
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 9c45bb731c97d1f02f83b872c67b2c1b04ec3a41)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
Android.common.mk
diff --git a/Android.common.mk b/Android.common.mk
index a75d4e7..f53750c 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -78,10 +78,22 @@ endif
ifeq ($(MESA_ENABLE_LLVM),true)
LOCAL_CFLAGS += \
- -DHAVE_LLVM=0x0305 -DMESA_LLVM_VERSION_PATCH=2 \
-D__STDC_CONSTANT_MACROS \
-D__STDC_FORMAT_MACROS \
-D__STDC_LIMIT_MACROS
+
+ ifeq ($(MESA_ANDROID_MAJOR_VERSION),5)
+ LOCAL_CFLAGS += -DHAVE_LLVM=0x0305 -DMESA_LLVM_VERSION_PATCH=2
+ ELF_INCLUDES := external/elfutils/0.153/libelf
+ endif
+ ifeq ($(MESA_ANDROID_MAJOR_VERSION),6)
+ LOCAL_CFLAGS += -DHAVE_LLVM=0x0307 -DMESA_LLVM_VERSION_PATCH=0
+ ELF_INCLUDES := external/elfutils/src/libelf
+ endif
+ ifeq ($(MESA_ANDROID_MAJOR_VERSION),7)
+ LOCAL_CFLAGS += -DHAVE_LLVM=0x0308 -DMESA_LLVM_VERSION_PATCH=0
+ ELF_INCLUDES := external/elfutils/libelf
+ endif
endif
ifneq ($(LOCAL_IS_HOST_MODULE),true)
diff --git a/src/amd/Android.common.mk b/src/amd/Android.common.mk
index dfa7e59..faace71 100644
--- a/src/amd/Android.common.mk
+++ b/src/amd/Android.common.mk
@@ -55,7 +55,7 @@ LOCAL_C_INCLUDES := \
external/llvm/include \
external/llvm/device/include \
external/libcxx/include \
- external/elfutils/$(if $(filter 5,$(MESA_ANDROID_MAJOR_VERSION)),0.153/,$(if $(filter 6,$(MESA_ANDROID_MAJOR_VERSION)),src/))libelf
+ $(ELF_INCLUDES)
LOCAL_STATIC_LIBRARIES := libLLVMCore
diff --git a/src/gallium/Android.common.mk b/src/gallium/Android.common.mk
index 7c6c7ac..8559b5b 100644
--- a/src/gallium/Android.common.mk
+++ b/src/gallium/Android.common.mk
@@ -34,7 +34,7 @@ LOCAL_C_INCLUDES += \
external/llvm/include \
external/llvm/device/include \
external/libcxx/include \
- external/elfutils/$(if $(filter true,$(MESA_LOLLIPOP_BUILD)),0.153/)libelf
+ $(ELF_INCLUDES)
endif
include $(MESA_COMMON_MK)
commit eadbc95d642cac6feb7f5e5abe136dfd36ff76ac
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Jan 30 19:53:17 2017 -0800
anv: Improve flushing around STATE_BASE_ADDRESS
It is not clear from the docs exactly how pipelined STATE_BASE_ADDRESS
actually is. We know from experimentation that we need to flush the
render cache prior to emitting STATE_BASE_ADDRESS and invalidate the
texture cache afterwards. The only thing the PRM says is that, on gen8+
we're supposed to invalidate the state cache after STATE_BASE_ADDRESS
but experimentation has indicated that doing so does nothing whatsoever.
Since we don't really know, let's do just a bit more flushing in the
hopes that this won't be a problem again. In particular:
1) Do a CS stall before we emit STATE_BASE_ADDRESS since we don't
really know whether or not it's pipelined.
2) Do a data cache flush in case what runs before STATE_BASE_ADDRESS
is a compute shader.
3) Invalidate the state and constant caches after STATE_BASE_ADDRESS
because the state may be getting cached there (we don't really know).
Reported-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 92128590bc78bcbbfb19144c7004b31d6405bbcb)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index d0e76e3d..0ad7cd5 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -63,7 +63,9 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
* clear depth, reset state base address, and then go render stuff.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+ pc.DCFlushEnable = true;
pc.RenderTargetCacheFlushEnable = true;
+ pc.CommandStreamerStallEnable = true;
}
anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
@@ -145,6 +147,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.TextureCacheInvalidationEnable = true;
+ pc.ConstantCacheInvalidationEnable = true;
+ pc.StateCacheInvalidationEnable = true;
}
}
commit 69ec90ad24a16087eac29fc076f0dff636fba62d
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Tue Jan 31 15:06:56 2017 -0800
anv: Flush render cache before STATE_BASE_ADDRESS on gen7
We had no good reason for *not* doing this on gen7 before but we didn't
know it was needed. Recently, when trying update to Vulkan CTS version
1.0.2 in our CI system, Mark discovered GPU hangs on Haswell that appear
to be STATE_BASE_ADDRESS related. This commit fixes them.
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f1f9794118008bcdc13d93ee709022d21cc4156d)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index d93d377..d0e76e3d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -55,8 +55,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
-/* XXX: Do we need this on more than just BDW? */
-#if (GEN_GEN >= 8)
/* Emit a render target cache flush.
*
* This isn't documented anywhere in the PRM. However, it seems to be
@@ -67,7 +65,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.RenderTargetCacheFlushEnable = true;
}
-#endif
anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
commit 7abecef5c3c27253af32083134aa964f114b96c1
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri Jan 27 12:31:40 2017 -0800
isl/formats: Only advertise sampling for A4B4G4R4 on Broadwell
This causes hangs on Broadwell if you try to render to it. I have no
idea how we managed to not hit this earlier.
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 4871930451215fd8673f7e213a88aa48e5ecaad3)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index c8daece..bc157d5 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -218,9 +218,10 @@ static const struct surface_format_info format_info[] = {
SF(50, 50, x, x, x, x, x, x, x, x, P8A8_UNORM_PALETTE1)
SF( x, x, x, x, x, x, x, x, x, x, A1B5G5R5_UNORM)
/* According to the PRM, A4B4G4R4_UNORM isn't supported until Sky Lake
- * but empirical testing indicates that it works just fine on Broadwell.
+ * but empirical testing indicates that at least sampling works just fine
+ * on Broadwell.
*/
- SF(80, 80, x, x, 80, x, x, x, x, x, A4B4G4R4_UNORM)
+ SF(80, 80, x, x, 90, x, x, x, x, x, A4B4G4R4_UNORM)
SF(90, x, x, x, x, x, x, x, x, x, L8A8_UINT)
SF(90, x, x, x, x, x, x, x, x, x, L8A8_SINT)
SF( Y, Y, x, 45, Y, Y, Y, x, x, x, R8_UNORM)
commit 5d470a68e67281e12ac6b82e593476fb50fb1b29
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri Jan 27 12:32:05 2017 -0800
intel/blorp: Handle clearing of A4B4G4R4 on all platforms
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a0348b5a0b679a78b3f49d41f980dec6066cc541)
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index afc505d..8ea22ac 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -349,6 +349,29 @@ blorp_clear(struct blorp_batch *batch,
if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) {
clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32);
format = ISL_FORMAT_R32_UINT;
+ } else if (format == ISL_FORMAT_A4B4G4R4_UNORM) {
+ /* Broadwell and earlier cannot render to this format so we need to work
+ * around it by swapping the colors around and using B4G4R4A4 instead.
+ */
+
+ /* First, we apply the swizzle. */
+ union isl_color_value old;
+ assert((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4);
+ assert((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4);
+ assert((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4);
+ assert((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4);
+ old.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = clear_color.u32[0];
+ old.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = clear_color.u32[1];
+ old.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = clear_color.u32[2];
+ old.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = clear_color.u32[3];
+ swizzle = ISL_SWIZZLE_IDENTITY;
+
+ /* Now we re-order for the new format */
+ clear_color.u32[0] = old.u32[1];
+ clear_color.u32[1] = old.u32[2];
+ clear_color.u32[2] = old.u32[3];
+ clear_color.u32[3] = old.u32[0];
+ format = ISL_FORMAT_B4G4R4A4_UNORM;
}
memcpy(¶ms.wm_inputs.clear_color, clear_color.f32, sizeof(float) * 4);
commit 3df060d9530b5f0cbfe9894dff12cb1c61b831b1
Author: Wladimir J. van der Laan <laanwj@gmail.com>
Date: Fri Nov 25 06:42:43 2016 +0000
etnaviv: Set SE.CLIP registers, add margins for scissor/clip registers
This fixes rendering of full-screen quads (and other screen-filling
geometry, e.g. ioquake3 walls up-close) on gc3000. It should be a no-op
on other hardware.
- It looks like SE_CLIP registers were not set at all.
I'm amazed that rendering worked without them. Emit them to
avoid issues on gc3000.
- Define constants
ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
These demarcate the margin (fixp16) between the computed sizes and the
value sent to the chip. I have set these to the numbers used by the
Vivante driver for gc2000. I am not sure whether any old hardware was
relying on the old numbers, or whether those were just a guess. But if
so, these need to be moved to the _specs structure.
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit 56314f5bafdfeb514adf8401c52f216bd430bbb2)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c
index 7eeeda5..8394474 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
@@ -491,6 +491,23 @@ etna_emit_state(struct etna_context *ctx)
/*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS);
/*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG);
}
+ if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
+ ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) {
+ struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
+
+ uint32_t clip_right =
+ MIN2(ctx->framebuffer.SE_CLIP_RIGHT, ctx->viewport.SE_CLIP_RIGHT);
+ uint32_t clip_bottom =
+ MIN2(ctx->framebuffer.SE_CLIP_BOTTOM, ctx->viewport.SE_CLIP_BOTTOM);
+
+ if (rasterizer->scissor) {
+ clip_right = MIN2(ctx->scissor.SE_CLIP_RIGHT, clip_right);
+ clip_bottom = MIN2(ctx->scissor.SE_CLIP_BOTTOM, clip_bottom);
+ }
+
+ /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, clip_right);
+ /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, clip_bottom);
+ }
if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
/*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
}
diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h
index 983321a..2f09d55 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_internal.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h
@@ -47,6 +47,17 @@
/* PE render targets must be aligned to 64 bytes */
#define ETNA_PE_ALIGNMENT (64)
+/* These demarcate the margin (fixp16) between the computed sizes and the
+ value sent to the chip. These have been set to the numbers used by the
+ Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
+ am not sure whether older hardware was relying on these or they were just a
+ guess. But if so, these need to be moved to the _specs structure.
+*/
+#define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
+#define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
+#define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
+#define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
+
/* GPU chip 3D specs */
struct etna_specs {
/* supports SUPERTILE (64x64) tiling? */
@@ -128,6 +139,8 @@ struct compiled_scissor_state {
uint32_t SE_SCISSOR_TOP;
uint32_t SE_SCISSOR_RIGHT;
uint32_t SE_SCISSOR_BOTTOM;
+ uint32_t SE_CLIP_RIGHT;
+ uint32_t SE_CLIP_BOTTOM;
};
/* Compiled pipe_viewport_state */
@@ -142,6 +155,8 @@ struct compiled_viewport_state {
uint32_t SE_SCISSOR_TOP;
uint32_t SE_SCISSOR_RIGHT;
uint32_t SE_SCISSOR_BOTTOM;
+ uint32_t SE_CLIP_RIGHT;
+ uint32_t SE_CLIP_BOTTOM;
uint32_t PE_DEPTH_NEAR;
uint32_t PE_DEPTH_FAR;
};
@@ -164,6 +179,8 @@ struct compiled_framebuffer_state {
uint32_t SE_SCISSOR_TOP;
uint32_t SE_SCISSOR_RIGHT;
uint32_t SE_SCISSOR_BOTTOM;
+ uint32_t SE_CLIP_RIGHT;
+ uint32_t SE_CLIP_BOTTOM;
uint32_t RA_MULTISAMPLE_UNK00E04;
uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c
index 2256261..141a34a 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -323,8 +323,10 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
/* Scissor setup */
cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
cs->SE_SCISSOR_TOP = 0;
- cs->SE_SCISSOR_RIGHT = (sv->width << 16) - 1;
- cs->SE_SCISSOR_BOTTOM = (sv->height << 16) - 1;
+ cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
cs->TS_MEM_CONFIG = ts_mem_config;
@@ -345,13 +347,17 @@ etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
{
struct etna_context *ctx = etna_context(pctx);
struct compiled_scissor_state *cs = &ctx->scissor;
+ assert(ss->minx <= ss->maxx);
+ assert(ss->miny <= ss->maxy);
/* note that this state is only used when rasterizer_state->scissor is on */
ctx->scissor_s = *ss;
cs->SE_SCISSOR_LEFT = (ss->minx << 16);
cs->SE_SCISSOR_TOP = (ss->miny << 16);
- cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) - 1;
- cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) - 1;
+ cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
ctx->dirty |= ETNA_DIRTY_SCISSOR;
}
@@ -387,22 +393,14 @@ etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
/* Compute scissor rectangle (fixp) from viewport.
* Make sure left is always < right and top always < bottom.
*/
- cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - vs->scale[0], 0.0f));
- cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - vs->scale[1], 0.0f));
- cs->SE_SCISSOR_RIGHT = etna_f32_to_fixp16(MAX2(vs->translate[0] + vs->scale[0], 0.0f));
- cs->SE_SCISSOR_BOTTOM = etna_f32_to_fixp16(MAX2(vs->translate[1] + vs->scale[1], 0.0f));
-
- if (cs->SE_SCISSOR_LEFT > cs->SE_SCISSOR_RIGHT) {
- uint32_t tmp = cs->SE_SCISSOR_RIGHT;
- cs->SE_SCISSOR_RIGHT = cs->SE_SCISSOR_LEFT;
- cs->SE_SCISSOR_LEFT = tmp;
- }
-
- if (cs->SE_SCISSOR_TOP > cs->SE_SCISSOR_BOTTOM) {
- uint32_t tmp = cs->SE_SCISSOR_BOTTOM;
- cs->SE_SCISSOR_BOTTOM = cs->SE_SCISSOR_TOP;
- cs->SE_SCISSOR_TOP = tmp;
- }
+ cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
+ cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
+ uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
+ uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
+ cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
cs->PE_DEPTH_FAR = fui(1.0);
commit 34cd53ca8c2652b095e090f52bbe66ffbfeced5d
Author: Wladimir J. van der Laan <laanwj@gmail.com>
Date: Tue Jan 31 09:23:51 2017 +0100
etnaviv: Generate new sin/cos instructions on GC3000
Shaders using sin/cos instructions were not working on GC3000.
The reason for this turns out to be that these chips implement sin/cos
in a different way (but using the same opcodes):
- Need their input scaled by 1/pi instead of 2/pi.
- Output an x and y component, which need to be multiplied to
get the result.
- tex_amode needs to be set to 1.
Add a new bit to the compiler specs and generate these instructions
as necessary.
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit fe3bb8cdb519a01e6315ce6f142827aece3d4a41)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
index dc9af57..7446a19 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
@@ -1444,7 +1444,42 @@ static void
trans_trig(const struct instr_translater *t, struct etna_compile *c,
const struct tgsi_full_instruction *inst, struct etna_inst_src *src)
{
- if (c->specs->has_sin_cos_sqrt) {
+ if (c->specs->has_new_sin_cos) { /* Alternative SIN/COS */
+ /* On newer chips alternative SIN/COS instructions are implemented,
+ * which:
+ * - Need their input scaled by 1/pi instead of 2/pi
+ * - Output an x and y component, which need to be multiplied to
+ * get the result
+ */
+ /* TGSI lowering should deal with SCS */
+ assert(inst->Instruction.Opcode != TGSI_OPCODE_SCS);
+
+ struct etna_native_reg temp = etna_compile_get_inner_temp(c); /* only using .xyz */
+ emit_inst(c, &(struct etna_inst) {
+ .opcode = INST_OPCODE_MUL,
+ .sat = 0,
+ .dst = etna_native_to_dst(temp, INST_COMPS_Z),
+ .src[0] = src[0], /* any swizzling happens here */
+ .src[1] = alloc_imm_f32(c, 1.0f / M_PI),
+ });
+ emit_inst(c, &(struct etna_inst) {
+ .opcode = inst->Instruction.Opcode == TGSI_OPCODE_COS
+ ? INST_OPCODE_COS
+ : INST_OPCODE_SIN,
+ .sat = 0,
+ .dst = etna_native_to_dst(temp, INST_COMPS_X | INST_COMPS_Y),
+ .src[2] = etna_native_to_src(temp, SWIZZLE(Z, Z, Z, Z)),
+ .tex = { .amode=1 }, /* Unknown bit needs to be set */
+ });
+ emit_inst(c, &(struct etna_inst) {
+ .opcode = INST_OPCODE_MUL,
+ .sat = inst->Instruction.Saturate,
+ .dst = convert_dst(c, &inst->Dst[0]),
+ .src[0] = etna_native_to_src(temp, SWIZZLE(X, X, X, X)),
+ .src[1] = etna_native_to_src(temp, SWIZZLE(Y, Y, Y, Y)),
+ });
+
+ } else if (c->specs->has_sin_cos_sqrt) {
/* TGSI lowering should deal with SCS */
assert(inst->Instruction.Opcode != TGSI_OPCODE_SCS);
diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h
index fa75c3e..983321a 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_internal.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h
@@ -59,6 +59,8 @@ struct etna_specs {
unsigned has_sign_floor_ceil : 1;
/* can use VS_RANGE, PS_RANGE registers*/
unsigned has_shader_range_registers : 1;
+ /* has the new sin/cos functions */
+ unsigned has_new_sin_cos : 1;
/* can use any kind of wrapping mode on npot textures */
unsigned npot_tex_any_wrap;
/* number of bits per TS tile */
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 0de74be..918b78d 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -620,6 +620,8 @@ etna_get_specs(struct etna_screen *screen)
screen->model >= 0x1000 || screen->model == 0x880;
screen->specs.npot_tex_any_wrap =
VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
+ screen->specs.has_new_sin_cos =
+ VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
if (instruction_count > 256) { /* unified instruction memory? */
screen->specs.vs_offset = 0xC000;
commit 05d1c8aa020cb61b9a53cdec92fdbf4dc56f966a
Author: Nanley Chery <nanley.g.chery@intel.com>
Date: Mon Jan 30 12:27:15 2017 -0800
anv/cmd_buffer: Use the proper depth input attachment surface state
Commit 2852efcda40274acf3272611c6a3b7731523a72d moved the location of
the depth input attachment surface state from the render pass to the
image view, but failed to update the surface state location used when
emitting the binding table. Fix this by loading the surface state from
the correct location.
Fixes:
dEQP-VK.renderpass.formats.d16_unorm.input.*
dEQP-VK.renderpass.formats.d24_unorm_s8_uint.input.*
dEQP-VK.renderpass.formats.d32_sfloat.input.*
dEQP-VK.renderpass.formats.x8_d24_unorm_pack32.input.*
dEQP-VK.renderpass.attachment_allocation.input_output.93
dEQP-VK.renderpass.attachment_allocation.input_output.92
dEQP-VK.renderpass.attachment_allocation.input_output.82
dEQP-VK.renderpass.attachment_allocation.input_output.46
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
(cherry picked from commit 33e0c5d003658320f5005e26caf55bbcfbe1fbb2)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index f7894a0..d93d377 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1177,9 +1177,9 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
assert(stage == MESA_SHADER_FRAGMENT);
- if (desc->image_view->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
- /* For stencil input attachments, we treat it like any old texture
- * that a user may have bound.
+ if (desc->image_view->aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT) {
+ /* For depth and stencil input attachments, we treat it like any
+ * old texture that a user may have bound.
*/
surface_state = desc->image_view->sampler_surface_state;
assert(surface_state.alloc_size);
@@ -1187,9 +1187,9 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
desc->image_view->image->aux_usage,
surface_state);
} else {
- /* For depth and color input attachments, we create the surface
- * state at vkBeginRenderPass time so that we can include aux
- * and clear color information.
+ /* For color input attachments, we create the surface state at
+ * vkBeginRenderPass time so that we can include aux and clear
+ * color information.
*/
assert(binding->input_attachment_index < subpass->input_count);
const unsigned subpass_att = binding->input_attachment_index;
commit ca222b7c1868491ede19f2da717b39c0a54e6846
Author: Bartosz Tomczyk <bartosz.tomczyk86@gmail.com>
Date: Tue Jan 31 12:02:20 2017 +0100
glsl: fix heap-buffer-overflow
The `end+1` skips the ']', whereas the `strlen+1` includes the final
'\0' in the move to terminate the string.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit fc27181f9e51441a26b7eb4f62794b5e9a994644)
diff --git a/src/compiler/glsl/link_uniforms.cpp b/src/compiler/glsl/link_uniforms.cpp
index 86711e2..1949867 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -535,7 +535,7 @@ private:
const char *str_end;
while((str_start = strchr(name_copy, '[')) &&
(str_end = strchr(name_copy, ']'))) {
- memmove(str_start, str_end + 1, 1 + strlen(str_end));
+ memmove(str_start, str_end + 1, 1 + strlen(str_end + 1));
}
unsigned index = 0;
commit 6c89a728d9e5d072cb504453e73077564c6523d3
Author: Wladimir J. van der Laan <laanwj@gmail.com>
Date: Wed Dec 7 12:59:54 2016 +0000
etnaviv: Cannot render to rb-swapped formats
Exposing rb swapped (or other swizzled) formats for rendering would
involve swizzing in the pixel shader. This is not the case at the
moment, so reject requests for creating such surfaces.
(GPUs that need an extra resolve step anyway due to multiple pixel
pipes, such as gc2000, might also do this swap in the resolve operation.
But this would be tricky to keep track of)
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit 658568941d5e232d690e1ffbcddbd6ea9685693a)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index fa76226..0de74be 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -469,8 +469,11 @@ etna_screen_is_format_supported(struct pipe_screen *pscreen,
return FALSE;
if (usage & PIPE_BIND_RENDER_TARGET) {
- /* if render target, must be RS-supported format */
- if (translate_rs_format(format) != ETNA_NO_MATCH) {
+ /* If render target, must be RS-supported format that is not rb swapped.
+ * Exposing rb swapped (or other swizzled) formats for rendering would
+ * involve swizzing in the pixel shader.
+ */
+ if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) {
/* Validate MSAA; number of samples must be allowed, and render target
* must have MSAA'able format. */
if (sample_count > 1) {
commit f3b7a513835605e340cbea351937969a9a420ef6
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date: Tue Jan 31 09:10:27 2017 +0100
etnaviv: Avoid infinite loop in find_frame()
Use of unsigned loop control variable with '>= 0' would lead
to infinite loop.
Reported by clang:
etnaviv_compiler.c:1024:39: warning: comparison of unsigned expression
>= 0 is always true [-Wtautological-compare]
for (unsigned sp = c->frame_sp; sp >= 0; sp--)
~~ ^ ~
v2: Simply use the same datatype as c->frame_sp is using.
CC: <mesa-stable@lists.freedesktop.org>
Reported-by: Rhys Kidd <rhyskidd@gmail.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
(cherry picked from commit 82fe240a9912d78bc2eec513c1139c918c5f189f)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
index 59e1452..dc9af57 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
@@ -1021,7 +1021,7 @@ label_mark_use(struct etna_compile *c, struct etna_compile_label *label)
static struct etna_compile_frame *
find_frame(struct etna_compile *c, enum etna_compile_frame_type type)
{
- for (unsigned sp = c->frame_sp; sp >= 0; sp--)
+ for (int sp = c->frame_sp; sp >= 0; sp--)
if (c->frame_stack[sp].type == type)
return &c->frame_stack[sp];
commit 9ecfbafedb09565b6ac5735c7893b0f58a46b8df
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Jan 31 10:09:11 2017 +1000
radv/ac: apply slice rounding to 1d arrays as well.
Fixes:
dEQP-VK.glsl.texture_functions.texture.*1darray*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8477aa71d902d6a6fd89741151f8d119a72a7dc0)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 68c2972..abced96 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3161,6 +3161,15 @@ static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
*fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
}
+static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
+ LLVMValueRef coord)
+{
+ coord = to_float(ctx, coord);
+ coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
+ coord = to_integer(ctx, coord);
+ return coord;
+}
+
static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
{
LLVMValueRef result = NULL;
@@ -3322,15 +3331,16 @@ static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
/* Pack texture coordinates */
if (coord) {
address[count++] = coords[0];
- if (instr->coord_components > 1)
+ if (instr->coord_components > 1) {
+ if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
+ coords[1] = apply_round_slice(ctx, coords[1]);
+ }
address[count++] = coords[1];
+ }
if (instr->coord_components > 2) {
/* This seems like a bit of a hack - but it passes Vulkan CTS with it */
if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
- coords[2] = to_float(ctx, coords[2]);
- coords[2] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coords[2],
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