libdrm: Changes to 'debian-experimental'
.editorconfig | 19
Android.common.mk | 12
Android.mk | 17
README | 6
amdgpu/Android.mk | 8
autogen.sh | 6
configure.ac | 11
debian/changelog | 9
debian/libdrm-intel1.symbols | 4
debian/libdrm2.symbols | 2
debian/rules | 4
debian/source/format | 1
debian/source/local-options | 6
etnaviv/Android.mk | 8
freedreno/Android.mk | 8
include/drm/i915_drm.h | 276 +++++++++++-
intel/Android.mk | 8
intel/intel-symbol-check | 4
intel/intel_bufmgr.h | 11
intel/intel_bufmgr_gem.c | 106 ++++
libkms/Android.mk | 6
libkms/Makefile.am | 4
libkms/exynos.c | 3
libkms/linux.c | 94 ----
nouveau/Android.mk | 8
radeon/Android.mk | 8
tests/Makefile.am | 46 --
tests/amdgpu/amdgpu_test.c | 259 ++++++++++-
tests/amdgpu/amdgpu_test.h | 3
tests/amdgpu/basic_tests.c | 7
tests/amdgpu/bo_tests.c | 13
tests/amdgpu/cs_tests.c | 8
tests/amdgpu/vce_tests.c | 8
tests/auth.c | 138 ------
tests/dristat.c | 285 ------------
tests/drmdevice.c | 60 ++
tests/drmtest.c | 135 ------
tests/drmtest.h | 40 -
tests/exynos/Makefile.am | 4
tests/getclient.c | 61 --
tests/getstats.c | 50 --
tests/getversion.c | 49 --
tests/lock.c | 264 -----------
tests/modetest/Android.mk | 3
tests/modetest/Makefile.am | 4
tests/modetest/modetest.c | 28 -
tests/name_from_fd.c | 58 --
tests/nouveau/Makefile.am | 8
tests/openclose.c | 37 -
tests/proptest/Android.mk | 3
tests/setversion.c | 91 ----
tests/updatedraw.c | 154 ------
tests/util/Android.mk | 7
tests/util/kms.c | 1
xf86drm.c | 962 +++++++++++++++++++++++++++++++++++++++----
xf86drm.h | 45 +-
xf86drmMode.c | 2
xf86drmMode.h | 19
58 files changed, 1747 insertions(+), 1754 deletions(-)
New commits:
commit c42cc002ab6ec4f757c3fe8fed52fe8915a052cb
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Wed Feb 1 17:08:39 2017 +0100
Upload to experimental.
diff --git a/debian/changelog b/debian/changelog
index c14b7dd..07f871e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,11 +1,11 @@
-libdrm (2.4.75-1) UNRELEASED; urgency=medium
+libdrm (2.4.75-1) experimental; urgency=medium
* New upstream release.
* Bump libdrm2's and libdrm-intel1's symbols and shlibs.
* Update extend-diff-ignore.
* Add debian/source/format file.
- -- Andreas Boll <andreas.boll.dev@gmail.com> Wed, 01 Feb 2017 15:56:49 +0100
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Wed, 01 Feb 2017 17:08:17 +0100
libdrm (2.4.74-2) experimental; urgency=medium
commit b7994bd7068cfd5956933abea1f06282a3a1a465
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Wed Feb 1 16:54:40 2017 +0100
Add debian/source/format file.
diff --git a/debian/changelog b/debian/changelog
index eda5cd3..c14b7dd 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -3,6 +3,7 @@ libdrm (2.4.75-1) UNRELEASED; urgency=medium
* New upstream release.
* Bump libdrm2's and libdrm-intel1's symbols and shlibs.
* Update extend-diff-ignore.
+ * Add debian/source/format file.
-- Andreas Boll <andreas.boll.dev@gmail.com> Wed, 01 Feb 2017 15:56:49 +0100
diff --git a/debian/source/format b/debian/source/format
new file mode 100644
index 0000000..d3827e7
--- /dev/null
+++ b/debian/source/format
@@ -0,0 +1 @@
+1.0
commit c408f868497cc33e2cc2b94522ab5e7bb328d97a
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Wed Feb 1 16:52:42 2017 +0100
Update extend-diff-ignore.
diff --git a/debian/changelog b/debian/changelog
index af6bbac..eda5cd3 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -2,6 +2,7 @@ libdrm (2.4.75-1) UNRELEASED; urgency=medium
* New upstream release.
* Bump libdrm2's and libdrm-intel1's symbols and shlibs.
+ * Update extend-diff-ignore.
-- Andreas Boll <andreas.boll.dev@gmail.com> Wed, 01 Feb 2017 15:56:49 +0100
diff --git a/debian/source/local-options b/debian/source/local-options
index b0c5d03..91254fb 100644
--- a/debian/source/local-options
+++ b/debian/source/local-options
@@ -4,10 +4,10 @@ extend-diff-ignore = intel/tests/g.*batch.sh
## The following files aren't shipped in the upstream tarball
# Android Makefiles
-extend-diff-ignore = Android\.mk|CleanSpec\.mk
+extend-diff-ignore = Android.*mk|CleanSpec\.mk
# misc. files and scripts used by libdrm developers but not required for the build
-extend-diff-ignore = RELEASING|autogen\.sh|freedreno/kgsl/README
+extend-diff-ignore = \.editorconfig|RELEASING|autogen\.sh|freedreno/kgsl/README
# dead code
-extend-diff-ignore = tests/auth.c|tests/lock.c
+extend-diff-ignore = tests/drmstat\.c
commit 918f29ffd9a188ea4767743e00baf9cef3ddbbff
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Wed Feb 1 16:51:57 2017 +0100
Bump libdrm2's and libdrm-intel1's symbols and shlibs.
diff --git a/debian/changelog b/debian/changelog
index 36ac821..af6bbac 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,7 @@
libdrm (2.4.75-1) UNRELEASED; urgency=medium
* New upstream release.
+ * Bump libdrm2's and libdrm-intel1's symbols and shlibs.
-- Andreas Boll <andreas.boll.dev@gmail.com> Wed, 01 Feb 2017 15:56:49 +0100
diff --git a/debian/libdrm-intel1.symbols b/debian/libdrm-intel1.symbols
index bf64a62..331b38d 100644
--- a/debian/libdrm-intel1.symbols
+++ b/debian/libdrm-intel1.symbols
@@ -39,6 +39,7 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
drm_intel_bufmgr_fake_set_exec_callback@Base 2.4.1
drm_intel_bufmgr_fake_set_fence_callback@Base 2.4.1
drm_intel_bufmgr_fake_set_last_dispatch@Base 2.4.1
+ drm_intel_bufmgr_gem_can_disable_implicit_sync@Base 2.4.75
drm_intel_bufmgr_gem_enable_fenced_relocs@Base 2.4.20
drm_intel_bufmgr_gem_enable_reuse@Base 2.4.1
drm_intel_bufmgr_gem_get_devid@Base 2.4.32
@@ -58,6 +59,9 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
drm_intel_gem_bo_aub_dump_bmp@Base 2.4.32
drm_intel_gem_bo_clear_relocs@Base 2.4.27
drm_intel_gem_bo_context_exec@Base 2.4.36
+ drm_intel_gem_bo_disable_implicit_sync@Base 2.4.75
+ drm_intel_gem_bo_enable_implicit_sync@Base 2.4.75
+ drm_intel_gem_bo_fence_exec@Base 2.4.75
drm_intel_gem_bo_get_reloc_count@Base 2.4.27
drm_intel_gem_bo_map__cpu@Base 2.4.73
drm_intel_gem_bo_map__gtt@Base 2.4.73
diff --git a/debian/libdrm2.symbols b/debian/libdrm2.symbols
index 275a4e9..75aaf4b 100644
--- a/debian/libdrm2.symbols
+++ b/debian/libdrm2.symbols
@@ -53,9 +53,11 @@ libdrm.so.2 libdrm2 #MINVER#
drmGetContextFlags@Base 2.3.1
drmGetContextPrivateMapping@Base 2.3.1
drmGetContextTag@Base 2.3.1
+ drmGetDevice2@Base 2.4.75
drmGetDevice@Base 2.4.66
drmGetDeviceNameFromFd2@Base 2.4.74
drmGetDeviceNameFromFd@Base 2.4.16
+ drmGetDevices2@Base 2.4.75
drmGetDevices@Base 2.4.65
drmGetEntry@Base 2.3.1
drmGetHashTable@Base 2.3.1
diff --git a/debian/rules b/debian/rules
index 067ed60..eb92a40 100755
--- a/debian/rules
+++ b/debian/rules
@@ -100,9 +100,9 @@ override_dh_install:
dh_install --fail-missing
override_dh_makeshlibs:
- dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.74)' --add-udeb=libdrm2-udeb -- -c4
+ dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.75)' --add-udeb=libdrm2-udeb -- -c4
ifeq ($(INTEL), yes)
- dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.74)' -- -c4
+ dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.75)' -- -c4
endif
ifeq ($(NOUVEAU), yes)
dh_makeshlibs -plibdrm-nouveau2 -V'libdrm-nouveau2 (>= 2.4.66)' -- -c4
commit 5390d51308e24f0faf95569d3687bc9db0e336a5
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Wed Feb 1 16:00:23 2017 +0100
Bump changelog
diff --git a/debian/changelog b/debian/changelog
index 5e2e240..36ac821 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+libdrm (2.4.75-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Andreas Boll <andreas.boll.dev@gmail.com> Wed, 01 Feb 2017 15:56:49 +0100
+
libdrm (2.4.74-2) experimental; urgency=medium
[ Andreas Boll ]
commit d4b8344363b4e0f0e831e5722b6df5cc0bb08df8
Author: Chad Versace <chadversary@chromium.org>
Date: Fri Jan 27 12:18:00 2017 -0800
Bump version for 2.4.75 release
For Intel explicit fencing.
Signed-off-by: Chad Versace <chadversary@chromium.org>
diff --git a/configure.ac b/configure.ac
index 39973b6..8e59332 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.74],
+ [2.4.75],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 0ad0c12fd3e04eaabec313432436fca462ca69ac
Author: Dave Airlie <airlied@redhat.com>
Date: Sat Jan 28 11:13:52 2017 +1000
intel: fix make distcheck
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/intel/intel-symbol-check b/intel/intel-symbol-check
index 038c982..2aa2d81 100755
--- a/intel/intel-symbol-check
+++ b/intel/intel-symbol-check
@@ -50,6 +50,7 @@ drm_intel_bufmgr_fake_init
drm_intel_bufmgr_fake_set_exec_callback
drm_intel_bufmgr_fake_set_fence_callback
drm_intel_bufmgr_fake_set_last_dispatch
+drm_intel_bufmgr_gem_can_disable_implicit_sync
drm_intel_bufmgr_gem_enable_fenced_relocs
drm_intel_bufmgr_gem_enable_reuse
drm_intel_bufmgr_gem_get_devid
@@ -69,6 +70,9 @@ drm_intel_decode_set_output_file
drm_intel_gem_bo_aub_dump_bmp
drm_intel_gem_bo_clear_relocs
drm_intel_gem_bo_context_exec
+drm_intel_gem_bo_disable_implicit_sync
+drm_intel_gem_bo_enable_implicit_sync
+drm_intel_gem_bo_fence_exec
drm_intel_gem_bo_get_reloc_count
drm_intel_gem_bo_map__cpu
drm_intel_gem_bo_map__gtt
commit ab5a9635563e43f8f948e4a29ea531e44ac9e79a
Author: Dave Airlie <airlied@redhat.com>
Date: Sat Jan 28 11:13:40 2017 +1000
Revert "Bump version for 2.4.75 release"
This reverts commit 736970c49beb9de7ab549f076069d52f4e7bc6f2.
diff --git a/configure.ac b/configure.ac
index 8e59332..39973b6 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.75],
+ [2.4.74],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 736970c49beb9de7ab549f076069d52f4e7bc6f2
Author: Chad Versace <chadversary@chromium.org>
Date: Fri Jan 27 12:18:00 2017 -0800
Bump version for 2.4.75 release
For Intel explicit fencing.
Signed-off-by: Chad Versace <chadversary@chromium.org>
diff --git a/configure.ac b/configure.ac
index 39973b6..8e59332 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.74],
+ [2.4.75],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit dfd536c60d0bdffe005e354be0677f066af94f83
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jan 27 20:25:04 2017 +0000
intel: Export a function to re-enable implicit synchronisation
Implicit synchronisation is the default behaviour of the kernel when
rendering with an execobject. It may be disabled with
drm_intel_gem_bo_disable_implicit_sync(), and then to restore it use
drm_intel_gem_bo_enable_implicit_sync().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 11579fb..693472a 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -187,6 +187,7 @@ int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
int drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr);
void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
+void drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo);
void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 077746c..a665600 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2816,6 +2816,25 @@ drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
}
/**
+ * Enables implicit synchronisation before executing the bo
+ *
+ * This is the default behaviour of the kernel, to wait upon prior writes
+ * completing on the object before rendering with it, or to wait for prior
+ * reads to complete before writing into the object.
+ * drm_intel_gem_bo_disable_implicit_sync() can stop this behaviour, telling
+ * the kernel never to insert a stall before using the object. Then this
+ * function can be used to restore the implicit sync before subsequent
+ * rendering.
+ */
+void
+drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo)
+{
+ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+
+ bo_gem->kflags &= ~EXEC_OBJECT_ASYNC;
+}
+
+/**
* Query whether the kernel supports disabling of its implicit synchronisation
* before execbuf. See drm_intel_gem_bo_disable_implicit_sync()
*/
commit 22cfd0431131538ad1953af86f7cc2d48af176d4
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jan 27 20:20:30 2017 +0000
intel: Clear execobject flags before preserving object in reuse cache
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 9195f3e..077746c 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1411,6 +1411,8 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
bo_gem->name = NULL;
bo_gem->validate_index = -1;
+ bo_gem->kflags = 0;
+
DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
} else {
drm_intel_gem_bo_free(bo);
commit c4b00767a7f3b2d00c7b1bc61e2b4d13f90c10ca
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Aug 20 12:38:46 2016 +0100
intel: Support passing of explicit fencing from execbuf
Allow the caller to pass in an fd to an array of fences to control
serialisation of the execbuf in the kernel and on the GPU, and in return
allow creation of a fence fd for signaling the completion (and flushing)
of the batch. When the returned fence is signaled, all writes to the
buffers inside the batch will be complete and coherent from the cpu, or
other consumers. The return fence is a sync_file object and can be
passed to other users (such as atomic modesetting, or other drivers).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index f43ee47..11579fb 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -221,6 +221,12 @@ int drm_intel_gem_context_get_id(drm_intel_context *ctx,
void drm_intel_gem_context_destroy(drm_intel_context *ctx);
int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
int used, unsigned int flags);
+int drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
+ drm_intel_context *ctx,
+ int used,
+ int in_fence,
+ int *out_fence,
+ unsigned int flags);
int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 554d079..9195f3e 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2376,6 +2376,7 @@ drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
static int
do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
+ int in_fence, int *out_fence,
unsigned int flags)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
@@ -2430,12 +2431,20 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
else
i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
execbuf.rsvd2 = 0;
+ if (in_fence != -1) {
+ execbuf.rsvd2 = in_fence;
+ execbuf.flags |= I915_EXEC_FENCE_IN;
+ }
+ if (out_fence != NULL) {
+ *out_fence = -1;
+ execbuf.flags |= I915_EXEC_FENCE_OUT;
+ }
if (bufmgr_gem->no_exec)
goto skip_execution;
ret = drmIoctl(bufmgr_gem->fd,
- DRM_IOCTL_I915_GEM_EXECBUFFER2,
+ DRM_IOCTL_I915_GEM_EXECBUFFER2_WR,
&execbuf);
if (ret != 0) {
ret = -errno;
@@ -2451,6 +2460,9 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
}
drm_intel_update_buffer_offsets2(bufmgr_gem);
+ if (ret == 0 && out_fence != NULL)
+ *out_fence = execbuf.rsvd2 >> 32;
+
skip_execution:
if (bufmgr_gem->bufmgr.debug)
drm_intel_gem_dump_validation_list(bufmgr_gem);
@@ -2476,7 +2488,7 @@ drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
int DR4)
{
return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
- I915_EXEC_RENDER);
+ -1, NULL, I915_EXEC_RENDER);
}
static int
@@ -2485,14 +2497,25 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
unsigned int flags)
{
return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
- flags);
+ -1, NULL, flags);
}
int
drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
int used, unsigned int flags)
{
- return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
+ return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags);
+}
+
+int
+drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
+ drm_intel_context *ctx,
+ int used,
+ int in_fence,
+ int *out_fence,
+ unsigned int flags)
+{
+ return do_exec2(bo, used, ctx, NULL, 0, 0, in_fence, out_fence, flags);
}
static int
commit 1bd35da961312aeb33fc7af586fa0d1f207a2d5f
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Aug 20 18:36:42 2016 +0100
intel: Allow the client to control implicit synchronisation
The kernel allows implicit synchronisation to be disabled on individual
buffers. Use at your own risk.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 85e4ff7..f43ee47 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -184,6 +184,10 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
+#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
+int drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr);
+void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
+
void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo);
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c47cb9b..554d079 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -149,6 +149,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
unsigned int has_vebox : 1;
+ unsigned int has_exec_async : 1;
bool fenced_relocs;
struct {
@@ -195,6 +196,8 @@ struct _drm_intel_bo_gem {
uint32_t swizzle_mode;
unsigned long stride;
+ unsigned long kflags;
+
time_t free_time;
/** Array passed to the DRM containing relocation information. */
@@ -575,12 +578,11 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr_gem->exec2_objects[index].alignment = bo->align;
- bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ?
- bo->offset64 : 0;
- bufmgr_gem->exec_bos[index] = bo;
- bufmgr_gem->exec2_objects[index].flags = flags;
+ bufmgr_gem->exec2_objects[index].offset = bo->offset64;
+ bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags;
bufmgr_gem->exec2_objects[index].rsvd1 = 0;
bufmgr_gem->exec2_objects[index].rsvd2 = 0;
+ bufmgr_gem->exec_bos[index] = bo;
bufmgr_gem->exec_count++;
}
@@ -1368,6 +1370,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
for (i = 0; i < bo_gem->softpin_target_count; i++)
drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
time);
+ bo_gem->kflags = 0;
bo_gem->reloc_count = 0;
bo_gem->used_as_reloc_target = false;
bo_gem->softpin_target_count = 0;
@@ -2766,6 +2769,40 @@ drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
}
/**
+ * Disables implicit synchronisation before executing the bo
+ *
+ * This will cause rendering corruption unless you correctly manage explicit
+ * fences for all rendering involving this buffer - including use by others.
+ * Disabling the implicit serialisation is only required if that serialisation
+ * is too coarse (for example, you have split the buffer into many
+ * non-overlapping regions and are sharing the whole buffer between concurrent
+ * independent command streams).
+ *
+ * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC,
+ * which can be checked using drm_intel_bufmgr_can_disable_implicit_sync,
+ * or subsequent execbufs involving the bo will generate EINVAL.
+ */
+void
+drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
+{
+ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+
+ bo_gem->kflags |= EXEC_OBJECT_ASYNC;
+}
+
+/**
+ * Query whether the kernel supports disabling of its implicit synchronisation
+ * before execbuf. See drm_intel_gem_bo_disable_implicit_sync()
+ */
+int
+drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr)
+{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
+
+ return bufmgr_gem->has_exec_async;
+}
+
+/**
* Enable use of fenced reloc type.
*
* New code should enable this to avoid unnecessary fence register
@@ -3635,6 +3672,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
bufmgr_gem->has_relaxed_fencing = ret == 0;
+ gp.param = I915_PARAM_HAS_EXEC_ASYNC;
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ bufmgr_gem->has_exec_async = ret == 0;
+
bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr;
gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
commit a3d715ee14b29d2680ceaf44955679205795140c
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jan 27 10:39:10 2017 +0000
Import uapi/i915_drm.h from v4.10-rc5-950-g152d5750dda9
To sync with "drm/i915: Support explicit fencing for execbuf"
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index eb611a7..5ebe046 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -29,6 +29,10 @@
#include "drm.h"
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*/
@@ -58,6 +62,30 @@
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
+/*
+ * MOCS indexes used for GPU surfaces, defining the cacheability of the
+ * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
+ */
+enum i915_mocs_table_index {
+ /*
+ * Not cached anywhere, coherency between CPU and GPU accesses is
+ * guaranteed.
+ */
+ I915_MOCS_UNCACHED,
+ /*
+ * Cacheability and coherency controlled by the kernel automatically
+ * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
+ * usage of the surface (used for display scanout or not).
+ */
+ I915_MOCS_PTE,
+ /*
+ * Cached in all GPU caches available on the platform.
+ * Coherency between CPU and GPU accesses to the surface is not
+ * guaranteed without extra synchronization.
+ */
+ I915_MOCS_CACHED,
+};
+
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
@@ -218,6 +246,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
#define DRM_I915_OVERLAY_ATTRS 0x28
#define DRM_I915_GEM_EXECBUFFER2 0x29
+#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
#define DRM_I915_GEM_WAIT 0x2c
@@ -230,6 +259,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_USERPTR 0x33
#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
+#define DRM_I915_PERF_OPEN 0x36
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -251,6 +281,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -283,6 +314,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
+#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -357,8 +389,28 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_GPU_RESET 35
#define I915_PARAM_HAS_RESOURCE_STREAMER 36
#define I915_PARAM_HAS_EXEC_SOFTPIN 37
-#define I915_PARAM_HAS_POOLED_EU 38
-#define I915_PARAM_MIN_EU_IN_POOL 39
+#define I915_PARAM_HAS_POOLED_EU 38
+#define I915_PARAM_MIN_EU_IN_POOL 39
+#define I915_PARAM_MMAP_GTT_VERSION 40
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+ * priorities and the driver will attempt to execute batches in priority order.
+ */
+#define I915_PARAM_HAS_SCHEDULER 41
+#define I915_PARAM_HUC_STATUS 42
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
+ * synchronisation with implicit fencing on individual objects.
+ * See EXEC_OBJECT_ASYNC.
+ */
+#define I915_PARAM_HAS_EXEC_ASYNC 43
+
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
+ * both being able to pass in a sync_file fd to wait upon before executing,
+ * and being able to return a new sync_file fd that is signaled when the
+ * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
+ */
+#define I915_PARAM_HAS_EXEC_FENCE 44
typedef struct drm_i915_getparam {
__s32 param;
@@ -694,15 +746,41 @@ struct drm_i915_gem_exec_object2 {
*/
__u64 offset;
-#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
-#define EXEC_OBJECT_NEEDS_GTT (1<<1)
-#define EXEC_OBJECT_WRITE (1<<2)
+#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
+#define EXEC_OBJECT_NEEDS_GTT (1<<1)
+#define EXEC_OBJECT_WRITE (1<<2)
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
-#define EXEC_OBJECT_PINNED (1<<4)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
+#define EXEC_OBJECT_PINNED (1<<4)
+#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
+/* The kernel implicitly tracks GPU activity on all GEM objects, and
+ * synchronises operations with outstanding rendering. This includes
+ * rendering on other devices if exported via dma-buf. However, sometimes
+ * this tracking is too coarse and the user knows better. For example,
+ * if the object is split into non-overlapping ranges shared between different
+ * clients or engines (i.e. suballocating objects), the implicit tracking
+ * by kernel assumes that each operation affects the whole object rather
+ * than an individual range, causing needless synchronisation between clients.
+ * The kernel will also forgo any CPU cache flushes prior to rendering from
+ * the object as the client is expected to be also handling such domain
+ * tracking.
+ *
+ * The kernel maintains the implicit tracking in order to manage resources
+ * used by the GPU - this flag only disables the synchronisation prior to
+ * rendering with this object in this execbuf.
+ *
+ * Opting out of implicit synhronisation requires the user to do its own
+ * explicit tracking to avoid rendering corruption. See, for example,
+ * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
+ */
+#define EXEC_OBJECT_ASYNC (1<<6)
+/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
__u64 flags;
- __u64 rsvd1;
+ union {
+ __u64 rsvd1;
+ __u64 pad_to_size;
+ };
__u64 rsvd2;
};
@@ -786,7 +864,32 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_RESOURCE_STREAMER (1<<15)
-#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
+/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_IN (1<<16)
+
+/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
+ * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
+ * to the caller, and it should be close() after use. (The fd is a regular
+ * file descriptor and will be cleaned up on process termination. It holds
+ * a reference to the request, but nothing else.)
+ *
+ * The sync_file fd can be combined with other sync_file and passed either
+ * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
+ * will only occur after this request completes), or to other devices.
+ *
+ * Using I915_EXEC_FENCE_OUT requires use of
+ * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
+ * back to userspace. Failure to do so will cause the out-fence to always
+ * be reported as zero, and the real fence fd to be leaked.
+ */
+#define I915_EXEC_FENCE_OUT (1<<17)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -822,7 +925,16 @@ struct drm_i915_gem_busy {
* having flushed any pending activity), and a non-zero return that
* the object is still in-flight on the GPU. (The GPU has not yet
* signaled completion for all pending requests that reference the
- * object.)
+ * object.) An object is guaranteed to become idle eventually (so
+ * long as no new GPU commands are executed upon it). Due to the
+ * asynchronous nature of the hardware, an object reported
+ * as busy may become idle before the ioctl is completed.
+ *
+ * Furthermore, if the object is busy, which engine is busy is only
+ * provided as a guide. There are race conditions which prevent the
+ * report of which engines are busy from being always accurate.
+ * However, the converse is not true. If the object is idle, the
+ * result of the ioctl, that all engines are idle, is accurate.
*
* The returned dword is split into two fields to indicate both
* the engines on which the object is being read, and the
@@ -845,6 +957,11 @@ struct drm_i915_gem_busy {
* execution engines, e.g. multiple media engines, which are
* mapped to the same identifier in the EXECBUFFER2 ioctl and
* so are not separately reported for busyness.
+ *
+ * Caveat emptor:
+ * Only the boolean result of this query is reliable; that is whether
+ * the object is idle or busy. The report of which engines are busy
+ * should be only used as a heuristic.
*/
__u32 busy;
};
@@ -893,6 +1010,7 @@ struct drm_i915_gem_caching {
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
+#define I915_TILING_LAST I915_TILING_Y
#define I915_BIT_6_SWIZZLE_NONE 0
#define I915_BIT_6_SWIZZLE_9 1
@@ -1169,7 +1287,145 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
+#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
+#define I915_CONTEXT_PARAM_BANNABLE 0x5
__u64 value;
};
+enum drm_i915_oa_format {
+ I915_OA_FORMAT_A13 = 1,
+ I915_OA_FORMAT_A29,
+ I915_OA_FORMAT_A13_B8_C8,
+ I915_OA_FORMAT_B4_C8,
+ I915_OA_FORMAT_A45_B8_C8,
+ I915_OA_FORMAT_B4_C8_A16,
+ I915_OA_FORMAT_C4_B8,
+
+ I915_OA_FORMAT_MAX /* non-ABI */
+};
+
+enum drm_i915_perf_property_id {
+ /**
+ * Open the stream for a specific context handle (as used with
+ * execbuffer2). A stream opened for a specific context this way
+ * won't typically require root privileges.
+ */
+ DRM_I915_PERF_PROP_CTX_HANDLE = 1,
+
+ /**
+ * A value of 1 requests the inclusion of raw OA unit reports as
+ * part of stream samples.
+ */
+ DRM_I915_PERF_PROP_SAMPLE_OA,
+
+ /**
+ * The value specifies which set of OA unit metrics should be
+ * be configured, defining the contents of any OA unit reports.
+ */
+ DRM_I915_PERF_PROP_OA_METRICS_SET,
+
+ /**
+ * The value specifies the size and layout of OA unit reports.
+ */
+ DRM_I915_PERF_PROP_OA_FORMAT,
+
+ /**
+ * Specifying this property implicitly requests periodic OA unit
+ * sampling and (at least on Haswell) the sampling frequency is derived
+ * from this exponent as follows:
+ *
+ * 80ns * 2^(period_exponent + 1)
+ */
+ DRM_I915_PERF_PROP_OA_EXPONENT,
+
+ DRM_I915_PERF_PROP_MAX /* non-ABI */
+};
+
+struct drm_i915_perf_open_param {
+ __u32 flags;
+#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
+#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
+#define I915_PERF_FLAG_DISABLED (1<<2)
+
+ /** The number of u64 (id, value) pairs */
+ __u32 num_properties;
+
+ /**
+ * Pointer to array of u64 (id, value) pairs configuring the stream
+ * to open.
+ */
+ __u64 properties_ptr;
+};
+
+/**
+ * Enable data capture for a stream that was either opened in a disabled state
+ * via I915_PERF_FLAG_DISABLED or was later disabled via
+ * I915_PERF_IOCTL_DISABLE.
+ *
+ * It is intended to be cheaper to disable and enable a stream than it may be
+ * to close and re-open a stream with the same configuration.
+ *
+ * It's undefined whether any pending data for the stream will be lost.
+ */
+#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
+
+/**
+ * Disable data capture for a stream.
+ *
+ * It is an error to try and read a stream that is disabled.
+ */
+#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
+
+/**
+ * Common to all i915 perf records
+ */
+struct drm_i915_perf_record_header {
+ __u32 type;
+ __u16 pad;
+ __u16 size;
+};
+
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