mesa: Changes to 'upstream-unstable'
Rebased ref, commits from common ancestor:
commit 2fc6a31f10e908af8f348aba796d0e6b1616b863
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Sep 5 12:14:11 2016 +0100
docs: add release notes for 12.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/12.0.2.html b/docs/relnotes/12.0.2.html
new file mode 100644
index 0000000..6745342
--- /dev/null
+++ b/docs/relnotes/12.0.2.html
@@ -0,0 +1,402 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 12.0.2 Release Notes / September 2, 2016</h1>
+
+<p>
+Mesa 12.0.2 is a bug fix release which fixes bugs found since the 12.0.1 release.
+</p>
+<p>
+Mesa 12.0.2 implements the OpenGL 4.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.3. OpenGL
+4.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=69622";>Bug 69622</a> - eglTerminate then eglMakeCurrent crahes</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=89599";>Bug 89599</a> - symbol 'x86_64_entry_start' is already defined when building with LLVM/clang</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91342";>Bug 91342</a> - Very dark textures on some objects in indoors environments in Postal 2</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=92306";>Bug 92306</a> - GL Excess demo renders incorrectly on nv43</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=94148";>Bug 94148</a> - Framebuffer considered invalid when a draw call is done before glCheckFramebufferStatus</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96274";>Bug 96274</a> - [NVC0] Failure when compiling compute shader: Assertion `bb->getFirst()->serial <= bb->getExit()->serial' failed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96358";>Bug 96358</a> - SSO: wrong interface validation between GS and VS (regresion due to latest gles 3.1)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96381";>Bug 96381</a> - Texture artifacts with immutable texture storage and mipmaps</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96762";>Bug 96762</a> - [radeonsi,apitrace] Firewatch: nothing rendered in scrollable (text) areas</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96835";>Bug 96835</a> - "gallium: Force blend color to 16-byte alignment" crash with "-march=native -O3" causes some 32bit games to crash</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96850";>Bug 96850</a> - Crucible tests fail for 32bit mesa</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96908";>Bug 96908</a> - [radeonsi] MSAA causes graphical artifacts</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96911";>Bug 96911</a> - webgl2 conformance2/textures/misc/tex-mipmap-levels.html crashes 12.1 Intel driver</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=96971";>Bug 96971</a> - invariant qualifier is not valid for shader inputs</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97039";>Bug 97039</a> - The Talos Principle and Serious Sam 3 GPU faults</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97207";>Bug 97207</a> - [IVY BRIDGE] Fragment shader discard writing to depth</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97214";>Bug 97214</a> - X not running with error "Failed to make EGL context current"</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97225";>Bug 97225</a> - [i965 on HD4600 Haswell] xcom switch to ingame cinematics cause segmentation fault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97231";>Bug 97231</a> - GL_DEPTH_CLAMP doesn't clamp to the far plane</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97307";>Bug 97307</a> - glsl/glcpp/tests/glcpp-test regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97331";>Bug 97331</a> - glDrawElementsBaseVertex doesn't work in display list on i915</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97351";>Bug 97351</a> - DrawElementsBaseVertex with VBO ignores base vertex on Intel GMA 9xx in some cases</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97426";>Bug 97426</a> - glScissor gives vertically inverted result</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97476";>Bug 97476</a> - Shader binaries should not be stored in the PipelineCache</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97567";>Bug 97567</a> - [SNB, ILK] ctl, piglit regressions in mesa 12.0.2rc1</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Andreas Boll (1):</p>
+<ul>
+ <li>configure.ac: Use ${datarootdir} for --with-vulkan-icddir help string too</li>
+</ul>
+
+<p>Bernard Kilarski (1):</p>
+<ul>
+ <li>glx: fix error code when there is no context bound</li>
+</ul>
+
+<p>Brian Paul (4):</p>
+<ul>
+ <li>svga: handle mismatched number of samplers, sampler views</li>
+ <li>mesa: use _mesa_clear_texture_image() in clear_texture_fields()</li>
+ <li>swrast: fix incorrectly positioned putImage() in swrast driver</li>
+ <li>mesa: fix format conversion bug in get_tex_rgba_uncompressed()</li>
+</ul>
+
+<p>Chad Versace (2):</p>
+<ul>
+ <li>i965: Fix miptree layout for EGLImage-based renderbuffers</li>
+ <li>i965: Respect miptree offsets in intel_readpixels_tiled_memcpy()</li>
+</ul>
+
+<p>Christian König (1):</p>
+<ul>
+ <li>st/mesa: fix reference counting bug in st_vdpau</li>
+</ul>
+
+<p>Chuck Atkins (1):</p>
+<ul>
+ <li>swr: Refactor checks for compiler feature flags</li>
+</ul>
+
+<p>Daniel Scharrer (1):</p>
+<ul>
+ <li>mesa: Fix fixed function spot lighting on newer hardware (again)</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+ <li>anv: fix writemask on blit fragment shader.</li>
+ <li>st/glsl_to_tgsi: fix st_src_reg_for_double constant.</li>
+</ul>
+
+<p>Emil Velikov (15):</p>
+<ul>
+ <li>docs: add sha256 checksums for 12.0.1</li>
+ <li>mesa: automake: list builddir before srcdir</li>
+ <li>mesa: scons: list builddir before srcdir</li>
+ <li>i965: store reference to the context within struct brw_fence (v2)</li>
+ <li>anv: remove internal 'validate' layer</li>
+ <li>anv: automake: use VISIBILITY_CFLAGS to restrict symbol visibility</li>
+ <li>anv: automake: build with -Bsymbolic</li>
+ <li>anv: do not export the Vulkan API</li>
+ <li>anv: remove dummy VK_DEBUG_MARKER_EXT entry points</li>
+ <li>isl: automake: use VISIBILITY_CFLAGS to restrict symbol visibility</li>
+ <li>cherry-ignore: temporary(?) drop "a4xx: make sure to actually clamp depth"</li>
+ <li>i915: Check return value of screen->image.loader->getBuffers</li>
+ <li>Revert "i965/miptree: Set logical_depth0 == 6 for cube maps"</li>
+ <li>glx/glvnd: list the strcmp arguments in correct order</li>
+ <li>Update version to 12.0.2</li>
+</ul>
+
+<p>Eric Anholt (4):</p>
+<ul>
+ <li>vc4: Close our screen's fd on screen close.</li>
+ <li>vc4: Disable early Z with computed depth.</li>
+ <li>vc4: Fix a leak of the src[] array of VPM reads in optimization.</li>
+ <li>vc4: Fix leak of the bo_handles table.</li>
+</ul>
+
+<p>Francisco Jerez (3):</p>
+<ul>
+ <li>i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.</li>
+ <li>i965: Make room in the batch epilogue for three more pipe controls.</li>
+ <li>i965: Fix remaining flush vs invalidate race conditions in brw_emit_pipe_control_flush.</li>
+</ul>
+
+<p>Haixia Shi (1):</p>
+<ul>
+ <li>platform_android: prevent deadlock in droid_swap_buffers</li>
+</ul>
+
+<p>Ian Romanick (5):</p>
+<ul>
+ <li>mesa: Strip arrayness from interface block names in some IO validation</li>
+ <li>glsl: Pack integer and double varyings as flat even if interpolation mode is none</li>
+ <li>glcpp: Track the actual version instead of just the version_resolved flag</li>
+ <li>glcpp: Only disallow #undef of pre-defined macros on GLSL ES >= 3.00 shaders</li>
+ <li>glsl: Mark cube map array sampler types as reserved in GLSL ES 3.10</li>
+</ul>
+
+<p>Ilia Mirkin (16):</p>
+<ul>
+ <li>mesa: etc2 online compression is unsupported, don't attempt it</li>
+ <li>st/mesa: return appropriate mesa format for ETC texture formats</li>
+ <li>mesa: set _NEW_BUFFERS when updating texture bound to current buffers</li>
+ <li>nv50,nvc0: srgb rendering is only available for rgba/bgra</li>
+ <li>vbo: allow DrawElementsBaseVertex in display lists</li>
+ <li>gallium/util: add helper to compute zmin/zmax for a viewport state</li>
+ <li>nv50,nvc0: fix depth range when halfz is enabled</li>
+ <li>nv50/ir: fix bb positions after exit instructions</li>
+ <li>vbo: add basevertex when looking up elements for vbo splitting</li>
+ <li>a4xx: only disable depth clipping, not all clipping, when requested</li>
+ <li>nv50/ir: make sure cfg iterator always hits all blocks</li>
+ <li>main: add missing EXTRA_END in OES_sample_variables get check</li>
+ <li>nouveau: always enable at least one RC</li>
+ <li>nv30: only bail on color/depth bpp mismatch when surfaces are swizzled</li>
+ <li>a4xx: make sure to actually clamp depth as requested</li>
+ <li>gk110/ir: fix quadop dall emission</li>
+</ul>
+
+<p>Jan Ziak (2):</p>
+<ul>
+ <li>egl/x11: avoid using freed memory if dri2 init fails</li>
+ <li>loader: fix memory leak in loader_dri3_open</li>
+</ul>
+
+<p>Jason Ekstrand (31):</p>
+<ul>
+ <li>nir/spirv: Don't multiply the push constant block size by 4</li>
+ <li>anv: Add a stub for CmdCopyQueryPoolResults on Ivy Bridge</li>
+ <li>glsl/types: Fix function type comparison function</li>
+ <li>glsl/types: Use _mesa_hash_data for hashing function types</li>
+ <li>genxml: Make gen6-7 blending look more like gen8</li>
+ <li>anv/pipeline: Unify blend state setup between gen7 and gen8</li>
+ <li>anv: Enable independentBlend on gen7</li>
+ <li>anv: Add an align_down_npot_u32 helper</li>
+ <li>anv: Handle VK_WHOLE_SIZE properly for buffer views</li>
+ <li>i965/miptree: Enforce that height == 1 for 1-D array textures</li>
+ <li>i965/miptree: Set logical_depth0 == 6 for cube maps</li>
+ <li>nir: Add a nir_deref_foreach_leaf helper</li>
+ <li>nir/inline: Constant-initialize local variables in the callee if needed</li>
+ <li>anv/pipeline: Set up point coord enables</li>
+ <li>i965/miptree: Stop multiplying cube depth by 6 in HiZ calculations</li>
+ <li>i965/vec4: Make opt_vector_float reset at the top of each block</li>
+ <li>anv/blit2d: Add a format parameter to bind_dst and create_iview</li>
+ <li>anv/blit2d: Add support for RGB destinations</li>
+ <li>anv/clear: Make cmd_clear_image take an actual VkClearValue</li>
+ <li>anv/clear: Clear E5B9G9R9 images as R32_UINT</li>
+ <li>anv: Include the pipeline layout in the shader hash</li>
+ <li>isl: Allow multisampled array textures</li>
+ <li>anv/descriptor_set: memset anv_descriptor_set_layout</li>
+ <li>anv/pipeline: Fix bind maps for fragment output arrays</li>
+ <li>anv/allocator: Correctly set the number of buckets</li>
+ <li>anv/pipeline: Properly handle OOM during shader compilation</li>
+ <li>anv: Remove unused fields from anv_pipeline_bind_map</li>
+ <li>anv: Add pipeline_has_stage guards a few places</li>
+ <li>anv: Add a struct for storing a compiled shader</li>
+ <li>anv/pipeline: Add support for caching the push constant map</li>
+ <li>anv: Rework pipeline caching</li>
+</ul>
+
+<p>José Fonseca (2):</p>
+<ul>
+ <li>appveyor: Install pywin32 extensions.</li>
+ <li>appveyor: Force Visual Studio 2013 image.</li>
+</ul>
+
+<p>Kenneth Graunke (21):</p>
+<ul>
+ <li>genxml: Add CLIPMODE_* prefix to 3DSTATE_CLIP's "Clip Mode" enum values.</li>
+ <li>genxml: Add APIMODE_D3D missing enum values and improve consistency.</li>
+ <li>anv: Fix near plane clipping on Gen7/7.5.</li>
+ <li>anv: Enable early culling on Gen7.</li>
+ <li>anv: Unify 3DSTATE_CLIP code across generations.</li>
+ <li>genxml: Rename "API Rendering Disable" to "Rendering Disable".</li>
+ <li>anv: Properly call gen75_emit_state_base_address on Haswell.</li>
+ <li>i965: Include VUE handles for GS with invocations > 1.</li>
+ <li>nir: Add a base const_index to shared atomic intrinsics.</li>
+ <li>i965: Fix shared atomic intrinsics to pay attention to base.</li>
+ <li>mesa: Add GL_BGRA_EXT to the list of GenerateMipmap internal formats.</li>
+ <li>mesa: Don't call GenerateMipmap if Width or Height == 0.</li>
+ <li>glsl: Delete bogus ir_set_program_inouts assert.</li>
+ <li>glsl: Fix the program resource names of gl_TessLevelOuter/Inner[].</li>
+ <li>glsl: Fix location bias for patch variables.</li>
+ <li>glsl: Fix invariant matching in GLSL 4.30 and GLSL ES 1.00.</li>
+ <li>mesa: Fix uf10_to_f32() scale factor in the E == 0 and M != 0 case.</li>
+ <li>nir/builder: Add bany_inequal and bany helpers.</li>
+ <li>i965: Implement the WaPreventHSTessLevelsInterference workaround.</li>
+ <li>i965: Fix execution size of scalar TCS barrier setup code.</li>
+ <li>i965: Fix barrier count shift in scalar TCS backend.</li>
+</ul>
+
+<p>Leo Liu (2):</p>
+<ul>
+ <li>st/omx/enc: check uninitialized list from task release</li>
+ <li>vl/dri3: fix a memory leak from front buffer</li>
+</ul>
+
+<p>Marek Olšák (7):</p>
+<ul>
+ <li>glsl_to_tgsi: don't use the negate modifier in integer ops after bitcast</li>
+ <li>radeonsi: add a workaround for a compute VGPR-usage LLVM bug</li>
+ <li>winsys/amdgpu: disallow DCC with mipmaps</li>
+ <li>gallium/util: fix align64</li>
+ <li>radeonsi: only set dual source blending for MRT0</li>
+ <li>radeonsi: fix VM faults due NULL internal const buffers on CIK</li>
+ <li>radeonsi: disable SDMA texture copying on Carrizo</li>
+</ul>
+
+<p>Matt Turner (4):</p>
+<ul>
+ <li>mapi: Massage code to allow clang to compile.</li>
+ <li>i965/vec4: Ignore swizzle of VGRF for use by var_range_end().</li>
+ <li>mesa: Use AC_HEADER_MAJOR to include correct header for major().</li>
+ <li>nir: Walk blocks in source code order in lower_vars_to_ssa.</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+ <li>glx: Don't use current context in __glXSendError</li>
+</ul>
+
+<p>Miklós Máté (1):</p>
+<ul>
+ <li>vbo: set draw_id</li>
+</ul>
+
+<p>Nanley Chery (5):</p>
+<ul>
+ <li>anv/descriptor_set: Fix binding partly undefined descriptor sets</li>
+ <li>isl: Fix assert on raw buffer surface state size</li>
+ <li>anv/device: Fix max buffer range limits</li>
+ <li>isl: Fix isl_tiling_is_any_y()</li>
+ <li>anv/gen7_pipeline: Set PixelShaderKillPixel for discards</li>
+</ul>
+
+<p>Nicolai Hähnle (7):</p>
+<ul>
+ <li>radeonsi: explicitly choose center locations for 1xAA on Polaris</li>
+ <li>radeonsi: fix Polaris MSAA regression</li>
+ <li>radeonsi: ensure sample locations are set for line and polygon smoothing</li>
+ <li>st_glsl_to_tgsi: only skip over slots of an input array that are present</li>
+ <li>glsl: fix optimization of discard nested multiple levels</li>
+ <li>radeonsi: flush TC L2 cache for indirect draw data</li>
+ <li>radeonsi: add si_set_rw_buffer to be used for internal descriptors</li>
+</ul>
+
+<p>Nicolas Boichat (6):</p>
+<ul>
+ <li>egl/dri2: dri2_make_current: Set EGL error if bindContext fails</li>
+ <li>egl/wayland: Set disp->DriverData to NULL on error</li>
+ <li>egl/surfaceless: Set disp->DriverData to NULL on error</li>
+ <li>egl/drm: Set disp->DriverData to NULL on error</li>
+ <li>egl/android: Set dpy->DriverData to NULL on error</li>
+ <li>egl/dri2: Add reference count for dri2_egl_display</li>
+</ul>
+
+<p>Rob Herring (3):</p>
+<ul>
+ <li>Android: add missing u_math.h include path for libmesa_isl</li>
+ <li>vc4: fix vc4_resource_from_handle() stride calculation</li>
+ <li>vc4: add hash table look-up for exported dmabufs</li>
+</ul>
+
+<p>Samuel Pitoiset (7):</p>
+<ul>
+ <li>nvc0/ir: fix images indirect access on Fermi</li>
+ <li>nvc0: fix the driver cb size when draw parameters are used</li>
+ <li>gm107/ir: add missing NEG modifier for IADD32I</li>
+ <li>gm107/ir: make use of ADD32I for all immediates</li>
+ <li>nvc0: upload sample locations on GM20x</li>
+ <li>nvc0: invalidate textures/samplers on GK104+</li>
+ <li>nv50/ir: always emit the NDV bit for OP_QUADOP</li>
+</ul>
+
+<p>Stefan Dirsch (1):</p>
+<ul>
+ <li>Avoid overflow in 'last' variable of FindGLXFunction(...)</li>
+</ul>
+
+<p>Stencel, Joanna (1):</p>
+<ul>
+ <li>egl/wayland-egl: Fix for segfault in dri2_wl_destroy_surface.</li>
+</ul>
+
+<p>Tim Rowley (2):</p>
+<ul>
+ <li>Revert "gallium: Force blend color to 16-byte alignment"</li>
+ <li>swr: switch from overriding -march to selecting features</li>
+</ul>
+
+<p>Tomasz Figa (8):</p>
+<ul>
+ <li>gallium/dri: Add shared glapi to LIBADD on Android</li>
+ <li>egl/android: Remove unused variables</li>
+ <li>egl/android: Check return value of dri2_get_dri_config()</li>
+ <li>egl/android: Stop leaking DRI images</li>
+ <li>gallium/winsys/kms: Fix double refcount when importing from prime FD (v2)</li>
+ <li>gallium/winsys/kms: Fully initialize kms_sw_dt at prime import time (v2)</li>
+ <li>gallium/winsys/kms: Move display target handle lookup to separate function</li>
+ <li>gallium/winsys/kms: Look up the GEM handle after importing a prime FD</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 63001e7ddfafe6a7a6d4449c020e594613920a3e
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Sep 5 12:09:24 2016 +0100
Update version to 12.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index b700dc1..f36e00a 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-12.0.1
+12.0.2
commit 7757de1ebfb4855a8c91d96be8c41d71c50a02ff
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Thu Sep 1 10:36:44 2016 +0100
glx/glvnd: list the strcmp arguments in correct order
Currently, due to the inverse order, strcmp will produce negative result
when the needle is towards the start of the haystack. Thus on the next
iteration(s) we'll end up further towards the end and eventually fail to
locate the entry.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 62b224d428e04760dc96afb93873d67683337f88)
diff --git a/src/glx/glxglvnd.c b/src/glx/glxglvnd.c
index 962eda8..098304d 100644
--- a/src/glx/glxglvnd.c
+++ b/src/glx/glxglvnd.c
@@ -24,8 +24,8 @@ static unsigned FindGLXFunction(const GLubyte *name)
while (first <= last) {
int middle = (first + last) / 2;
- int comp = strcmp((const char *) name,
- __glXDispatchTableStrings[middle]);
+ int comp = strcmp(__glXDispatchTableStrings[middle],
+ (const char *) name);
if (comp < 0)
first = middle + 1;
commit 8e9b6161eb327f9fb030b976a6078376f80a8f9b
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Sep 4 18:21:29 2016 -0400
gk110/ir: fix quadop dall emission
We recently starting to always emit the NDV (== dall) bit for quadops.
However it was folded into the wrong code word.
Fixes: e0a067ed48 (nv50/ir: always emit the NDV bit for OP_QUADOP)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 61e978524a0e5de4f8570b44bcb9b907a9187684)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index b3e6c56..939972d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -1320,8 +1320,8 @@ CodeEmitterGK110::emitTXQ(const TexInstruction *i)
void
CodeEmitterGK110::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
{
- code[0] = 0x00000202 | ((qOp & 1) << 31); // dall
- code[1] = 0x7fc00000 | (qOp >> 1) | (laneMask << 12);
+ code[0] = 0x00000002 | ((qOp & 1) << 31);
+ code[1] = 0x7fc00200 | (qOp >> 1) | (laneMask << 12); // dall
defId(i->def(0), 2);
srcId(i->src(0), 10);
commit 7c96b11fd6aaf74578f32f8f1c79b4cc93d50ec1
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Thu Sep 1 21:49:26 2016 -0400
a4xx: make sure to actually clamp depth as requested
We were previously ... not clamping. I guess this meant that everything
got clamped to 1/0, which was enough to pass the existing tests. Or
perhaps the clamping would only happen to the rasterized depth value and
not the frag shader's output depth value.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97231
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry-picked from 89f00f749fda4c1beca38f362c7f86bdc6e32785)
[imirkin: adjust ctx->batch to just ctx]
diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index a90a4ce..aeb61e7 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -1376,7 +1376,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
{
return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
}
-#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
+#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 00e985d..8b350ae 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -31,6 +31,7 @@
#include "util/u_memory.h"
#include "util/u_helpers.h"
#include "util/u_format.h"
+#include "util/u_viewport.h"
#include "freedreno_resource.h"
#include "freedreno_query_hw.h"
@@ -544,12 +545,14 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
}
- if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
+ if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
bool fragz = fp->has_kill | fp->writes_pos;
+ bool clamp = !ctx->rasterizer->depth_clip;
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, zsa->rb_depth_control |
+ COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
@@ -636,6 +639,30 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
}
+ if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
+ float zmin, zmax;
+ int depth = 24;
+ if (ctx->framebuffer.zsbuf) {
+ depth = util_format_get_component_bits(
+ pipe_surface_format(ctx->framebuffer.zsbuf),
+ UTIL_FORMAT_COLORSPACE_ZS, 0);
+ }
+ util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
+ &zmin, &zmax);
+
+ OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
+ if (depth == 32) {
+ OUT_RING(ring, fui(zmin));
+ OUT_RING(ring, fui(zmax));
+ } else if (depth == 16) {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffff));
+ } else {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
+ }
+ }
+
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
unsigned n = pfb->nr_cbufs;
commit 49e84b8f18631b9460ade078f86d7567b80c332d
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Sep 3 18:52:06 2016 +0100
Revert "i965/miptree: Set logical_depth0 == 6 for cube maps"
This reverts commit 48e9ecc47f078cba3f56694e4583003681717410.
The commit regressed several piglit tests on SNB/ILK hardware.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97567
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a82f7bb..c234f24 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -501,8 +501,10 @@ intel_miptree_create_layout(struct brw_context *brw,
}
}
- if (target == GL_TEXTURE_CUBE_MAP)
- assert(depth0 == 6);
+ if (target == GL_TEXTURE_CUBE_MAP) {
+ assert(depth0 == 1);
+ depth0 = 6;
+ }
mt->physical_width0 = width0;
mt->physical_height0 = height0;
@@ -1036,15 +1038,6 @@ intel_get_image_dims(struct gl_texture_image *image,
*height = 1;
*depth = image->Height;
break;
- case GL_TEXTURE_CUBE_MAP:
- /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
- * though we really have 6 slices.
- */
- assert(image->Depth == 1);
- *width = image->Width;
- *height = image->Height;
- *depth = 6;
- break;
default:
*width = image->Width;
*height = image->Height;
commit 463d9ea0dc84c356e6208e00e15cf1b4c672f267
Author: Jose Fonseca <jfonseca@vmware.com>
Date: Thu Aug 11 14:11:00 2016 +0100
appveyor: Force Visual Studio 2013 image.
It seems the default build image is now Visual Studio 2015, and Visual
Studio 2013 is not installed.
diff --git a/appveyor.yml b/appveyor.yml
index 2618f69..c2efa7e 100644
--- a/appveyor.yml
+++ b/appveyor.yml
@@ -37,6 +37,8 @@ cache:
- win_flex_bison-2.4.5.zip
- llvm-3.3.1-msvc2013-mtd.7z
+os: Visual Studio 2013
+
environment:
WINFLEXBISON_ARCHIVE: win_flex_bison-2.4.5.zip
LLVM_ARCHIVE: llvm-3.3.1-msvc2013-mtd.7z
commit 53e8701c7b01407787121269d2849c400d2273ee
Author: Jose Fonseca <jfonseca@vmware.com>
Date: Thu Aug 11 14:00:35 2016 +0100
appveyor: Install pywin32 extensions.
AppVeyor build images seem to have been upgraded to Python 2.7.12, but
no longer have pywin32 pre-installed.
diff --git a/appveyor.yml b/appveyor.yml
index 2e9b9d6..2618f69 100644
--- a/appveyor.yml
+++ b/appveyor.yml
@@ -47,6 +47,8 @@ install:
- python -m pip --version
# Install Mako
- python -m pip install --egg Mako
+# Install pywin32 extensions, needed by SCons
+- python -m pip install pypiwin32
# Install SCons
- python -m pip install --egg scons==2.4.1
- scons --version
commit 0fa0e2a5051f32438436adef20bd335eaf91feb2
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Wed Aug 31 00:54:17 2016 -0400
nv30: only bail on color/depth bpp mismatch when surfaces are swizzled
The actual restriction is a little weaker than I originally thought. See
https://bugs.freedesktop.org/show_bug.cgi?id=92306#c17 for the
suggestion. This also explain why things weren't *always* failing
before, only sometimes. We will allocate a non-swizzled depth buffer for
NPOT winsys buffer sizes, which they almost always are.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8caf2cb0c06fe0a1dddff3aed56392f376fda424)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_state.c b/src/gallium/drivers/nouveau/nv30/nv30_state.c
index fd604c2..43ecaac 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_state.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_state.c
@@ -379,8 +379,9 @@ nv30_set_framebuffer_state(struct pipe_context *pipe,
struct nv30_miptree *zeta_mt = nv30_miptree(fb->zsbuf->texture);
if (color_mt->swizzled != zeta_mt->swizzled ||
- (util_format_get_blocksize(fb->zsbuf->format) > 2) !=
- (util_format_get_blocksize(fb->cbufs[0]->format) > 2)) {
+ (color_mt->swizzled &&
+ (util_format_get_blocksize(fb->zsbuf->format) > 2) !=
+ (util_format_get_blocksize(fb->cbufs[0]->format) > 2))) {
nv30->framebuffer.zsbuf = NULL;
debug_printf("Mismatched color and zeta formats, ignoring zeta.\n");
}
commit 9a8d60539860d131a181e4d4ec446a5f5b699992
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Aug 25 01:49:49 2016 -0700
anv: Rework pipeline caching
The original pipeline cache the Kristian wrote was based on a now-false
premise that the shaders can be stored in the pipeline cache. The Vulkan
1.0 spec explicitly states that the pipeline cache object is transiant and
you are allowed to delete it after using it to create a pipeline with no
ill effects. As nice as Kristian's design was, it doesn't jive with the
expectation provided by the Vulkan spec.
The new pipeline cache uses reference-counted anv_shader_bin objects that
are backed by a large state pool. The cache itself is just a hash table
mapping keys hashes to anv_shader_bin objects. This has the added
advantage of removing one more hand-rolled hash table from mesa.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97476
Acked-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
(cherry picked from commit 10f9901bcef7724cb72fb2fe7e3dd8d6660d2f34)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c
index b4533ac..ca78c09 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -760,7 +760,7 @@ anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
return VK_SUCCESS;
}
- struct anv_pipeline_bind_map *map = &pipeline->bindings[stage];
+ struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
if (bias + map->surface_count == 0) {
*bt_state = (struct anv_state) { 0, };
return VK_SUCCESS;
@@ -925,7 +925,7 @@ anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
return VK_SUCCESS;
}
- struct anv_pipeline_bind_map *map = &pipeline->bindings[stage];
+ struct anv_pipeline_bind_map *map = &pipeline->shaders[stage]->bind_map;
if (map->sampler_count == 0) {
*state = (struct anv_state) { 0, };
return VK_SUCCESS;
@@ -1099,7 +1099,7 @@ anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
struct anv_push_constants *data =
cmd_buffer->state.push_constants[stage];
const struct brw_stage_prog_data *prog_data =
- cmd_buffer->state.pipeline->prog_data[stage];
+ anv_shader_bin_get_prog_data(cmd_buffer->state.pipeline->shaders[stage]);
/* If we don't actually have any push constants, bail. */
if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index f4c1528..cd8fb3a 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -877,7 +877,6 @@ VkResult anv_CreateDevice(
anv_block_pool_init(&device->instruction_block_pool, device, 128 * 1024);
anv_state_pool_init(&device->instruction_state_pool,
&device->instruction_block_pool);
- anv_pipeline_cache_init(&device->default_pipeline_cache, device);
anv_block_pool_init(&device->surface_state_block_pool, device, 4096);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index ac55b31..33c7fe4 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -204,6 +204,12 @@ void anv_DestroyPipeline(
pAllocator ? pAllocator : &device->alloc);
if (pipeline->blend_state.map)
anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
+
+ for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
+ if (pipeline->shaders[s])
+ anv_shader_bin_unref(device, pipeline->shaders[s]);
+ }
+
anv_free2(&device->alloc, pAllocator, pipeline);
}
@@ -391,15 +397,34 @@ anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
prog_data->binding_table.image_start = bias;
}
+static struct anv_shader_bin *
+anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
+ struct anv_pipeline_cache *cache,
+ const void *key_data, uint32_t key_size,
+ const void *kernel_data, uint32_t kernel_size,
+ const void *prog_data, uint32_t prog_data_size,
+ const struct anv_pipeline_bind_map *bind_map)
+{
+ if (cache) {
+ return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
+ kernel_data, kernel_size,
+ prog_data, prog_data_size,
+ bind_map);
+ } else {
+ return anv_shader_bin_create(pipeline->device, key_data, key_size,
+ kernel_data, kernel_size,
+ prog_data, prog_data_size, bind_map);
+ }
+}
+
+
static void
anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
gl_shader_stage stage,
- const struct brw_stage_prog_data *prog_data,
- struct anv_pipeline_bind_map *map)
+ struct anv_shader_bin *shader)
{
- pipeline->prog_data[stage] = prog_data;
+ pipeline->shaders[stage] = shader;
pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
- pipeline->bindings[stage] = *map;
}
static VkResult
@@ -412,21 +437,20 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
{
const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
- const struct brw_stage_prog_data *stage_prog_data;
struct anv_pipeline_bind_map map;
struct brw_vs_prog_key key;
- uint32_t kernel = NO_KERNEL;
+ struct anv_shader_bin *bin = NULL;
unsigned char sha1[20];
populate_vs_prog_key(&pipeline->device->info, &key);
- if (module->size > 0) {
+ if (cache) {
anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
pipeline->layout, spec_info);
- kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
+ bin = anv_pipeline_cache_search(cache, sha1, 20);
}
- if (kernel == NO_KERNEL) {
+ if (bin == NULL) {
struct brw_vs_prog_data prog_data = { 0, };
struct anv_pipeline_binding surface_to_descriptor[256];
struct anv_pipeline_binding sampler_to_descriptor[256];
@@ -465,28 +489,29 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
- stage_prog_data = &prog_data.base.base;
- kernel = anv_pipeline_cache_upload_kernel(cache,
- module->size > 0 ? sha1 : NULL,
- shader_code, code_size,
- &stage_prog_data, sizeof(prog_data),
- &map);
+ bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
+ shader_code, code_size,
+ &prog_data, sizeof(prog_data), &map);
+ if (!bin) {
+ ralloc_free(mem_ctx);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
+
ralloc_free(mem_ctx);
}
const struct brw_vs_prog_data *vs_prog_data =
- (const struct brw_vs_prog_data *) stage_prog_data;
+ (const struct brw_vs_prog_data *)anv_shader_bin_get_prog_data(bin);
if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
- pipeline->vs_simd8 = kernel;
+ pipeline->vs_simd8 = bin->kernel.offset;
pipeline->vs_vec4 = NO_KERNEL;
} else {
pipeline->vs_simd8 = NO_KERNEL;
- pipeline->vs_vec4 = kernel;
+ pipeline->vs_vec4 = bin->kernel.offset;
}
- anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
- stage_prog_data, &map);
+ anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
return VK_SUCCESS;
}
@@ -501,21 +526,20 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
{
const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
- const struct brw_stage_prog_data *stage_prog_data;
struct anv_pipeline_bind_map map;
struct brw_gs_prog_key key;
- uint32_t kernel = NO_KERNEL;
+ struct anv_shader_bin *bin = NULL;
unsigned char sha1[20];
populate_gs_prog_key(&pipeline->device->info, &key);
- if (module->size > 0) {
+ if (cache) {
anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
pipeline->layout, spec_info);
- kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
+ bin = anv_pipeline_cache_search(cache, sha1, 20);
}
- if (kernel == NO_KERNEL) {
+ if (bin == NULL) {
struct brw_gs_prog_data prog_data = { 0, };
struct anv_pipeline_binding surface_to_descriptor[256];
struct anv_pipeline_binding sampler_to_descriptor[256];
@@ -553,20 +577,20 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
}
/* TODO: SIMD8 GS */
- stage_prog_data = &prog_data.base.base;
- kernel = anv_pipeline_cache_upload_kernel(cache,
- module->size > 0 ? sha1 : NULL,
- shader_code, code_size,
- &stage_prog_data, sizeof(prog_data),
- &map);
+ bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
+ shader_code, code_size,
+ &prog_data, sizeof(prog_data), &map);
+ if (!bin) {
+ ralloc_free(mem_ctx);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
ralloc_free(mem_ctx);
}
- pipeline->gs_kernel = kernel;
+ pipeline->gs_kernel = bin->kernel.offset;
- anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
- stage_prog_data, &map);
+ anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
return VK_SUCCESS;
}
@@ -582,21 +606,20 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
{
const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
- const struct brw_stage_prog_data *stage_prog_data;
struct anv_pipeline_bind_map map;
struct brw_wm_prog_key key;
+ struct anv_shader_bin *bin = NULL;
unsigned char sha1[20];
populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
- if (module->size > 0) {
+ if (cache) {
anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
pipeline->layout, spec_info);
- pipeline->ps_ksp0 =
- anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
+ bin = anv_pipeline_cache_search(cache, sha1, 20);
}
- if (pipeline->ps_ksp0 == NO_KERNEL) {
+ if (bin == NULL) {
struct brw_wm_prog_data prog_data = { 0, };
struct anv_pipeline_binding surface_to_descriptor[256];
struct anv_pipeline_binding sampler_to_descriptor[256];
@@ -685,19 +708,20 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
- stage_prog_data = &prog_data.base;
- pipeline->ps_ksp0 =
- anv_pipeline_cache_upload_kernel(cache,
- module->size > 0 ? sha1 : NULL,
- shader_code, code_size,
- &stage_prog_data, sizeof(prog_data),
- &map);
+ bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
+ shader_code, code_size,
+ &prog_data, sizeof(prog_data), &map);
+ if (!bin) {
+ ralloc_free(mem_ctx);
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