mesa: Changes to 'ubuntu'
VERSION | 2
bin/.cherry-ignore | 3
configure.ac | 19
debian/changelog | 12
docs/relnotes/11.0.7.html | 3
docs/relnotes/11.0.8.html | 199 ++++++++++
src/gallium/auxiliary/nir/tgsi_to_nir.c | 14
src/gallium/auxiliary/tgsi/tgsi_scan.c | 3
src/gallium/auxiliary/tgsi/tgsi_scan.h | 1
src/gallium/auxiliary/util/u_helpers.c | 8
src/gallium/drivers/freedreno/a4xx/a4xx.xml.h | 8
src/gallium/drivers/freedreno/a4xx/fd4_program.c | 8
src/gallium/drivers/freedreno/a4xx/fd4_texture.c | 1
src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 15
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 6
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 5
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 43 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 2
src/gallium/drivers/nouveau/nv50/nv50_state.c | 7
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 6
src/gallium/drivers/r600/evergreen_state.c | 9
src/gallium/drivers/r600/r600_pipe.h | 2
src/gallium/drivers/r600/r600_shader.c | 155 +++++++
src/gallium/drivers/r600/r600_state_common.c | 18
src/gallium/drivers/r600/r600d.h | 1
src/gallium/drivers/radeon/Makefile.am | 5
src/gallium/drivers/radeon/cayman_msaa.c | 12
src/gallium/drivers/radeon/r600_pipe_common.c | 7
src/gallium/drivers/radeon/r600d_common.h | 2
src/gallium/drivers/radeon/radeon_uvd.c | 2
src/gallium/drivers/radeon/radeon_uvd.h | 5
src/gallium/drivers/radeonsi/si_compute.c | 39 -
src/gallium/drivers/radeonsi/si_shader.c | 10
src/gallium/drivers/radeonsi/si_shader.h | 4
src/gallium/drivers/radeonsi/si_state.c | 23 +
src/gallium/drivers/radeonsi/si_state_draw.c | 22 -
src/gallium/drivers/radeonsi/si_state_shaders.c | 4
src/gallium/targets/opencl/Makefile.am | 5
src/glsl/ast_to_hir.cpp | 4
src/glsl/linker.cpp | 8
src/mesa/drivers/common/meta_generate_mipmap.c | 17
src/mesa/drivers/dri/i965/brw_context.c | 18
src/mesa/drivers/dri/i965/brw_fs.cpp | 157 +++----
src/mesa/drivers/dri/i965/brw_fs.h | 6
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 41 +-
src/mesa/drivers/dri/i965/brw_surface_formats.c | 5
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4
src/mesa/main/shader_query.cpp | 11
src/mesa/main/varray.c | 2
53 files changed, 756 insertions(+), 214 deletions(-)
New commits:
commit 82f5f7fe8db13deaefa1f45fe74fa486f8a2b75c
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Wed Dec 23 14:54:26 2015 +0200
release to xenial
diff --git a/debian/changelog b/debian/changelog
index 1f8f9ed..ce2a3f3 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (11.0.8-1ubuntu1) xenial; urgency=medium
+
+ * Merge from debian.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 22 Dec 2015 16:59:55 +0200
+
mesa (11.0.8-1) unstable; urgency=medium
* New upstream release.
commit d4b7200fe893c252ed53289483f6d4a75e62c3b9
Author: Timo Aaltonen <tjaalton@debian.org>
Date: Tue Dec 22 16:18:15 2015 +0200
new release, upload to unstable
diff --git a/debian/changelog b/debian/changelog
index a370c4a..fea180b 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (11.0.8-1) unstable; urgency=medium
+
+ * New upstream release.
+
+ -- Timo Aaltonen <tjaalton@debian.org> Tue, 22 Dec 2015 16:12:35 +0200
+
mesa (11.0.7-1) unstable; urgency=medium
[ Julien Cristau ]
commit 261daab6b4f7a1cff143bebcd632ad5a2cdafa74
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Dec 21 09:22:06 2015 +0000
docs: add release notes for 11.0.8
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/docs/relnotes/11.0.8.html b/docs/relnotes/11.0.8.html
new file mode 100644
index 0000000..df4b4c2
--- /dev/null
+++ b/docs/relnotes/11.0.8.html
@@ -0,0 +1,199 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 11.0.8 Release Notes / December 9, 2015</h1>
+
+<p>
+Mesa 11.0.8 is a bug fix release which fixes bugs found since the 11.0.7 release.
+</p>
+<p>
+Mesa 11.0.8 implements the OpenGL 4.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.1. OpenGL
+4.1 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91806";>Bug 91806</a> - configure does not test whether assembler supports sse4.1</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=92849";>Bug 92849</a> - [IVB HSW BDW] piglit image load/store load-from-cleared-image.shader_test fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=92909";>Bug 92909</a> - Offset/alignment issue with layout std140 and vec3</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93004";>Bug 93004</a> - Guild Wars 2 crash on nouveau DX11 cards</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93215";>Bug 93215</a> - [Regression bisected] Ogles1conform Automatic mipmap generation test is fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93266";>Bug 93266</a> - gl_arb_shading_language_420pack does not allow binding of image variables</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Boyuan Zhang (1):</p>
+<ul>
+ <li>radeon/uvd: uv pitch separation for stoney</li>
+</ul>
+
+<p>Dave Airlie (9):</p>
+<ul>
+ <li>r600: do SQ flush ES ring rolling workaround</li>
+ <li>r600: SMX returns CONTEXT_DONE early workaround</li>
+ <li>r600/shader: split address get out to a function.</li>
+ <li>r600/shader: add utility functions to do single slot arithmatic</li>
+ <li>r600g: fix geom shader input indirect indexing.</li>
+ <li>r600: handle geometry dynamic input array index</li>
+ <li>radeonsi: handle doubles in lds load path.</li>
+ <li>mesa/varray: set double arrays to non-normalised.</li>
+ <li>mesa/shader: return correct attribute location for double matrix arrays</li>
+</ul>
+
+<p>Emil Velikov (8):</p>
+<ul>
+ <li>docs: add sha256 checksums for 11.0.7</li>
+ <li>cherry-ignore: don't pick a specific i965 formats patch</li>
+ <li>Revert "i965/nir: Remove unused indirect handling"</li>
+ <li>Revert "i965/state: Get rid of dword_pitch arguments to buffer functions"</li>
+ <li>Revert "i965/vec4: Use a stride of 1 and byte offsets for UBOs"</li>
+ <li>Revert "i965/fs: Use a stride of 1 and byte offsets for UBOs"</li>
+ <li>Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"</li>
+ <li>Update version to 11.0.8</li>
+</ul>
+
+<p>Francisco Jerez (1):</p>
+<ul>
+ <li>i965: Resolve color and flush for all active shader images in intel_update_state().</li>
+</ul>
+
+<p>Ian Romanick (1):</p>
+<ul>
+ <li>meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER</li>
+</ul>
+
+<p>Ilia Mirkin (17):</p>
+<ul>
+ <li>freedreno/a4xx: support lod_bias</li>
+ <li>freedreno/a4xx: fix 5_5_5_1 texture sampler format</li>
+ <li>freedreno/a4xx: point regid to "red" even for alpha-only rb formats</li>
+ <li>nvc0/ir: fold postfactor into immediate</li>
+ <li>nv50/ir: deal with loops with no breaks</li>
+ <li>nv50/ir: the mad source might not have a defining instruction</li>
+ <li>nv50/ir: fix instruction permutation logic</li>
+ <li>nv50/ir: don't forget to mark flagsDef on cvt in txb lowering</li>
+ <li>nv50/ir: fix DCE to not generate 96-bit loads</li>
+ <li>nv50/ir: avoid looking at uninitialized srcMods entries</li>
+ <li>gk110/ir: fix imul hi emission with limm arg</li>
+ <li>gk104/ir: sampler doesn't matter for txf</li>
+ <li>gk110/ir: fix imad sat/hi flag emission for immediate args</li>
+ <li>nv50/ir: fix cutoff for using r63 vs r127 when replacing zero</li>
+ <li>nv50/ir: can't have predication and immediates</li>
+ <li>glsl: assign varying locations to tess shaders when doing SSO</li>
+ <li>ttn: add TEX2 support</li>
+</ul>
+
+<p>Jason Ekstrand (5):</p>
+<ul>
+ <li>i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge</li>
+ <li>i965/fs: Use a stride of 1 and byte offsets for UBOs</li>
+ <li>i965/vec4: Use a stride of 1 and byte offsets for UBOs</li>
+ <li>i965/state: Get rid of dword_pitch arguments to buffer functions</li>
+ <li>i965/nir: Remove unused indirect handling</li>
+</ul>
+
+<p>Jonathan Gray (2):</p>
+<ul>
+ <li>configure.ac: use pkg-config for libelf</li>
+ <li>configure: check for python2.7 for PYTHON2</li>
+</ul>
+
+<p>Kenneth Graunke (2):</p>
+<ul>
+ <li>i965: Fix fragment shader struct inputs.</li>
+ <li>i965: Fix scalar vertex shader struct outputs.</li>
+</ul>
+
+<p>Marek Olšák (8):</p>
+<ul>
+ <li>radeonsi: fix occlusion queries on Fiji</li>
+ <li>radeonsi: fix a hang due to uninitialized border color registers</li>
+ <li>radeonsi: fix Fiji for LLVM <= 3.7</li>
+ <li>radeonsi: don't call of u_prims_for_vertices for patches and rectangles</li>
+ <li>radeonsi: apply the streamout workaround to Fiji as well</li>
+ <li>gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly</li>
+ <li>tgsi/scan: add flag colors_written</li>
+ <li>r600g: write all MRTs only if there is exactly one output (fixes a hang)</li>
+</ul>
+
+<p>Matt Turner (1):</p>
+<ul>
+ <li>glsl: Allow binding of image variables with 420pack.</li>
+</ul>
+
+<p>Neil Roberts (2):</p>
+<ul>
+ <li>i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format</li>
+ <li>i965: Add B8G8R8X8_SRGB to the alpha format override</li>
+</ul>
+
+<p>Oded Gabbay (1):</p>
+<ul>
+ <li>configura.ac: fix test for SSE4.1 assembler support</li>
+</ul>
+
+<p>Patrick Rudolph (2):</p>
+<ul>
+ <li>nv50,nvc0: fix use-after-free when vertex buffers are unbound</li>
+ <li>gallium/util: return correct number of bound vertex buffers</li>
+</ul>
+
+<p>Samuel Pitoiset (1):</p>
+<ul>
+ <li>nvc0: free memory allocated by the prog which reads MP perf counters</li>
+</ul>
+
+<p>Tapani Pälli (1):</p>
+<ul>
+ <li>i965: use _Shader to get fragment program when updating surface state</li>
+</ul>
+
+<p>Tom Stellard (2):</p>
+<ul>
+ <li>radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}</li>
+ <li>radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 9f3bb782c607ec497dc7cc5a98d907e9ea985fc2
Author: Emil Velikov <emil.velikov@collabora.com>
Date: Mon Dec 21 09:16:42 2015 +0000
Update version to 11.0.8
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
diff --git a/VERSION b/VERSION
index 229ebd3..b32da19 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-11.0.7
+11.0.8
commit 94ac4b3e84737b8c5faa371834670fd25502e024
Author: Marek Olšák <marek.olsak@amd.com>
Date: Fri Dec 18 17:16:39 2015 +0100
r600g: write all MRTs only if there is exactly one output (fixes a hang)
This fixes a hang in
piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD.
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry-picked from commit b5b87c4ed1dfd58aec8905e0514c9ba92ba83e1d)
Conflicts:
src/gallium/drivers/r600/r600_shader.c
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index b345f14..911e81f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2109,7 +2109,9 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
ctx.nliterals = 0;
ctx.literals = NULL;
- shader->fs_write_all = FALSE;
+
+ shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
+ ctx.info.colors_written == 1;
if (shader->vs_as_gs_a)
vs_add_primid_output(&ctx, key.vs.prim_id_out);
@@ -2140,10 +2142,6 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
case TGSI_TOKEN_TYPE_PROPERTY:
property = &ctx.parse.FullToken.FullProperty;
switch (property->Property.PropertyName) {
- case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
- if (property->u[0].Data == 1)
- shader->fs_write_all = TRUE;
- break;
case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
if (property->u[0].Data == 1)
shader->vs_position_window_space = TRUE;
commit d126fffe9d22223cb2c4e0eef329b028870d48af
Author: Marek Olšák <marek.olsak@amd.com>
Date: Thu Dec 10 13:15:50 2015 +0100
tgsi/scan: add flag colors_written
This is a prerequisite for the following r600g fix.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit eb4813a9524e1a61f46bf45150adb1bd78564863)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 7523baf..98a5fec 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -258,6 +258,9 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
info->output_semantic_index[reg] = (ubyte) semIndex;
info->num_outputs++;
+ if (semName == TGSI_SEMANTIC_COLOR)
+ info->colors_written |= 1 << semIndex;
+
if (procType == TGSI_PROCESSOR_VERTEX ||
procType == TGSI_PROCESSOR_GEOMETRY ||
procType == TGSI_PROCESSOR_TESS_CTRL ||
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index b81bdd7..6301f91 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -76,6 +76,7 @@ struct tgsi_shader_info
uint opcode_count[TGSI_OPCODE_LAST]; /**< opcode histogram */
+ ubyte colors_written;
boolean reads_position; /**< does fragment shader read position? */
boolean reads_z; /**< does fragment shader read depth? */
boolean writes_z; /**< does fragment shader write Z value? */
commit 4b4ca9ca38471bff5156b4006bc54148c84cdf97
Author: Boyuan Zhang <boyuan.zhang@amd.com>
Date: Thu Nov 12 18:01:16 2015 -0500
radeon/uvd: uv pitch separation for stoney
v2: set the behaviour default for future ASICs.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit f55f134a033a61d67c2a71bbe57f85eb3484eec1)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index 55c216a..3a5d9f4 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -951,6 +951,8 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
dec->msg->body.decode.db_pitch = dec->base.width;
dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
+ if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
+ dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
switch (u_reduce_video_profile(picture->profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h
index 452fbd6..756f698 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -385,7 +385,10 @@ struct ruvd_msg {
uint32_t dt_chroma_top_offset;
uint32_t dt_chroma_bottom_offset;
uint32_t dt_surf_tile_config;
- uint32_t dt_reserved[3];
+ uint32_t dt_uv_surf_tile_config;
+ // re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
+ uint32_t dt_wa_chroma_top_offset;
+ uint32_t dt_wa_chroma_bottom_offset;
uint32_t reserved[16];
commit 9c9e843733d71a1d57f551c28855a5306fab9e93
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Fri Nov 20 16:51:07 2015 -0500
ttn: add TEX2 support
This fixes CubeArrayShadow tests (where the shadow comes in via a second
arg to the TEX2 instruction).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 4fd24caf92fc995e4a730181e0f179a7f2218e60)
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 93dfb80..14370e2 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1087,6 +1087,11 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
op = nir_texop_tex;
num_srcs = 1;
break;
+ case TGSI_OPCODE_TEX2:
+ op = nir_texop_tex;
+ num_srcs = 1;
+ samp = 2;
+ break;
case TGSI_OPCODE_TXP:
op = nir_texop_tex;
num_srcs = 2;
@@ -1242,10 +1247,12 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
}
if (instr->is_shadow) {
- if (instr->coord_components < 3)
- instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
- else
+ if (instr->coord_components == 4)
+ instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
+ else if (instr->coord_components == 3)
instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
+ else
+ instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
instr->src[src_number].src_type = nir_tex_src_comparitor;
src_number++;
@@ -1651,6 +1658,7 @@ ttn_emit_instruction(struct ttn_compile *c)
case TGSI_OPCODE_TXL:
case TGSI_OPCODE_TXB:
case TGSI_OPCODE_TXD:
+ case TGSI_OPCODE_TEX2:
case TGSI_OPCODE_TXL2:
case TGSI_OPCODE_TXB2:
case TGSI_OPCODE_TXQ_LZ:
commit 0f98683c83d92a4b430ee61b654625a435932b2e
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Dec 19 00:19:14 2015 +0000
Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"
This reverts commit 34cbde2e6320a55f54180e7f9f68db435b58e542.
As mentioned in the beginning of this revert series - let's pull the lot
out, as they cause regressions.
Additionally they are bugfixes (as opposed to regression fixes), which
if needed will need to be reworked.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 1b2ce15..92050b9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -996,21 +996,8 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
gen6_resolve_implied_move(p, &header, inst->base_mrf);
- if (devinfo->gen >= 6) {
- if (offset.file == BRW_IMMEDIATE_VALUE) {
- brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
- BRW_REGISTER_TYPE_D),
- brw_imm_d(offset.dw1.ud >> 4));
- } else {
- brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
- BRW_REGISTER_TYPE_D),
- offset, brw_imm_d(4));
- }
- } else {
- brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
- BRW_REGISTER_TYPE_D),
- offset);
- }
+ brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
+ offset);
uint32_t msg_type;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index b2adb9a..23b2fab 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -660,20 +660,12 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
unsigned const_offset = instr->const_index[0];
src_reg offset;
- if (devinfo->gen <= 6) {
- if (!has_indirect) {
- offset = src_reg(const_offset & ~15);
- } else {
- offset = get_nir_src(instr->src[1], nir_type_int, 1);
- }
+ if (!has_indirect) {
+ offset = src_reg(const_offset / 16);
} else {
- if (!has_indirect) {
- offset = src_reg(const_offset & ~15);
- } else {
- offset = src_reg(this, glsl_type::uint_type);
- emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
- src_reg(4u)));
- }
+ offset = src_reg(this, glsl_type::uint_type);
+ emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
+ src_reg(4u)));
}
src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 005c8b1..9062bcc 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3432,10 +3432,10 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
src_reg(reg_offset)));
- /* Pre-gen7, the message header uses byte offsets instead of vec4
+ /* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
- if (devinfo->gen < 7) {
+ if (devinfo->gen < 6) {
emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
}
@@ -3446,7 +3446,7 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset)));
return offset;
} else {
- int message_header_scale = devinfo->gen < 7 ? 16 : 1;
+ int message_header_scale = devinfo->gen < 6 ? 16 : 1;
return src_reg(reg_offset * message_header_scale);
}
}
commit eff2eea1452ea35c2e7eaf063ec4902cb18dc437
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Dec 19 00:18:54 2015 +0000
Revert "i965/fs: Use a stride of 1 and byte offsets for UBOs"
This reverts commit 0ae22b3ebde780c2c88b5bfceaf172e311bd4742.
See the previous reverts.
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index aea985b..12bf0c8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -185,7 +185,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
* the redundant ones.
*/
fs_reg vec4_offset = vgrf(glsl_type::int_type);
- bld.ADD(vec4_offset, varying_offset, fs_reg(const_offset & ~0xf));
+ bld.ADD(vec4_offset, varying_offset, fs_reg(const_offset & ~3));
int scale = 1;
if (devinfo->gen == 4 && bld.dispatch_width() == 8) {
@@ -217,7 +217,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
inst->mlen = 1 + bld.dispatch_width() / 8;
}
- bld.MOV(dst, offset(vec4_result, bld, ((const_offset & 0xf) / 4) * scale));
+ bld.MOV(dst, offset(vec4_result, bld, (const_offset & 3) * scale));
}
/**
@@ -1939,12 +1939,10 @@ fs_visitor::demote_pull_constants()
/* Generate a pull load into dst. */
if (inst->src[i].reladdr) {
- fs_reg indirect = ibld.vgrf(BRW_REGISTER_TYPE_D);
- ibld.MUL(indirect, *inst->src[i].reladdr, brw_imm_d(4));
VARYING_PULL_CONSTANT_LOAD(ibld, dst,
surf_index,
- indirect,
- pull_index * 4);
+ *inst->src[i].reladdr,
+ pull_index);
inst->src[i].reladdr = NULL;
inst->src[i].stride = 1;
} else {
@@ -2980,11 +2978,13 @@ fs_visitor::lower_uniform_pull_constant_loads()
continue;
if (devinfo->gen >= 7) {
- /* The offset arg is a vec4-aligned immediate byte offset. */
+ /* The offset arg before was a vec4-aligned byte offset. We need to
+ * turn it into a dword offset.
+ */
fs_reg const_offset_reg = inst->src[1];
assert(const_offset_reg.file == IMM &&
const_offset_reg.type == BRW_REGISTER_TYPE_UD);
- assert(const_offset_reg.fixed_hw_reg.dw1.ud % 16 == 0);
+ const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
fs_reg payload, offset;
if (devinfo->gen >= 9) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 1230383..5ebbf70 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1588,13 +1588,16 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
}
if (has_indirect) {
- fs_reg base_offset = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_D);
+ /* Turn the byte offset into a dword offset. */
+ fs_reg base_offset = vgrf(glsl_type::int_type);
+ bld.SHR(base_offset, retype(get_nir_src(instr->src[1]),
+ BRW_REGISTER_TYPE_D),
+ fs_reg(2));
- unsigned vec4_offset = instr->const_index[0];
+ unsigned vec4_offset = instr->const_index[0] / 4;
for (int i = 0; i < instr->num_components; i++)
VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
- base_offset, vec4_offset + i * 4);
+ base_offset, vec4_offset + i);
} else {
fs_reg packed_consts = vgrf(glsl_type::float_type);
packed_consts.type = dest.type;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 53c85e9..b8e1f70 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -403,7 +403,7 @@ brw_create_constant_surface(struct brw_context *brw,
uint32_t *out_offset,
bool dword_pitch)
{
- uint32_t stride = dword_pitch ? 1 : 16;
+ uint32_t stride = dword_pitch ? 4 : 16;
uint32_t elements = ALIGN(size, stride) / stride;
brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
commit 0452dcd92da3eb4d31b6a83a2c39968e18d1f1d1
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Dec 19 00:18:07 2015 +0000
Revert "i965/vec4: Use a stride of 1 and byte offsets for UBOs"
This reverts commit 147c3fbdb3f779f5172304e3be10cc27e0e67be7.
See the previous reverts.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 19a71f3..b2adb9a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -660,10 +660,20 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
unsigned const_offset = instr->const_index[0];
src_reg offset;
- if (!has_indirect) {
- offset = src_reg(const_offset & ~15);
+ if (devinfo->gen <= 6) {
+ if (!has_indirect) {
+ offset = src_reg(const_offset & ~15);
+ } else {
+ offset = get_nir_src(instr->src[1], nir_type_int, 1);
+ }
} else {
- offset = get_nir_src(instr->src[1], nir_type_int, 1);
+ if (!has_indirect) {
+ offset = src_reg(const_offset & ~15);
+ } else {
+ offset = src_reg(this, glsl_type::uint_type);
+ emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
+ src_reg(4u)));
+ }
}
src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c5de3aa..005c8b1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3431,16 +3431,23 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
src_reg(reg_offset)));
- emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
+
+ /* Pre-gen7, the message header uses byte offsets instead of vec4
+ * (16-byte) offset units.
+ */
+ if (devinfo->gen < 7) {
+ emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
+ }
return index;
} else if (devinfo->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
src_reg offset = src_reg(this, glsl_type::int_type);
- emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset * 16)));
+ emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset)));
return offset;
} else {
- return src_reg(reg_offset * 16);
+ int message_header_scale = devinfo->gen < 7 ? 16 : 1;
+ return src_reg(reg_offset * message_header_scale);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e689fed..53c85e9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -403,9 +403,12 @@ brw_create_constant_surface(struct brw_context *brw,
uint32_t *out_offset,
bool dword_pitch)
{
+ uint32_t stride = dword_pitch ? 1 : 16;
+ uint32_t elements = ALIGN(size, stride) / stride;
+
brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
- size, 1, false);
+ elements, stride, false);
}
/**
commit 86f18de1c05457ec3c709f4e1e6bf93bac93db4f
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Dec 19 00:17:43 2015 +0000
Revert "i965/state: Get rid of dword_pitch arguments to buffer functions"
This reverts commit 683d65dae3e673ee95d544008874edf1255e87cf.
See previous commit.
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ba8e1df..b52bca7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1776,7 +1776,8 @@ void brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
uint32_t size,
- uint32_t *out_offset);
+ uint32_t *out_offset,
+ bool dword_pitch);
void brw_update_buffer_texture_surface(struct gl_context *ctx,
unsigned unit,
uint32_t *surf_offset);
@@ -1788,7 +1789,8 @@ brw_update_sol_surface(struct brw_context *brw,
void brw_upload_ubo_surfaces(struct brw_context *brw,
struct gl_shader *shader,
struct brw_stage_state *stage_state,
- struct brw_stage_prog_data *prog_data);
+ struct brw_stage_prog_data *prog_data,
+ bool dword_pitch);
void brw_upload_abo_surfaces(struct brw_context *brw,
struct gl_shader_program *prog,
struct brw_stage_state *stage_state,
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
index 2b2ed2e..00125c0 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -48,10 +48,11 @@ brw_upload_gs_pull_constants(struct brw_context *brw)
/* BRW_NEW_GS_PROG_DATA */
const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
+ const bool dword_pitch = prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_GS_CONSTBUF, &gp->program.Base,
- stage_state, &prog_data->base);
+ stage_state, &prog_data->base, dword_pitch);
}
const struct brw_tracked_state brw_gs_pull_constants = {
@@ -78,9 +79,10 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw)
/* BRW_NEW_GS_PROG_DATA */
struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
+ bool dword_pitch = prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_GEOMETRY],
- &brw->gs.base, &prog_data->base);
+ &brw->gs.base, &prog_data->base, dword_pitch);
}
const struct brw_tracked_state brw_gs_ubo_surfaces = {
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 0618334..7bd2645 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -358,7 +358,8 @@ brw_upload_pull_constants(struct brw_context *brw,
GLbitfield brw_new_constbuf,
const struct gl_program *prog,
struct brw_stage_state *stage_state,
- const struct brw_stage_prog_data *prog_data);
+ const struct brw_stage_prog_data *prog_data,
+ bool dword_pitch);
/* gen7_vs_state.c */
void
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index bb23cc8..f50dd71 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -53,7 +53,8 @@ brw_upload_pull_constants(struct brw_context *brw,
GLbitfield brw_new_constbuf,
const struct gl_program *prog,
struct brw_stage_state *stage_state,
- const struct brw_stage_prog_data *prog_data)
+ const struct brw_stage_prog_data *prog_data,
+ bool dword_pitch)
{
unsigned i;
uint32_t surf_index = prog_data->binding_table.pull_constants_start;
@@ -93,7 +94,8 @@ brw_upload_pull_constants(struct brw_context *brw,
}
brw_create_constant_surface(brw, const_bo, const_offset, size,
- &stage_state->surf_offset[surf_index]);
+ &stage_state->surf_offset[surf_index],
+ dword_pitch);
drm_intel_bo_unreference(const_bo);
brw->ctx.NewDriverState |= brw_new_constbuf;
@@ -110,6 +112,7 @@ static void
brw_upload_vs_pull_constants(struct brw_context *brw)
{
struct brw_stage_state *stage_state = &brw->vs.base;
+ bool dword_pitch;
/* BRW_NEW_VERTEX_PROGRAM */
struct brw_vertex_program *vp =
@@ -118,9 +121,11 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
/* BRW_NEW_VS_PROG_DATA */
const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
+ dword_pitch = brw->vs.prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
+
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_VS_CONSTBUF, &vp->program.Base,
- stage_state, prog_data);
+ stage_state, prog_data, dword_pitch);
}
const struct brw_tracked_state brw_vs_pull_constants = {
@@ -140,13 +145,16 @@ brw_upload_vs_ubo_surfaces(struct brw_context *brw)
/* _NEW_PROGRAM */
struct gl_shader_program *prog =
ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX];
+ bool dword_pitch;
if (!prog)
return;
/* BRW_NEW_VS_PROG_DATA */
+ dword_pitch = brw->vs.prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX],
- &brw->vs.base, &brw->vs.prog_data->base.base);
+ &brw->vs.base, &brw->vs.prog_data->base.base,
+ dword_pitch);
}
const struct brw_tracked_state brw_vs_ubo_surfaces = {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 9c77593..e689fed 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -400,7 +400,8 @@ brw_create_constant_surface(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t offset,
uint32_t size,
- uint32_t *out_offset)
+ uint32_t *out_offset,
+ bool dword_pitch)
{
brw->vtbl.emit_buffer_surface_state(brw, out_offset, bo, offset,
BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
@@ -510,7 +511,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &fp->program.Base,
- stage_state, prog_data);
+ stage_state, prog_data, true);
}
const struct brw_tracked_state brw_wm_pull_constants = {
@@ -884,7 +885,8 @@ void
brw_upload_ubo_surfaces(struct brw_context *brw,
struct gl_shader *shader,
struct brw_stage_state *stage_state,
- struct brw_stage_prog_data *prog_data)
+ struct brw_stage_prog_data *prog_data,
+ bool dword_pitch)
{
struct gl_context *ctx = &brw->ctx;
@@ -911,7 +913,8 @@ brw_upload_ubo_surfaces(struct brw_context *brw,
*/
brw_create_constant_surface(brw, bo, binding->Offset,
bo->size - binding->Offset,
- &surf_offsets[i]);
+ &surf_offsets[i],
+ dword_pitch);
}
if (shader->NumUniformBlocks)
@@ -930,7 +933,7 @@ brw_upload_wm_ubo_surfaces(struct brw_context *brw)
/* BRW_NEW_FS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
- &brw->wm.base, &brw->wm.prog_data->base);
+ &brw->wm.base, &brw->wm.prog_data->base, true);
}
const struct brw_tracked_state brw_wm_ubo_surfaces = {
commit 494da6217beb65c9414ac5a98ef686817a2c70c3
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Dec 19 00:16:12 2015 +0000
Revert "i965/nir: Remove unused indirect handling"
This reverts commit 4acb394f459b58725a2059a911b6236703c44eb2.
As discussed with Jason on IRC. Earlier commit in the series, causes
regression, and "there's no point in having the others in there, if we
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