mesa: Changes to 'upstream-unstable'
VERSION | 2
bin/.cherry-ignore | 2
docs/relnotes/10.6.7.html | 3
docs/relnotes/10.6.8.html | 135 ++++++++++++++++++++++
src/gallium/auxiliary/gallivm/lp_bld_const.c | 2
src/gallium/auxiliary/gallivm/lp_bld_debug.cpp | 2
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 13 ++
src/gallium/drivers/nouveau/nv30/nv30_miptree.c | 29 ++--
src/gallium/drivers/nouveau/nv30/nv30_resource.h | 3
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 20 +++
src/gallium/drivers/nouveau/nv30/nv30_screen.h | 2
src/gallium/drivers/nouveau/nv30/nv30_transfer.c | 4
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 2
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2
src/gbm/backends/dri/gbm_dri.c | 18 ++
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 7 +
src/mesa/drivers/dri/i965/brw_vec4.cpp | 31 +++++
src/mesa/main/texcompress_bptc.c | 3
src/mesa/main/texcompress_fxt1.c | 3
src/mesa/main/texcompress_rgtc.c | 6
src/mesa/main/texcompress_s3tc.c | 9 -
src/mesa/main/uniform_query.cpp | 35 ++++-
src/mesa/main/uniforms.c | 72 +++++------
src/mesa/main/uniforms.h | 2
src/mesa/state_tracker/st_atom_texture.c | 4
src/mesa/state_tracker/st_format.c | 22 +--
28 files changed, 348 insertions(+), 89 deletions(-)
New commits:
commit 91c6302734574e91424a7ccb52b6368b712366cc
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sun Sep 20 11:05:07 2015 +0100
docs: add release notes for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
diff --git a/docs/relnotes/10.6.8.html b/docs/relnotes/10.6.8.html
new file mode 100644
index 0000000..b016260
--- /dev/null
+++ b/docs/relnotes/10.6.8.html
@@ -0,0 +1,135 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.6.8 Release Notes / September 20, 2015</h1>
+
+<p>
+Mesa 10.6.8 is a bug fix release which fixes bugs found since the 10.6.7 release.
+</p>
+<p>
+Mesa 10.6.8 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3. OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=90621";>Bug 90621</a> - Mesa fail to build from git</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91526";>Bug 91526</a> - World of Warcraft (on Wine) has UI corruption with nouveau</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91719";>Bug 91719</a> - [SNB,HSW,BYT] dEQP regressions associated with using NIR for vertex shaders</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alejandro Piñeiro (1):</p>
+<ul>
+ <li>i965/vec4: fill src_reg type using the constructor type parameter</li>
+</ul>
+
+<p>Antia Puentes (1):</p>
+<ul>
+ <li>i965/vec4: Fix saturation errors when coalescing registers</li>
+</ul>
+
+<p>Emil Velikov (2):</p>
+<ul>
+ <li>docs: add sha256 checksums for 10.6.7</li>
+ <li>cherry-ignore: add commit non applicable for 10.6</li>
+</ul>
+
+<p>Hans de Goede (4):</p>
+<ul>
+ <li>nv30: Fix creation of scanout buffers</li>
+ <li>nv30: Implement color resolve for msaa</li>
+ <li>nv30: Fix max width / height checks in nv30 sifm code</li>
+ <li>nv30: Disable msaa unless requested from the env by NV30_MAX_MSAA</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+ <li>mesa: Pass the type to _mesa_uniform_matrix as a glsl_base_type</li>
+ <li>mesa: Don't allow wrong type setters for matrix uniforms</li>
+</ul>
+
+<p>Ilia Mirkin (5):</p>
+<ul>
+ <li>st/mesa: don't fall back to 16F when 32F is requested</li>
+ <li>nvc0: always emit a full shader colormask</li>
+ <li>nvc0: remove BGRA4 format support</li>
+ <li>st/mesa: avoid integer overflows with buffers >= 512MB</li>
+ <li>nv50, nvc0: fix max texture buffer size to 128M elements</li>
+</ul>
+
+<p>Jason Ekstrand (1):</p>
+<ul>
+ <li>i965/vec4: Don't reswizzle hardware registers</li>
+</ul>
+
+<p>Jose Fonseca (1):</p>
+<ul>
+ <li>gallivm: Workaround LLVM PR23628.</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>i965: Momentarily pretend to support ARB_texture_stencil8 for blits.</li>
+</ul>
+
+<p>Oded Gabbay (1):</p>
+<ul>
+ <li>llvmpipe: convert double to long long instead of unsigned long long</li>
+</ul>
+
+<p>Ray Strode (1):</p>
+<ul>
+ <li>gbm: convert gbm bo format to fourcc format on dma-buf import</li>
+</ul>
+
+<p>Ulrich Weigand (1):</p>
+<ul>
+ <li>mesa: Fix texture compression on big-endian systems</li>
+</ul>
+
+<p>Vinson Lee (1):</p>
+<ul>
+ <li>gallivm: Do not use NoFramePointerElim with LLVM 3.7.</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit 9a4ebbe1ecee0cb1ee1062ba4b448a9c496c03fa
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sun Sep 20 11:05:23 2015 +0100
Update version to 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
diff --git a/VERSION b/VERSION
index 11ffa66..60660e0 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.6.7
+10.6.8
commit eb06d2b6496159a505c8d290e51b14ed2ba36718
Author: Alejandro Piñeiro <apinheiro@igalia.com>
Date: Tue Sep 1 17:02:20 2015 +0200
i965/vec4: fill src_reg type using the constructor type parameter
The src_reg constructor that received the glsl_type was using it
only to build the swizzle, but not to fill this->type as dst_reg
is doing.
This caused some type mismatch between movs and alu operations
on the NIR path, so copy propagation optimization was not applied
to remove unneeded movs if negate modifier was involved. This was
first detected on minus (negate+add) operations.
Shader DB results (taking into account only vec4):
total instructions in shared programs: 20019 -> 19934 (-0.42%)
instructions in affected programs: 2918 -> 2833 (-2.91%)
helped: 79
HURT: 0
GAINED: 0
LOST: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 4de86e1371b0d59a5b9a787b726be3d373024647)
Nominated-by: Christoph Brill <egore911@egore911.de>
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 729d081..aaf4e43 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -60,6 +60,8 @@ src_reg::src_reg(register_file file, int reg, const glsl_type *type)
this->swizzle = brw_swizzle_for_size(type->vector_elements);
else
this->swizzle = BRW_SWIZZLE_XYZW;
+ if (type)
+ this->type = brw_type_for_base_type(type);
}
/** Generic unset register constructor. */
commit 0fe894db48f96a4c8db72e83b30f6d4965ba5eeb
Author: Ulrich Weigand <uweigand@de.ibm.com>
Date: Tue Sep 15 15:23:26 2015 +0200
mesa: Fix texture compression on big-endian systems
Various pieces of code to create compressed textures will first
generate an uncompressed RGBA texture into a temporary buffer,
and then read from that buffer while creating the final compressed
texture in the requested format.
The code reading from the temporary buffer assumes the buffer is
formatted as an array of bytes in RGBA order. However, the buffer
is filled using a _mesa_texstore call with MESA_FORMAT_R8G8B8A8_UNORM
format -- this is defined as an array of *integers* holding the
RGBA values in packed format (least-significant to most-significant).
This means incorrect bytes are accessed on big-endian systems.
This patch fixes this by using the MESA_FORMAT_A8B8G8R8_UNORM format
instead on big-endian systems when filling the buffer. This fixes
about 100 piglit test case failures on s390x for me.
Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Tested-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "10.6" "11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@gmail.com>
(cherry picked from commit bd016a2601a741799bc76734deae0cb9ebcb2b8f)
diff --git a/src/mesa/main/texcompress_bptc.c b/src/mesa/main/texcompress_bptc.c
index a600180..f0f6553 100644
--- a/src/mesa/main/texcompress_bptc.c
+++ b/src/mesa/main/texcompress_bptc.c
@@ -1291,7 +1291,8 @@ _mesa_texstore_bptc_rgba_unorm(TEXSTORE_PARAMS)
tempImageSlices[0] = (GLubyte *) tempImage;
_mesa_texstore(ctx, dims,
baseInternalFormat,
- MESA_FORMAT_R8G8B8A8_UNORM,
+ _mesa_little_endian() ? MESA_FORMAT_R8G8B8A8_UNORM
+ : MESA_FORMAT_A8B8G8R8_UNORM,
rgbaRowStride, tempImageSlices,
srcWidth, srcHeight, srcDepth,
srcFormat, srcType, srcAddr,
diff --git a/src/mesa/main/texcompress_fxt1.c b/src/mesa/main/texcompress_fxt1.c
index d605e25..ae339e1 100644
--- a/src/mesa/main/texcompress_fxt1.c
+++ b/src/mesa/main/texcompress_fxt1.c
@@ -130,7 +130,8 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS)
tempImageSlices[0] = (GLubyte *) tempImage;
_mesa_texstore(ctx, dims,
baseInternalFormat,
- MESA_FORMAT_R8G8B8A8_UNORM,
+ _mesa_little_endian() ? MESA_FORMAT_R8G8B8A8_UNORM
+ : MESA_FORMAT_A8B8G8R8_UNORM,
rgbaRowStride, tempImageSlices,
srcWidth, srcHeight, srcDepth,
srcFormat, srcType, srcAddr,
diff --git a/src/mesa/main/texcompress_rgtc.c b/src/mesa/main/texcompress_rgtc.c
index 66de1f1..8cab7a5 100644
--- a/src/mesa/main/texcompress_rgtc.c
+++ b/src/mesa/main/texcompress_rgtc.c
@@ -196,9 +196,11 @@ _mesa_texstore_rg_rgtc2(TEXSTORE_PARAMS)
dstFormat == MESA_FORMAT_LA_LATC2_UNORM);
if (baseInternalFormat == GL_RG)
- tempFormat = MESA_FORMAT_R8G8_UNORM;
+ tempFormat = _mesa_little_endian() ? MESA_FORMAT_R8G8_UNORM
+ : MESA_FORMAT_G8R8_UNORM;
else
- tempFormat = MESA_FORMAT_L8A8_UNORM;
+ tempFormat = _mesa_little_endian() ? MESA_FORMAT_L8A8_UNORM
+ : MESA_FORMAT_A8L8_UNORM;
rgRowStride = 2 * srcWidth * sizeof(GLubyte);
tempImage = malloc(srcWidth * srcHeight * 2 * sizeof(GLubyte));
diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c
index 6cfe06a..7ddb0ed 100644
--- a/src/mesa/main/texcompress_s3tc.c
+++ b/src/mesa/main/texcompress_s3tc.c
@@ -198,7 +198,8 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS)
tempImageSlices[0] = (GLubyte *) tempImage;
_mesa_texstore(ctx, dims,
baseInternalFormat,
- MESA_FORMAT_R8G8B8A8_UNORM,
+ _mesa_little_endian() ? MESA_FORMAT_R8G8B8A8_UNORM
+ : MESA_FORMAT_A8B8G8R8_UNORM,
rgbaRowStride, tempImageSlices,
srcWidth, srcHeight, srcDepth,
srcFormat, srcType, srcAddr,
@@ -255,7 +256,8 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS)
tempImageSlices[0] = (GLubyte *) tempImage;
_mesa_texstore(ctx, dims,
baseInternalFormat,
- MESA_FORMAT_R8G8B8A8_UNORM,
+ _mesa_little_endian() ? MESA_FORMAT_R8G8B8A8_UNORM
+ : MESA_FORMAT_A8B8G8R8_UNORM,
rgbaRowStride, tempImageSlices,
srcWidth, srcHeight, srcDepth,
srcFormat, srcType, srcAddr,
@@ -311,7 +313,8 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS)
tempImageSlices[0] = (GLubyte *) tempImage;
_mesa_texstore(ctx, dims,
baseInternalFormat,
- MESA_FORMAT_R8G8B8A8_UNORM,
+ _mesa_little_endian() ? MESA_FORMAT_R8G8B8A8_UNORM
+ : MESA_FORMAT_A8B8G8R8_UNORM,
rgbaRowStride, tempImageSlices,
srcWidth, srcHeight, srcDepth,
srcFormat, srcType, srcAddr,
commit 7b583e05835b7c43fe94b580d2b6dcf1ec271cb6
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Tue Sep 15 19:39:25 2015 -0400
nv50, nvc0: fix max texture buffer size to 128M elements
This is what the hardware supports, there never was any sort of 64K
limit.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 7a275fcda8ffa3d69b7be6f356469f4af272a6ad)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index f455a7f..69c54cc 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -100,7 +100,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- return 65536;
+ return 128 * 1024 * 1024;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return 330;
case PIPE_CAP_MAX_RENDER_TARGETS:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 1ca997a..7375208 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -87,7 +87,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
return 31;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- return 65536;
+ return 128 * 1024 * 1024;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return 410;
case PIPE_CAP_MAX_RENDER_TARGETS:
commit 8fd7f10ae0583f8e01f0b9e8e1130113ca18945c
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Tue Sep 15 19:32:10 2015 -0400
st/mesa: avoid integer overflows with buffers >= 512MB
This fixes failures with the newly-submitted max-size texture buffer
piglit test for GPUs exposing >= 128M max texels.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
(cherry picked from commit eb081681df248750727a8a76436760d617b4a6a9)
diff --git a/src/mesa/state_tracker/st_atom_texture.c b/src/mesa/state_tracker/st_atom_texture.c
index a1c181c..a019c34 100644
--- a/src/mesa/state_tracker/st_atom_texture.c
+++ b/src/mesa/state_tracker/st_atom_texture.c
@@ -253,8 +253,8 @@ st_create_texture_sampler_view_from_stobj(struct pipe_context *pipe,
return NULL;
size = MIN2(stObj->pt->width0 - base, (unsigned)stObj->base.BufferSize);
- f = ((base * 8) / desc->block.bits) * desc->block.width;
- n = ((size * 8) / desc->block.bits) * desc->block.width;
+ f = (base / (desc->block.bits / 8)) * desc->block.width;
+ n = (size / (desc->block.bits / 8)) * desc->block.width;
if (!n)
return NULL;
templ.u.buf.first_element = f;
commit a9df9b1854081a933a86c74e173a82bfb29fbe92
Author: Ray Strode <rstrode@redhat.com>
Date: Fri Aug 28 14:50:21 2015 -0400
gbm: convert gbm bo format to fourcc format on dma-buf import
At the moment if a gbm buffer is imported and the gbm buffer
has an old-style GBM_BO_FORMAT format, the import will crash,
since it's passed directly to DRI functions that expect
a fourcc format (as provided by the newer GBM_FORMAT
definitions)
This commit addresses the problem in two ways:
1) it prevents invalid formats from leading to a crash by
returning EINVAL if the image couldn't be created
2) it translates GBM_BO_FORMAT formats into the comparable
GBM_FORMAT formats.
Reference: https://bugzilla.gnome.org/show_bug.cgi?id=753531
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
(cherry picked from commit 4bf151e66279da00655cec02aadb52c9c6583213)
diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index ccc3cc6..57cdeac 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -706,14 +706,30 @@ gbm_dri_bo_import(struct gbm_device *gbm,
{
struct gbm_import_fd_data *fd_data = buffer;
int stride = fd_data->stride, offset = 0;
+ int dri_format;
+
+ switch (fd_data->format) {
+ case GBM_BO_FORMAT_XRGB8888:
+ dri_format = GBM_FORMAT_XRGB8888;
+ break;
+ case GBM_BO_FORMAT_ARGB8888:
+ dri_format = GBM_FORMAT_ARGB8888;
+ break;
+ default:
+ dri_format = fd_data->format;
+ }
image = dri->image->createImageFromFds(dri->screen,
fd_data->width,
fd_data->height,
- fd_data->format,
+ dri_format,
&fd_data->fd, 1,
&stride, &offset,
NULL);
+ if (image == NULL) {
+ errno = EINVAL;
+ return NULL;
+ }
gbm_format = fd_data->format;
break;
}
commit a6714a9a0404e665f0efd15c48260267679c8c56
Author: Antia Puentes <apuentes@igalia.com>
Date: Wed Aug 5 15:57:33 2015 +0200
i965/vec4: Fix saturation errors when coalescing registers
If the register types do not match and the instruction
that contains the final destination is saturated, register
coalescing generated non-equivalent code.
This did not happen when using IR because types usually
matched, but it is visible in nir-vec4.
For example,
mov vgrf7:D vgrf2:D
mov.sat m4:F vgrf7:F
is coalesced to:
mov.sat m4:D vgrf2:D
The patch prevents coalescing in such scenario, unless the
instruction we want to coalesce into is a MOV (without type
conversion implied). In that case, the patch sets the register
types to the type of the final destination.
Shader-db results in HSW (only vec4 instructions shown):
total instructions in shared programs: 1754415 -> 1754416 (0.00%)
instructions in affected programs: 74 -> 75 (1.35%)
helped: 0
HURT: 1
GAINED: 0
LOST: 0
Only one extra instruction in one of the shaders, that comes from
eliminating a saturation error by preventing register coalesce.
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit 79f1a7ae28c37f77e08e550cd077959a2a1f8341)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 86e8287..729d081 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1049,6 +1049,17 @@ vec4_visitor::opt_register_coalesce()
}
}
+ /* This doesn't handle saturation on the instruction we
+ * want to coalesce away if the register types do not match.
+ * But if scan_inst is a non type-converting 'mov', we can fix
+ * the types later.
+ */
+ if (inst->saturate &&
+ inst->dst.type != scan_inst->dst.type &&
+ !(scan_inst->opcode == BRW_OPCODE_MOV &&
+ scan_inst->dst.type == scan_inst->src[0].type))
+ break;
+
/* If we can't handle the swizzle, bail. */
if (!scan_inst->can_reswizzle(inst->dst.writemask,
inst->src[0].swizzle,
@@ -1124,6 +1135,16 @@ vec4_visitor::opt_register_coalesce()
scan_inst->dst.file = inst->dst.file;
scan_inst->dst.reg = inst->dst.reg;
scan_inst->dst.reg_offset = inst->dst.reg_offset;
+ if (inst->saturate &&
+ inst->dst.type != scan_inst->dst.type) {
+ /* If we have reached this point, scan_inst is a non
+ * type-converting 'mov' and we can modify its register types
+ * to match the ones in inst. Otherwise, we could have an
+ * incorrect saturation result.
+ */
+ scan_inst->dst.type = inst->dst.type;
+ scan_inst->src[0].type = inst->src[0].type;
+ }
scan_inst->saturate |= inst->saturate;
}
scan_inst = (vec4_instruction *)scan_inst->next;
commit 022892323d78311e59325991207839e70549f515
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Sep 10 16:19:42 2015 -0700
i965/vec4: Don't reswizzle hardware registers
Cc: "11.0 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91719
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 1037e0a84f61f4b1815093bcfd548d4b58ca106f)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index e9681b7..86e8287 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -938,6 +938,14 @@ vec4_instruction::can_reswizzle(int dst_writemask,
if (mlen > 0)
return false;
+ /* We can't use swizzles on the accumulator and that's really the only
+ * HW_REG we would care to reswizzle so just disallow them all.
+ */
+ for (int i = 0; i < 3; i++) {
+ if (src[i].file == HW_REG)
+ return false;
+ }
+
return true;
}
commit 34bfebda14cc8474fa5d498d1ed03f9a3d4e733a
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Wed Sep 9 21:50:03 2015 -0400
nvc0: remove BGRA4 format support
Something is wrong with the support somewhere. I couldn't get the blob
driver to use it either, although it happily used RGB5_A1.
teximage-colors works, but WoW seems to fail in the menus for drawing
text.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 342e68dc60eebb20ac1be9f47800ee9e604354f0)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 0f86ba1..88d8e07 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -203,8 +203,10 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
F3B(B5G6R5_UNORM, B5G6R5_UNORM, C2, C1, C0, xx, UNORM, 5_6_5, TD),
C4B(B5G5R5A1_UNORM, BGR5_A1_UNORM, C2, C1, C0, C3, UNORM, 5_5_5_1, TD),
F3B(B5G5R5X1_UNORM, BGR5_X1_UNORM, C2, C1, C0, xx, UNORM, 5_5_5_1, TD),
+#if NOUVEAU_DRIVER != 0xc0
C4B(B4G4R4A4_UNORM, NONE, C2, C1, C0, C3, UNORM, 4_4_4_4, T),
F3B(B4G4R4X4_UNORM, NONE, C2, C1, C0, xx, UNORM, 4_4_4_4, T),
+#endif
F3B(R9G9B9E5_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 9_9_9_E5, T),
C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2,
commit cb2209e9efa8f3fac4c27ff98fbaba19ec551191
Author: Hans de Goede <hdegoede@redhat.com>
Date: Wed Sep 9 15:52:09 2015 +0200
nv30: Disable msaa unless requested from the env by NV30_MAX_MSAA
Some modern apps try to use msaa without keeping in mind the
restrictions on videomem of older cards. Resulting in dmesg saying:
[ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
[ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
[ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
Because we are running out of video memory, after which the program
using the msaa visual freezes, and eventually the entire system freezes.
To work around this we do not allow msaa visauls by default and allow
the user to override this via NV30_MAX_MSAA.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[imirkin: move env var lookup to screen so that it's only done once]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3e9df0e3af7a8a84147ae48f588e9c435bf65b98)
Signed-off-by: Emil Velikov <emil.velikov@collabora.co.uk>
Conflicts:
src/gallium/drivers/nouveau/nv30/nv30_screen.c
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 025cad2..fbe4b3a 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -310,8 +310,9 @@ nv30_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
- if (sample_count > 4)
+ if (sample_count > nv30_screen(pscreen)->max_sample_count)
return FALSE;
+
if (!(0x00000017 & (1 << sample_count)))
return FALSE;
@@ -441,6 +442,23 @@ nv30_screen_create(struct nouveau_device *dev)
return NULL;
}
+ /*
+ * Some modern apps try to use msaa without keeping in mind the
+ * restrictions on videomem of older cards. Resulting in dmesg saying:
+ * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
+ * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
+ * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
+ *
+ * Because we are running out of video memory, after which the program
+ * using the msaa visual freezes, and eventually the entire system freezes.
+ *
+ * To work around this we do not allow msaa visauls by default and allow
+ * the user to override this via NV30_MAX_MSAA.
+ */
+ screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
+ if (screen->max_sample_count > 4)
+ screen->max_sample_count = 4;
+
pscreen = &screen->base.base;
pscreen->destroy = nv30_screen_destroy;
pscreen->get_param = nv30_screen_get_param;
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.h b/src/gallium/drivers/nouveau/nv30/nv30_screen.h
index 3f2e47f..af3dd03 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.h
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.h
@@ -38,6 +38,8 @@ struct nv30_screen {
/*XXX: nvfx state */
struct nouveau_heap *vp_exec_heap;
struct nouveau_heap *vp_data_heap;
+
+ unsigned max_sample_count;
};
static INLINE struct nv30_screen *
commit 2ecfc4e38d6804f28dce8a347205f793ab7ce149
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Sep 6 04:51:29 2015 -0400
nvc0: always emit a full shader colormask
Indications are that if the colormask indicates a single bit set on
fermi, that value will always be read from $r0 instead of a potentially
higher register (if e.g. green is set). Not to upset the counting logic,
always set the header up with a full color mask for each RT. Such a
situation can basically only ever happen with generated blit shaders.
Fixes the following piglit on Fermi (Kepler is unaffected):
fbo-stencil blit GL_DEPTH32F_STENCIL8
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 39df725f731f75f488c75a4910169beb352213fb)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 4a47cb2..b116f40 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -459,7 +459,7 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
for (i = 0; i < info->numOutputs; ++i) {
if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
- fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
+ fp->hdr[18] |= 0xf << info->out[i].slot[0];
}
fp->fp.early_z = info->prop.fp.earlyFragTests;
commit 3fa83e99de2a135e3093cb5f60b7e4bbb906d049
Author: Hans de Goede <hdegoede@redhat.com>
Date: Mon Sep 7 21:50:48 2015 +0200
nv30: Fix max width / height checks in nv30 sifm code
The sifm object has a limit of 1024x1024 for its input size and 2048x2048
for its output. The code checking this was trying to be clever resulting
in it seeing a surface of e.g 1024x256 being outside of the input size
limit.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 87073c69f3e253044bc235f34917aaa89041a63c)
Signed-off-by: Emil Velikov <emil.velikov@collabora.co.uk>
Conflicts:
src/gallium/drivers/nouveau/nv30/nv30_transfer.c
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
index 99bc099..76a5e5b 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
@@ -371,7 +371,7 @@ nv30_transfer_rect_blit(XFER_ARGS)
static boolean
nv30_transfer_sifm(XFER_ARGS)
{
- if (!src->pitch || (src->w | src->h) > 1024 || src->w < 2 || src->h < 2)
+ if (!src->pitch || src->w > 1024 || src->h > 1024 || src->w < 2 || src->h < 2)
return FALSE;
if (src->d > 1 || dst->d > 1)
@@ -381,7 +381,7 @@ nv30_transfer_sifm(XFER_ARGS)
return FALSE;
if (!dst->pitch) {
- if ((dst->w | dst->h) > 2048 || dst->w < 2 || dst->h < 2)
+ if (dst->w > 2048 || dst->h > 2048 || dst->w < 2 || dst->h < 2)
return FALSE;
} else {
if (dst->domain != NOUVEAU_BO_VRAM)
commit 0869fefe1a83c4d8aef688be8c77ea3fd9026e26
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun Sep 6 11:29:00 2015 -0400
st/mesa: don't fall back to 16F when 32F is requested
Nothing in the spec allows for the reduced precision, and this also
fixes st_QuerySamplesForFormat for nv50, which does not allow MS8 on
RGBA32F. Now this will be respected instead of reporting MS8 as
supported with an assumption that the format used will be RGBA16F.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit e40f32d5626c87d9e77bbc261df3648cd54bd066)
diff --git a/src/mesa/state_tracker/st_format.c b/src/mesa/state_tracker/st_format.c
index db7b5b7..f582166 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -1270,46 +1270,40 @@ static const struct format_mapping format_map[] = {
/* 32-bit float formats */
{
{ GL_RGBA32F_ARB, 0 },
- { PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ { PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_RGB32F_ARB, 0 },
{ PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32X32_FLOAT,
- PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_LUMINANCE_ALPHA32F_ARB, 0 },
- { PIPE_FORMAT_L32A32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT,
- PIPE_FORMAT_L16A16_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ { PIPE_FORMAT_L32A32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_ALPHA32F_ARB, 0 },
{ PIPE_FORMAT_A32_FLOAT, PIPE_FORMAT_L32A32_FLOAT,
- PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_A16_FLOAT,
- PIPE_FORMAT_L16A16_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_INTENSITY32F_ARB, 0 },
{ PIPE_FORMAT_I32_FLOAT, PIPE_FORMAT_L32A32_FLOAT,
- PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_I16_FLOAT,
- PIPE_FORMAT_L16A16_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_LUMINANCE32F_ARB, 0 },
{ PIPE_FORMAT_L32_FLOAT, PIPE_FORMAT_L32A32_FLOAT,
- PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_L16_FLOAT,
- PIPE_FORMAT_L16A16_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_R32F, 0 },
{ PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT,
- PIPE_FORMAT_R32G32B32A32_FLOAT, PIPE_FORMAT_R16_FLOAT,
- PIPE_FORMAT_R16G16_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
{
{ GL_RG32F, 0 },
- { PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT,
- PIPE_FORMAT_R16G16_FLOAT, PIPE_FORMAT_R16G16B16A16_FLOAT, 0 }
+ { PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT, 0 }
},
/* R, RG formats */
commit cefbc3f7c1847d1d816baf4666b35228c9f3bfcc
Author: Oded Gabbay <oded.gabbay@gmail.com>
Date: Thu Sep 3 19:00:26 2015 +0300
llvmpipe: convert double to long long instead of unsigned long long
round(val*dscale) produces a double result, as val and dscale are double.
However, LLVMConstInt receives unsigned long long, so there is an
implicit conversion from double to unsigned long long.
This is an undefined behavior. Therefore, we need to first explicitly
convert the round result to long long, and then let the compiler handle
conversion from that to unsigned long long.
This bug manifests itself in POWER, where all IMM values of -1 are being
converted to 0 implicitly, causing a wrong LLVM IR output.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 4f2290d1612569686284609059d29a85c9de67cf)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_const.c b/src/gallium/auxiliary/gallivm/lp_bld_const.c
index 0f5a8f8..9cd7c55 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_const.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_const.c
@@ -311,7 +311,7 @@ lp_build_const_elem(struct gallivm_state *gallivm,
else {
double dscale = lp_const_scale(type);
- elem = LLVMConstInt(elem_type, round(val*dscale), 0);
+ elem = LLVMConstInt(elem_type, (long long) round(val*dscale), 0);
}
return elem;
commit 3cbe492fb45b2fa1a06fba6a71fb50367e06ff8a
Author: Hans de Goede <hdegoede@redhat.com>
Date: Thu Sep 3 12:38:01 2015 +0200
nv30: Implement color resolve for msaa
Note this is not ideal. Since the sifm can only do source sizes upto
1024x1024 we end up using the blitter on nv4x, which is not that fast.
And on nv3x we end up using the cpu which is really slow.
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 3c6c4d4f298ec81fe57992790a68aaab2e573519)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_miptree.c b/src/gallium/drivers/nouveau/nv30/nv30_miptree.c
index 84b113d..c07c7b1 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_miptree.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_miptree.c
@@ -145,21 +145,18 @@ nv30_resource_copy_region(struct pipe_context *pipe,
nv30_transfer_rect(nv30, NEAREST, &src, &dst);
}
-void
-nv30_resource_resolve(struct pipe_context *pipe,
- const struct pipe_resolve_info *info)
+static void
+nv30_resource_resolve(struct nv30_context *nv30,
+ const struct pipe_blit_info *info)
{
-#if 0
- struct nv30_context *nv30 = nv30_context(pipe);
struct nv30_rect src, dst;
- define_rect(info->src.res, 0, 0, info->src.x0, info->src.y0,
- info->src.x1 - info->src.x0, info->src.y1 - info->src.y0, &src);
- define_rect(info->dst.res, info->dst.level, 0, info->dst.x0, info->dst.y0,
- info->dst.x1 - info->dst.x0, info->dst.y1 - info->dst.y0, &dst);
+ define_rect(info->src.resource, 0, info->src.box.z, info->src.box.x,
+ info->src.box.y, info->src.box.width, info->src.box.height, &src);
+ define_rect(info->dst.resource, 0, info->dst.box.z, info->dst.box.x,
+ info->dst.box.y, info->dst.box.width, info->dst.box.height, &dst);
nv30_transfer_rect(nv30, BILINEAR, &src, &dst);
-#endif
}
void
@@ -173,7 +170,7 @@ nv30_blit(struct pipe_context *pipe,
info.dst.resource->nr_samples <= 1 &&
!util_format_is_depth_or_stencil(info.src.resource->format) &&
!util_format_is_pure_integer(info.src.resource->format)) {
- debug_printf("nv30: color resolve unimplemented\n");
+ nv30_resource_resolve(nv30, blit_info);
return;
}
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_resource.h b/src/gallium/drivers/nouveau/nv30/nv30_resource.h
index 1981c8d..5096ff2 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_resource.h
+++ b/src/gallium/drivers/nouveau/nv30/nv30_resource.h
@@ -66,9 +66,6 @@ nv30_resource_copy_region(struct pipe_context *pipe,
const struct pipe_box *src_box);
void
-nv30_resource_resolve(struct pipe_context *, const struct pipe_resolve_info *);
-
-void
nv30_blit(struct pipe_context *pipe,
const struct pipe_blit_info *blit_info);
commit 1f4ff00356897b120bee73d6a7cdbb5157163e92
Author: Hans de Goede <hdegoede@redhat.com>
Date: Wed Aug 12 13:39:42 2015 +0200
nv30: Fix creation of scanout buffers
Scanout buffers on nv30 must always be non-swizzled and have special
width alignment constraints.
These constrains have been taken from the xf86-video-nouveau
src/nv_accel_common.c: nouveau_allocate_surface() function.
nouveau_allocate_surface() applies these width constraints only when a
tiled attribute is set, which it sets for all surfaces allocated via
dri, and this "tiling" is not the same as swizzling, scanout surfaces
must be linear / have a uniform_pitch or only complete garbage is shown.
This commit fixes dri3 on nv30 showing a garbled display, with dri3 the
scanout buffers are allocated by mesa, rather then by the ddx, and the
wrong stride of these buffers was causing the garbled display.
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 3329703eb116a7ad73bc694356b43e014532240b)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_miptree.c b/src/gallium/drivers/nouveau/nv30/nv30_miptree.c
index 1a4b892..84b113d 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_miptree.c
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