mesa: Changes to 'upstream-unstable'
VERSION | 2
docs/relnotes/10.6.4.html | 3
docs/relnotes/10.6.5.html | 123 ++++++++++
include/pci_ids/radeonsi_pci_ids.h | 1
src/egl/drivers/dri2/platform_x11.c | 20 +
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 14 -
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 14 -
src/gallium/drivers/r600/evergreen_state.c | 2
src/gallium/drivers/r600/r600_state.c | 2
src/gallium/drivers/r600/r600_state_common.c | 5
src/gallium/drivers/radeonsi/si_state.c | 2
src/gallium/drivers/vc4/Makefile.am | 1
src/glsl/ast_function.cpp | 9
src/glsl/ast_to_hir.cpp | 9
src/glx/glxext.c | 3
src/mesa/drivers/common/meta_copy_image.c | 4
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 2
src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c | 1
src/mesa/drivers/dri/nouveau/nv04_render.c | 1
src/mesa/main/formats.c | 23 +
src/mesa/main/formats.h | 5
src/mesa/main/glformats.c | 14 -
23 files changed, 220 insertions(+), 52 deletions(-)
New commits:
commit a43b3dd99bd4c114d0f3e90f4fd4792164fe7539
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Aug 22 10:20:54 2015 +0100
docs: add release notes for 10.6.5
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
diff --git a/docs/relnotes/10.6.5.html b/docs/relnotes/10.6.5.html
new file mode 100644
index 0000000..3ccf2ec
--- /dev/null
+++ b/docs/relnotes/10.6.5.html
@@ -0,0 +1,123 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.6.5 Release Notes / August 22, 2015</h1>
+
+<p>
+Mesa 10.6.5 is a bug fix release which fixes bugs found since the 10.6.4 release.
+</p>
+<p>
+Mesa 10.6.5 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3. OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85252";>Bug 85252</a> - Segfault in compiler while processing ternary operator with void arguments</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91570";>Bug 91570</a> - Upgrading mesa to 10.6 causes segfault in OpenGL applications with GeForce4 MX 440 / AGP 8X</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91610";>Bug 91610</a> - [BSW] GPU hang for spec.shaders.point-vertex-id gl_instanceid divisor</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Adam Jackson (1):</p>
+<ul>
+ <li>glx: Fix __glXWireToEvent for BufferSwapComplete</li>
+</ul>
+
+<p>Alex Deucher (2):</p>
+<ul>
+ <li>radeonsi: add new OLAND pci id</li>
+ <li>radeonsi: properly set the raster_config for KV</li>
+</ul>
+
+<p>Emil Velikov (4):</p>
+<ul>
+ <li>docs: add sha256 checksums for 10.6.4</li>
+ <li>vc4: add missing nir include, to fix the build</li>
+ <li>Revert "radeonsi: properly set the raster_config for KV"</li>
+ <li>Update version to 10.6.5</li>
+</ul>
+
+<p>Frank Binns (1):</p>
+<ul>
+ <li>egl/x11: don't abort when creating a DRI2 drawable fails</li>
+</ul>
+
+<p>Ilia Mirkin (3):</p>
+<ul>
+ <li>nouveau: no need to do tnl wakeup, state updates are always hooked up</li>
+ <li>gm107/ir: indirect handle goes first on maxwell also</li>
+ <li>nv50,nvc0: take level into account when doing eng2d multi-layer blits</li>
+</ul>
+
+<p>Jason Ekstrand (4):</p>
+<ul>
+ <li>meta/copy_image: Stash off the scissor</li>
+ <li>mesa/formats: Only do byteswapping for packed formats</li>
+ <li>mesa/formats: Fix swizzle flipping for big-endian targets</li>
+ <li>mesa/formats: Don't flip channels of null array formats</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+ <li>radeonsi: fix polygon offset scale</li>
+ <li>r600g: fix polygon offset scale</li>
+ <li>r600g: allow setting geometry shader sampler states</li>
+</ul>
+
+<p>Neil Roberts (1):</p>
+<ul>
+ <li>i965/bdw: Fix setting the instancing state for the SGVS element</li>
+</ul>
+
+<p>Oded Gabbay (2):</p>
+<ul>
+ <li>mesa: clear existing swizzle info before bitwise-OR</li>
+ <li>mesa/formats: don't byteswap when building array formats</li>
+</ul>
+
+<p>Renaud Gaubert (1):</p>
+<ul>
+ <li>glsl: avoid compiler's segfault when processing operators with void arguments</li>
+</ul>
+
+
+</div>
+</body>
+</html>
commit b9df15bef99c4c7a949070a8e065b0884645bc01
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Aug 22 10:15:00 2015 +0100
Update version to 10.6.5
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
diff --git a/VERSION b/VERSION
index 827886a..cac93e5 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.6.4
+10.6.5
commit 76cc235e2b5605b9a9e93855c38e12cd19929acd
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Sat Aug 22 10:12:52 2015 +0100
Revert "radeonsi: properly set the raster_config for KV"
This reverts commit 20bb0a771dded700ba1b213256bf47dfedbdfd77.
Requested-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fb6dba2..4d38a32 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3023,7 +3023,6 @@ si_write_harvested_raster_configs(struct si_context *sctx,
void si_init_config(struct si_context *sctx)
{
- unsigned num_rb = sctx->screen->b.info.r600_num_backends;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -3072,17 +3071,14 @@ void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
break;
case CHIP_KAVERI:
- if (num_rb > 1)
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002);
- else
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
- break;
+ /* XXX todo */
case CHIP_KABINI:
+ /* XXX todo */
case CHIP_MULLINS:
+ /* XXX todo */
default:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
break;
}
} else {
commit 4a2a49040e6891355a80b582932c5a3cffaa3c16
Author: Renaud Gaubert <renaud@lse.epita.fr>
Date: Sat Jul 11 19:38:10 2015 +0200
glsl: avoid compiler's segfault when processing operators with void arguments
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignment of a void variable
which will be optimized out (the assignment) during the optimization
pass.
This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.
Thus preventing to dereference NULL in the following cases:
* binary operator
* unary operators
* ternary operator
* comparison operators (except equal and nequal operator)
Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252
Signed-off-by: Renaud Gaubert <renaud@lse.epita.fr>
Reviewed-by: Gabriel Laskar <gabriel@lse.epita.fr>
Reviewed-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
(cherry picked from commit 7b9ebf879b6f35038996805a641667f00d93c4b7)
Nominated-by: Mark Janes <mark.a.janes@intel.com>
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 7583613..8d2c801 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -1773,7 +1773,14 @@ ast_function_expression::hir(exec_list *instructions,
/* an error has already been emitted */
value = ir_rvalue::error_value(ctx);
} else {
- value = generate_call(instructions, sig, &actual_parameters, state);
+ value = generate_call(instructions, sig, &actual_parameters, state);
+ if (!value) {
+ ir_variable *const tmp = new(ctx) ir_variable(glsl_type::void_type,
+ "void_var",
+ ir_var_temporary);
+ instructions->push_tail(tmp);
+ value = new(ctx) ir_dereference_variable(tmp);
+ }
}
return value;
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index a0154f1..05d00d8 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1270,7 +1270,14 @@ ast_expression::do_hir(exec_list *instructions,
* applied to one operand that can make them match, in which
* case this conversion is done."
*/
- if ((!apply_implicit_conversion(op[0]->type, op[1], state)
+
+ if (op[0]->type == glsl_type::void_type || op[1]->type == glsl_type::void_type) {
+ _mesa_glsl_error(& loc, state, "`%s': wrong operand types: "
+ "no operation `%1$s' exists that takes a left-hand "
+ "operand of type 'void' or a right operand of type "
+ "'void'", (this->oper == ast_equal) ? "==" : "!=");
+ error_emitted = true;
+ } else if ((!apply_implicit_conversion(op[0]->type, op[1], state)
&& !apply_implicit_conversion(op[1]->type, op[0], state))
|| (op[0]->type != op[1]->type)) {
_mesa_glsl_error(& loc, state, "operands of `%s' must have the same "
commit e9ab083702fb6be6444224074632b0d36e6a16da
Author: Neil Roberts <neil@linux.intel.com>
Date: Mon Jul 13 18:01:13 2015 +0100
i965/bdw: Fix setting the instancing state for the SGVS element
When gl_VertexID or gl_InstanceID is used a 3DSTATE_VF_SGVS
instruction is sent to create a sort of element to store the generated
values. The last instruction in this chunk of code looks like it was
trying to set the instancing state for the element using the
3DSTATE_VF_INSTANCING instruction. However it was sending
brw->vb.nr_buffers instead of the element index. This instruction is
supposed to take an element index and that is how it is used further
down in the function so the previous code looks wrong. Perhaps
previously the number of buffers coincidentally matched the number of
enabled elements so the value was generally correct anyway. In a
subsequent patch I want to change a bit how it chooses the SGVS
element index so this needs to be fixed.
v2 [by Ben]
Remove stable 10.5 stable tag (it's too late now)
Commit update as follows:
The number of vertex buffers emitted is always <= the number of vertex elements.
To maximize reuse (actually, to minimize relocations - according to the code
comments), a vertex buffer is only emitted once, even when we setup multiple
components (3DSTATE_VERTEX_ELEMENT) from that buffer. This meant that the
previous code would use the wrong indexed element for these reuse cases. This
patch by itself prevents hangs on BSW in the linked bug. It doesn't make the
test pass, the remaining patches are needed for that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91610
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c03247bae010dfd81a08572a32067e9ea8637f63)
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 1af90ec..f7d9952 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -74,7 +74,7 @@ gen8_emit_vertices(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
- OUT_BATCH(brw->vb.nr_buffers | GEN8_VF_INSTANCING_ENABLE);
+ OUT_BATCH(vue | GEN8_VF_INSTANCING_ENABLE);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
commit e57c526b8705d06f305b3d758edd0312316650a1
Author: Adam Jackson <ajax@redhat.com>
Date: Fri Jul 31 11:32:58 2015 -0400
glx: Fix __glXWireToEvent for BufferSwapComplete
In the DRI2 path this event is magically synthesized from the
corresponding DRI2 event, but with Present, the server sends us the
event itself. The DRI2 path fills in the serial number, send_event, and
display fields of the XEvent struct that the app sees, but the Present
path did not.
This is likely related to a class of crashes seen in gtk/clutter apps:
https://bugzilla.redhat.com/attachment.cgi?id=1032631
Note that the crashing instruction is looking up the lock_fns slot in
the Display *, and %rdi (holding the Display *) is 0x1.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 8f7ebcb6fad53ea6d2f80fc5b7a046db07690032)
diff --git a/src/glx/glxext.c b/src/glx/glxext.c
index fdc24d4..dc87fb9 100644
--- a/src/glx/glxext.c
+++ b/src/glx/glxext.c
@@ -138,6 +138,9 @@ __glXWireToEvent(Display *dpy, XEvent *event, xEvent *wire)
if (!glxDraw)
return False;
+ aevent->serial = _XSetLastRequestRead(dpy, (xGenericReply *) wire);
+ aevent->send_event = (awire->type & 0x80) != 0;
+ aevent->display = dpy;
aevent->event_type = awire->event_type;
aevent->drawable = glxDraw->xDrawable;
aevent->ust = ((CARD64)awire->ust_hi << 32) | awire->ust_lo;
commit 69649ea637c0729b72969b1f466d86708b95bccc
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat Aug 15 22:05:15 2015 -0400
nv50,nvc0: take level into account when doing eng2d multi-layer blits
This fixes arb_get_texture_sub_image-get, and any situation where the 2d
engine was being used for multi-layer blits to a non-0 level.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 2514c78fba507ca8ab94d2e6de553b8b20d653d2)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index dc9852d..8c9176f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -1387,18 +1387,24 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
PUSH_DATA (push, info->dst.box.z + i);
} else {
const unsigned z = info->dst.box.z + i;
+ const uint64_t address = dst->base.address +
+ dst->level[info->dst.level].offset +
+ z * dst->layer_stride;
BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
- PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
+ PUSH_DATAh(push, address);
+ PUSH_DATA (push, address);
}
if (src->layout_3d) {
/* not possible because of depth tiling */
assert(0);
} else {
const unsigned z = info->src.box.z + i;
+ const uint64_t address = src->base.address +
+ src->level[info->src.level].offset +
+ z * src->layer_stride;
BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, src->base.address + z * src->layer_stride);
- PUSH_DATA (push, src->base.address + z * src->layer_stride);
+ PUSH_DATAh(push, address);
+ PUSH_DATA (push, address);
}
BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
PUSH_DATA (push, srcy >> 32);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index ac4dd25..44fe1b0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -1336,18 +1336,24 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
PUSH_DATA (push, info->dst.box.z + i);
} else {
const unsigned z = info->dst.box.z + i;
+ const uint64_t address = dst->base.address +
+ dst->level[info->dst.level].offset +
+ z * dst->layer_stride;
BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
- PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
+ PUSH_DATAh(push, address);
+ PUSH_DATA (push, address);
}
if (src->layout_3d) {
/* not possible because of depth tiling */
assert(0);
} else {
const unsigned z = info->src.box.z + i;
+ const uint64_t address = src->base.address +
+ src->level[info->src.level].offset +
+ z * src->layer_stride;
BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, src->base.address + z * src->layer_stride);
- PUSH_DATA (push, src->base.address + z * src->layer_stride);
+ PUSH_DATAh(push, address);
+ PUSH_DATA (push, address);
}
BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
PUSH_DATA (push, srcy >> 32);
commit 0a831196665f8a9c2c5001f9c1890e073bac9f14
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Fri Aug 14 14:10:36 2015 -0400
gm107/ir: indirect handle goes first on maxwell also
Fixes fs-simple-texture-size.shader_test
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit b346a84e270a50f0a8f1a6e474a51da04dd72f0e)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index e71fa11..3fd19a9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -987,14 +987,10 @@ NVC0LoweringPass::handleTXQ(TexInstruction *txq)
txq->tex.r = 0xff;
txq->tex.s = 0x1f;
- if (chipset < NVISA_GM107_CHIPSET) {
- txq->setIndirectR(NULL);
- txq->moveSources(0, 1);
- txq->setSrc(0, hnd);
- txq->tex.rIndirectSrc = 0;
- } else {
- txq->setIndirectR(hnd);
- }
+ txq->setIndirectR(NULL);
+ txq->moveSources(0, 1);
+ txq->setSrc(0, hnd);
+ txq->tex.rIndirectSrc = 0;
}
return true;
commit 20bb0a771dded700ba1b213256bf47dfedbdfd77
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Wed Jun 10 11:39:30 2015 -0400
radeonsi: properly set the raster_config for KV
This enables the second RB on asics that support it which
should boost performance.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 649975e7162cc4ee0586ee76d24321cd7250581f)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 4d38a32..fb6dba2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3023,6 +3023,7 @@ si_write_harvested_raster_configs(struct si_context *sctx,
void si_init_config(struct si_context *sctx)
{
+ unsigned num_rb = sctx->screen->b.info.r600_num_backends;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -3071,14 +3072,17 @@ void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
break;
case CHIP_KAVERI:
- /* XXX todo */
+ if (num_rb > 1)
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002);
+ else
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ break;
case CHIP_KABINI:
- /* XXX todo */
case CHIP_MULLINS:
- /* XXX todo */
default:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
break;
}
} else {
commit 16c65ec37f5554041fa3dd8238d435041ac38526
Author: Frank Binns <frank.binns@imgtec.com>
Date: Tue Aug 4 14:32:45 2015 +0100
egl/x11: don't abort when creating a DRI2 drawable fails
When calling either eglCreateWindowSurface or eglCreatePixmapSurface it
was possible for an application to be aborted as a result of it failing
to create a DRI2 drawable on the server. This could happen due to an
application passing in an invalid native drawable handle, for example.
v2: Handle the case where an error has been set on the connection
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 9a4eae61c24858d69d731d63b141d2acaed40d69)
diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/platform_x11.c
index 809974b..66342c1 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -273,7 +273,25 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay *disp, EGLint type,
}
if (dri2_dpy->dri2) {
- xcb_dri2_create_drawable (dri2_dpy->conn, dri2_surf->drawable);
+ xcb_void_cookie_t cookie;
+ int conn_error;
+
+ cookie = xcb_dri2_create_drawable_checked(dri2_dpy->conn,
+ dri2_surf->drawable);
+ error = xcb_request_check(dri2_dpy->conn, cookie);
+ conn_error = xcb_connection_has_error(dri2_dpy->conn);
+ if (conn_error || error != NULL) {
+ if (type == EGL_PBUFFER_BIT || conn_error || error->error_code == BadAlloc)
+ _eglError(EGL_BAD_ALLOC, "xcb_dri2_create_drawable_checked");
+ else if (type == EGL_WINDOW_BIT)
+ _eglError(EGL_BAD_NATIVE_WINDOW,
+ "xcb_dri2_create_drawable_checked");
+ else
+ _eglError(EGL_BAD_NATIVE_PIXMAP,
+ "xcb_dri2_create_drawable_checked");
+ free(error);
+ goto cleanup_dri_drawable;
+ }
} else {
if (type == EGL_PBUFFER_BIT) {
dri2_surf->depth = _eglGetConfigKey(conf, EGL_BUFFER_SIZE);
commit 23bbe418fcce69447fb425012e9ac8d149fb5455
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Aug 11 21:37:59 2015 +0200
r600g: allow setting geometry shader sampler states
We were ignoring them. This is both hilarious and sad.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 8c0b943e87b48e7359230825cc06fbdd059a9e58)
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 13dc9ee..baba849 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -399,11 +399,6 @@ static void r600_bind_sampler_states(struct pipe_context *pipe,
assert(start == 0); /* XXX fix below */
- if (shader != PIPE_SHADER_VERTEX &&
- shader != PIPE_SHADER_FRAGMENT) {
- return;
- }
-
for (i = 0; i < count; i++) {
struct r600_pipe_sampler_state *rstate = rstates[i];
commit f40be8799671e1195274ae846cd329d7a71c80bb
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Aug 11 22:36:51 2015 +0200
r600g: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
(untested, ported from radeonsi)
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d335aad11b208bcdcc75a99d4b6c5fc8b69ce368)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 3256332..a7c705d 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -485,7 +485,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
/* offset */
rs->offset_units = state->offset_units;
- rs->offset_scale = state->offset_scale * 12.0f;
+ rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
if (state->point_size_per_vertex) {
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 960dfce..254201e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -473,7 +473,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
/* offset */
rs->offset_units = state->offset_units;
- rs->offset_scale = state->offset_scale * 12.0f;
+ rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
if (state->point_size_per_vertex) {
commit e7e38e11c3ec7ae03d46451ce45b7226a56ac25c
Author: Marek Olšák <marek.olsak@amd.com>
Date: Tue Aug 11 22:36:51 2015 +0200
radeonsi: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Fixes piglit: gl-1.4-polygon-offset (formerly a glean test)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit bfac8ba9d32be351277c7ea814ac9848bdcb1f16)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 7f0fdd5..4d38a32 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -634,7 +634,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
/* offset */
rs->offset_units = state->offset_units;
- rs->offset_scale = state->offset_scale * 12.0f;
+ rs->offset_scale = state->offset_scale * 16.0f;
tmp = S_0286D4_FLAT_SHADE_ENA(1);
if (state->sprite_coord_enable) {
commit b7a8003c588d928c1be224b595a1c43c76f67de6
Author: Oded Gabbay <oded.gabbay@gmail.com>
Date: Wed Aug 12 18:22:53 2015 +0300
mesa/formats: don't byteswap when building array formats
Because we build here an array format, we don't need to swap the
bytes for big endian.
If it isn't an array format, the bytes will be swapped in
_mesa_format_convert.
v2: remove temp variable
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 5f1d5b1c7857f8680b47a7a450ee9e4530e22c6f)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 8ced579..4fc85ab 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -2570,8 +2570,6 @@ get_swizzle_from_gl_format(GLenum format, uint8_t *swizzle)
uint32_t
_mesa_format_from_format_and_type(GLenum format, GLenum type)
{
- mesa_array_format array_format;
-
bool is_array_format = true;
uint8_t swizzle[4];
bool normalized = false, is_float = false, is_signed = false;
@@ -2627,15 +2625,9 @@ _mesa_format_from_format_and_type(GLenum format, GLenum type)
normalized = !_mesa_is_enum_format_integer(format);
num_channels = _mesa_components_in_format(format);
- array_format =
- MESA_ARRAY_FORMAT(type_size, is_signed, is_float,
- normalized, num_channels,
- swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
-
- if (!_mesa_little_endian())
- array_format = _mesa_array_format_flip_channels(array_format);
-
- return array_format;
+ return MESA_ARRAY_FORMAT(type_size, is_signed, is_float,
+ normalized, num_channels,
+ swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
}
/* Otherwise this is not an array format, so return the mesa_format
commit d18593b4160d75d21e8e5849aeb021514bd77b35
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon Aug 10 01:32:23 2015 -0700
mesa/formats: Don't flip channels of null array formats
Before, if we encountered an array format of 0 on a BE system, we would
flip all the channels even though it's an invalid format. This would
result in a mostly invalid format with a swizzle of yyyy or wwww. Instead,
we should just return 0 if the array format stashed in the format info is
invalid.
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit e3eb91af804f449005a2ff535c805eaa1d579d99)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index a20a41d..bedab99 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -380,7 +380,8 @@ uint32_t
_mesa_format_to_array_format(mesa_format format)
{
const struct gl_format_info *info = _mesa_get_format_info(format);
- if (!_mesa_little_endian() && info->Layout == MESA_FORMAT_LAYOUT_PACKED)
+ if (info->ArrayFormat && !_mesa_little_endian() &&
+ info->Layout == MESA_FORMAT_LAYOUT_PACKED)
return _mesa_array_format_flip_channels(info->ArrayFormat);
else
return info->ArrayFormat;
commit 096282a662a303c24f5de5d8a0eeb16239f0c537
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sun Aug 9 23:45:44 2015 -0700
mesa/formats: Fix swizzle flipping for big-endian targets
The swizzle defines where in the format you should look for any given
channel. When we flip the format around for BE targets, we need to change
the destinations of the swizzles, not the sources. For example, say the
format is an RGBX format with a swizzle of xyz1 on LE. Then it should be
wzy1 on BE; however, the code as it was before, would have made it 1zyx on
BE which is clearly wrong.
Reviewed-by: Iago Toral <itoral@igalia.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 28d1a506c8d09fa66170978c85566c34cbf1cc0a)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 99a5ad3..a20a41d 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -354,14 +354,22 @@ _mesa_array_format_flip_channels(mesa_array_format format)
return format;
if (num_channels == 2) {
- _mesa_array_format_set_swizzle(&format, swizzle[1], swizzle[0],
- swizzle[2], swizzle[3]);
+ /* Assert that the swizzle makes sense for 2 channels */
+ for (unsigned i = 0; i < 4; i++)
+ assert(swizzle[i] != 2 && swizzle[i] != 3);
+
+ static const uint8_t flip_xy[6] = { 1, 0, 2, 3, 4, 5 };
+ _mesa_array_format_set_swizzle(&format,
+ flip_xy[swizzle[0]], flip_xy[swizzle[1]],
+ flip_xy[swizzle[2]], flip_xy[swizzle[3]]);
return format;
}
if (num_channels == 4) {
- _mesa_array_format_set_swizzle(&format, swizzle[3], swizzle[2],
- swizzle[1], swizzle[0]);
+ static const uint8_t flip[6] = { 3, 2, 1, 0, 4, 5 };
+ _mesa_array_format_set_swizzle(&format,
+ flip[swizzle[0]], flip[swizzle[1]],
+ flip[swizzle[2]], flip[swizzle[3]]);
return format;
}
commit c364a00cf957f4e0b5e4d039f1736f54c57e7fde
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Sat Aug 8 09:00:21 2015 -0700
mesa/formats: Only do byteswapping for packed formats
Reviewed-by: Iago Toral <itoral@igalia.com>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3941539179b72fe25b6dffd1aacc0722d198a5ca)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 8af44e9..99a5ad3 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -372,10 +372,10 @@ uint32_t
_mesa_format_to_array_format(mesa_format format)
{
const struct gl_format_info *info = _mesa_get_format_info(format);
- if (_mesa_little_endian())
- return info->ArrayFormat;
- else
+ if (!_mesa_little_endian() && info->Layout == MESA_FORMAT_LAYOUT_PACKED)
return _mesa_array_format_flip_channels(info->ArrayFormat);
+ else
+ return info->ArrayFormat;
}
static struct hash_table *format_array_format_table;
commit e5a198e4dd4771621e70f8a4c8f685e05a3cb22f
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon Aug 10 15:35:21 2015 -0400
radeonsi: add new OLAND pci id
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 87cea61b9e2681e5365e989c7fa7a0298e4005fa)
diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h
index cd5da99..f451b7d 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -63,6 +63,7 @@ CHIPSET(0x6608, OLAND_6608, OLAND)
CHIPSET(0x6610, OLAND_6610, OLAND)
CHIPSET(0x6611, OLAND_6611, OLAND)
CHIPSET(0x6613, OLAND_6613, OLAND)
+CHIPSET(0x6617, OLAND_6617, OLAND)
CHIPSET(0x6620, OLAND_6620, OLAND)
CHIPSET(0x6621, OLAND_6621, OLAND)
CHIPSET(0x6623, OLAND_6623, OLAND)
commit 0a7202385d6c129164feb151deec99a0e43ed7bf
Author: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Mon Aug 10 17:41:36 2015 -0400
nouveau: no need to do tnl wakeup, state updates are always hooked up
A TNL state update now requires a DrawBuffer to be set, which it isn't
early on in context creation. Since we init swtnl from context init,
this caused crashes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3fa1ca34cc0134bd16b3315a0695703c9f684bd4)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c b/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c
index 0753c3a..755de2c 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c
@@ -338,7 +338,6 @@ TAG(swtnl_init)(struct gl_context *ctx)
NUM_VERTEX_ATTRS * 4 * sizeof(GLfloat));
_tnl_need_projected_coords(ctx, GL_FALSE);
_tnl_allow_vertex_fog(ctx, GL_FALSE);
- _tnl_wakeup(ctx);
swtnl_alloc_vertices(ctx);
}
diff --git a/src/mesa/drivers/dri/nouveau/nv04_render.c b/src/mesa/drivers/dri/nouveau/nv04_render.c
index 30e9f9a..3b7f782 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_render.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_render.c
@@ -285,7 +285,6 @@ nv04_render_init(struct gl_context *ctx)
_tnl_init_vertices(ctx, tnl->vb.Size,
NUM_VERTEX_ATTRS * 4 * sizeof(GLfloat));
_tnl_allow_pixel_fog(ctx, GL_FALSE);
- _tnl_wakeup(ctx);
}
void
commit d706b00522e23704ea1cee91fd0d5e7dedccca9e
Author: Oded Gabbay <oded.gabbay@gmail.com>
Date: Tue Aug 4 21:39:32 2015 +0300
mesa: clear existing swizzle info before bitwise-OR
This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.
v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit 2ac171a7db4e4ad2fa902e62bf18bc1f67e91643)
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index 7e451ca..d938e6a 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -191,6 +191,11 @@ static inline void
_mesa_array_format_set_swizzle(mesa_array_format *f,
int32_t x, int32_t y, int32_t z, int32_t w)
{
+ *f &= ~(MESA_ARRAY_FORMAT_SWIZZLE_X_MASK |
+ MESA_ARRAY_FORMAT_SWIZZLE_Y_MASK |
+ MESA_ARRAY_FORMAT_SWIZZLE_Z_MASK |
+ MESA_ARRAY_FORMAT_SWIZZLE_W_MASK);
+
*f |= ((x << 8 ) & MESA_ARRAY_FORMAT_SWIZZLE_X_MASK) |
((y << 11) & MESA_ARRAY_FORMAT_SWIZZLE_Y_MASK) |
((z << 14) & MESA_ARRAY_FORMAT_SWIZZLE_Z_MASK) |
commit d02bb82d52da5029ae2e2cb77f6d2568f5ed425b
Author: Emil Velikov <emil.l.velikov@gmail.com>
Date: Fri Jul 17 12:52:27 2015 +0100
vc4: add missing nir include, to fix the build
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 75ce7919d6496981013a21a7055c668e47e7bed2)
diff --git a/src/gallium/drivers/vc4/Makefile.am b/src/gallium/drivers/vc4/Makefile.am
index 3fc591f..3e9f184 100644
--- a/src/gallium/drivers/vc4/Makefile.am
+++ b/src/gallium/drivers/vc4/Makefile.am
@@ -30,6 +30,7 @@ SIM_LDFLAGS = -lsimpenrose
endif
AM_CFLAGS = \
+ -I$(top_builddir)/src/glsl/nir \
$(LIBDRM_CFLAGS) \
$(GALLIUM_DRIVER_CFLAGS) \
$(SIM_CFLAGS) \
commit 3ebf4afbf704dd7f4b537694a6641de32f856669
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu Jul 23 17:26:56 2015 -0700
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