mesa: Changes to 'upstream-unstable'
VERSION | 2
docs/relnotes/10.2.3.html | 3
docs/relnotes/10.2.4.html | 125 ++++++++++
src/gallium/auxiliary/util/u_blitter.c | 9
src/gallium/auxiliary/util/u_transfer.c | 4
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 10
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 8
src/gallium/drivers/radeonsi/si_shader.c | 9
src/mesa/drivers/dri/i965/brw_defines.h | 10
src/mesa/drivers/dri/i965/brw_fs.cpp | 34 +-
src/mesa/drivers/dri/i965/brw_fs.h | 1
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 54 +++-
src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp | 8
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 12
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 25 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 -
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 2
src/mesa/drivers/dri/i965/gen8_surface_state.c | 54 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 -
src/mesa/main/context.c | 3
src/mesa/main/shared.c | 1
src/mesa/state_tracker/st_context.c | 1
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 8
24 files changed, 339 insertions(+), 75 deletions(-)
New commits:
commit efe8cb1e5374e17fdb04e7cf2025093cfa2d4845
Author: Carl Worth <cworth@cworth.org>
Date: Fri Jul 18 12:45:19 2014 -0700
Add release notes for 10.2.4
Just prior to the release.
diff --git a/docs/relnotes/10.2.4.html b/docs/relnotes/10.2.4.html
new file mode 100644
index 0000000..207b791
--- /dev/null
+++ b/docs/relnotes/10.2.4.html
@@ -0,0 +1,125 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.4 Release Notes / July 18, 2014</h1>
+
+<p>
+Mesa 10.2.4 is a bug fix release which fixes bugs found since the 10.2.3 release.
+</p>
+<p>
+Mesa 10.2.4 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3. OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=81157";>Bug 81157</a> - [BDW]Piglit some spec_glsl-1.50_execution_built-in-functions* cases fail</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Abdiel Janulgue (3):</p>
+<ul>
+ <li>i965/fs: Refactor check for potential copy propagated instructions.</li>
+ <li>i965/fs: skip copy-propate for logical instructions with negated src entries</li>
+ <li>i965/vec4: skip copy-propate for logical instructions with negated src entries</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+ <li>mesa: fix geometry shader memory leaks</li>
+ <li>st/mesa: fix geometry shader memory leak</li>
+ <li>gallium/u_blitter: fix some shader memory leaks</li>
+</ul>
+
+<p>Carl Worth (2):</p>
+<ul>
+ <li>docs: Add sha256 checksums for the 10.2.3 release</li>
+ <li>Update VERSION to 10.2.4</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+ <li>i965: Generalize the pixel_x/y workaround for all UW types.</li>
+</ul>
+
+<p>Ilia Mirkin (4):</p>
+<ul>
+ <li>nv50/ir: retrieve shadow compare from first arg</li>
+ <li>nv50/ir: ignore bias for samplerCubeShadow on nv50</li>
+ <li>nvc0/ir: do quadops on the right texture coordinates for TXD</li>
+ <li>nvc0/ir: use manual TXD when offsets are involved</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+ <li>i965: Add auxiliary surface field #defines for Broadwell.</li>
+</ul>
+
+<p>Kenneth Graunke (9):</p>
+<ul>
+ <li>i965: Don't copy propagate abs into Broadwell logic instructions.</li>
+ <li>i965: Set execution size to 8 for instructions with force_sechalf set.</li>
+ <li>i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.</li>
+ <li>i965/fs: Use WE_all for gl_SampleID header register munging.</li>
+ <li>i965: Add plumbing for Broadwell's auxiliary surface support.</li>
+ <li>i965: Drop SINT workaround for CMS layout on Broadwell.</li>
+ <li>i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.</li>
+ <li>i965: Add 2x MSAA support to the MCS allocation function.</li>
+ <li>i965: Enable compressed multisample support (CMS) on Broadwell.</li>
+</ul>
+
+<p>Marek Olšák (4):</p>
+<ul>
+ <li>gallium: fix u_default_transfer_inline_write for textures</li>
+ <li>st/mesa: fix samplerCubeShadow with bias</li>
+ <li>radeonsi: fix samplerCubeShadow with bias</li>
+ <li>radeonsi: add support for TXB2</li>
+</ul>
+
+<p>Matt Turner (8):</p>
+<ul>
+ <li>i965/vec4: Don't return void from a void function.</li>
+ <li>i965/vec4: Don't fix_math_operand() on Gen >= 8.</li>
+ <li>i965/fs: Don't fix_math_operand() on Gen >= 8.</li>
+ <li>i965/fs: Make try_constant_propagate() static.</li>
+ <li>i965/fs: Constant propagate into 2-src math instructions on Gen8.</li>
+ <li>i965/vec4: Constant propagate into 2-src math instructions on Gen8.</li>
+ <li>i965/fs: Don't use brw_imm_* unnecessarily.</li>
+ <li>i965/fs: Set correct number of regs_written for MCS fetches.</li>
+</ul>
+
+</div>
+</body>
+</html>
commit 54733e5cb87fc132cfce3b18f85a928f4db754a5
Author: Carl Worth <cworth@cworth.org>
Date: Fri Jul 18 12:37:31 2014 -0700
Update VERSION to 10.2.4
In preparation for the 10.2.4 release, of course.
diff --git a/VERSION b/VERSION
index ea657e0..06bcad3 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.2.3
+10.2.4
commit 6388ad51ffc2d179383b7fa38757036973397422
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Jun 24 16:34:49 2014 -0700
i965: Enable compressed multisample support (CMS) on Broadwell.
Everything is in place and appears to be working.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 8cf289c3ef2fcaded5a89f9d7a600f60a5e8356e)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e8a5a00..d783d56 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -67,14 +67,6 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
case GL_DEPTH_STENCIL:
return INTEL_MSAA_LAYOUT_IMS;
default:
- /* Disable MCS on Broadwell for now. We can enable it once things
- * are working without it.
- */
- if (brw->gen >= 8) {
- perf_debug("Missing CMS support on Broadwell.\n");
- return INTEL_MSAA_LAYOUT_UMS;
- }
-
/* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
*
* This field must be set to 0 for all SINT MSRTs when all RT channels
commit ab0ad8f7e9b6203fc9fd074e201a04fa138f3951
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Jun 24 16:33:56 2014 -0700
i965: Add 2x MSAA support to the MCS allocation function.
2x MSAA also uses 8 bits, just like 4x. More bits are unused.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit db184d43b0573c00d911ef9e98fbaab26ebd6466)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4b6b796..e8a5a00 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1249,6 +1249,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
mesa_format format;
switch (num_samples) {
+ case 2:
case 4:
/* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
* each sample).
commit 1c386d5c352c71c5632804c81daffd399c0b237f
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Sat May 10 01:59:10 2014 -0700
i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.
MCS buffers are never allocated on Broadwell, so this does nothing for
now, but puts the infrastructure in place for when they do exist.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit a248b2a4ebb27832d6c8a40ce2b10134f8735b93)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 0268e5c..72983f5 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -157,6 +157,11 @@ gen8_update_texture_surface(struct gl_context *ctx,
pitch = mt->pitch;
}
+ if (mt->mcs_mt) {
+ aux_mt = mt->mcs_mt;
+ aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
+ }
+
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
@@ -355,6 +360,11 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
__FUNCTION__, _mesa_get_format_name(rb_format));
}
+ if (mt->mcs_mt) {
+ aux_mt = mt->mcs_mt;
+ aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
+ }
+
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
&brw->wm.base.surf_offset[surf_index]);
commit e3c0c238736bbfc990bfd275426eb8fd8c259ade
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri May 9 22:22:24 2014 -0700
i965: Drop SINT workaround for CMS layout on Broadwell.
According to the documentation, we don't need this SINT workaround on
Broadwell. (Or at least, it doesn't mention that we need it.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit e10311be9f61230de7f06e9fb30834835ba3677d)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 88bd8f0..4b6b796 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -86,9 +86,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
* would require converting between CMS and UMS MSAA layouts on the fly,
* which is expensive.
*/
- if (_mesa_get_format_datatype(format) == GL_INT) {
- /* TODO: is this workaround needed for future chipsets? */
- assert(brw->gen == 7);
+ if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
} else {
return INTEL_MSAA_LAYOUT_CMS;
commit 2a90fbfce4bd50ab85e1a36f3786720d56323b62
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Sat May 10 01:42:15 2014 -0700
i965: Add plumbing for Broadwell's auxiliary surface support.
Broadwell generalizes the MCS fields to allow for multiple kinds of
auxiliary surfaces. This patch adds the plumbing to set those values,
but doesn't yet hook any up.
v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1.
v3: Don't forget to subtract 1 from aux_mt->pitch.
v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit fd7718768929ff7fd1460bafc32f7b8be75a3140)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 80ac4f3..0268e5c 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -134,6 +134,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
struct intel_mipmap_tree *mt = intelObj->mt;
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
+ struct intel_mipmap_tree *aux_mt = NULL;
+ uint32_t aux_mode = 0;
mesa_format format = intelObj->_Format;
if (tObj->Target == GL_TEXTURE_BUFFER) {
@@ -197,7 +199,13 @@ gen8_update_texture_surface(struct gl_context *ctx,
GEN7_SURFACE_MIN_LOD) |
(intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
- surf[6] = 0;
+ if (aux_mt) {
+ surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
+ SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
+ aux_mode;
+ } else {
+ surf[6] = 0;
+ }
/* Handling GL_ALPHA as a surface format override breaks 1.30+ style
* texturing functions that return a float, as our code generation always
@@ -219,8 +227,15 @@ gen8_update_texture_surface(struct gl_context *ctx,
*((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
- surf[10] = 0;
- surf[11] = 0;
+ if (aux_mt) {
+ *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
+ drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
+ aux_mt->bo, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0);
+ } else {
+ surf[10] = 0;
+ surf[11] = 0;
+ }
surf[12] = 0;
/* Emit relocation to surface contents */
@@ -286,6 +301,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
+ struct intel_mipmap_tree *aux_mt = NULL;
+ uint32_t aux_mode = 0;
unsigned width = mt->logical_width0;
unsigned height = mt->logical_height0;
unsigned pitch = mt->pitch;
@@ -364,7 +381,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
surf[5] = irb->mt_level - irb->mt->first_level;
- surf[6] = 0; /* Nothing of relevance. */
+ if (aux_mt) {
+ surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
+ SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
+ aux_mode;
+ } else {
+ surf[6] = 0;
+ }
surf[7] = mt->fast_clear_color_value |
SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
@@ -374,9 +397,16 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
*((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
- /* Nothing of relevance. */
- surf[10] = 0;
- surf[11] = 0;
+ if (aux_mt) {
+ *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
+ drm_intel_bo_emit_reloc(brw->batch.bo,
+ brw->wm.base.surf_offset[surf_index] + 10 * 4,
+ aux_mt->bo, 0,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ } else {
+ surf[10] = 0;
+ surf[11] = 0;
+ }
surf[12] = 0;
drm_intel_bo_emit_reloc(brw->batch.bo,
commit d374cfe0bca9929d451a47c29fce8445a12d5963
Author: Jordan Justen <jordan.l.justen@intel.com>
Date: Thu Mar 6 09:18:14 2014 -0800
i965: Add auxiliary surface field #defines for Broadwell.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit a46cb6a971b136f41e24739551f6d36ecc1694c0)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3afd399..2f77245 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -580,6 +580,16 @@
#define GEN7_SURFACE_MCS_ENABLE (1 << 0)
#define GEN7_SURFACE_MCS_PITCH_SHIFT 3
#define GEN7_SURFACE_MCS_PITCH_MASK INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_QPITCH_SHIFT 16
+#define GEN8_SURFACE_AUX_QPITCH_MASK INTEL_MASK(30, 16)
+#define GEN8_SURFACE_AUX_PITCH_SHIFT 3
+#define GEN8_SURFACE_AUX_PITCH_MASK INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_MODE_MASK INTEL_MASK(2, 0)
+
+#define GEN8_SURFACE_AUX_MODE_NONE 0
+#define GEN8_SURFACE_AUX_MODE_MCS 1
+#define GEN8_SURFACE_AUX_MODE_APPEND 2
+#define GEN8_SURFACE_AUX_MODE_HIZ 3
/* Surface state DW7 */
#define GEN7_SURFACE_CLEAR_COLOR_SHIFT 28
commit b56908d7db3a691b63e62c41b7ad0a5d4559ee50
Author: Matt Turner <mattst88@gmail.com>
Date: Tue May 27 15:26:06 2014 -0700
i965/fs: Set correct number of regs_written for MCS fetches.
regs_written is in units of virtual GRFs.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit dfd117b8570a69a429e660c069997e78b181ab6d)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 4a23aec..0d55c82 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1588,9 +1588,9 @@ fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler)
inst->base_mrf = -1;
inst->mlen = next.reg_offset * reg_width;
inst->header_present = false;
- inst->regs_written = 4 * reg_width; /* we only care about one reg of response,
- * but the sampler always writes 4/8
- */
+ inst->regs_written = 4; /* we only care about one reg of response,
+ * but the sampler always writes 4/8
+ */
inst->sampler = sampler;
return dest;
commit c6a6acb6b4412427e3a7e49ec5efc769fe43695b
Author: Eric Anholt <eric@anholt.net>
Date: Tue May 6 13:22:10 2014 -0700
i965: Generalize the pixel_x/y workaround for all UW types.
This is the only case where a fs_reg in brw_fs_visitor is used during
optimization/code generation, and it meant that optimizations had to be
careful to not move pixel_x/y's register number without updating it.
Additionally, it turns out we had a couple of other UW values that weren't
getting this treatment (like gl_SampleID), so this more general fix is
probably a good idea (though I wasn't able to replicate problems with
either pixel_[xy]'s values or gl_SampleID, even when telling the register
allocator to reuse registers immediately)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 66f5c8df067ed014c98ef7cf21591e9ea0b5b6bb)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index c7b1f25..7969b67 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -86,10 +86,10 @@ fs_live_variables::setup_one_read(bblock_t *block, fs_inst *inst,
*/
int end_ip = ip;
if (v->dispatch_width == 16 && (reg.stride == 0 ||
- ((v->pixel_x.file == GRF &&
- v->pixel_x.reg == reg.reg) ||
- (v->pixel_y.file == GRF &&
- v->pixel_y.reg == reg.reg)))) {
+ reg.type == BRW_REGISTER_TYPE_UW ||
+ reg.type == BRW_REGISTER_TYPE_W ||
+ reg.type == BRW_REGISTER_TYPE_UB ||
+ reg.type == BRW_REGISTER_TYPE_B)) {
end_ip++;
}
commit 64ff84abaee8d8925a21eea7cd2b833a51b0ba03
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Jul 15 20:40:55 2014 -0700
i965/fs: Use WE_all for gl_SampleID header register munging.
This code should execute without regard to the currently executing
channels. Asking for gl_SampleID inside control flow might break in
strange ways. It appears to break even at the top of the program in
SIMD16 mode occasionally as well.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 6dc9e4e22a19108057162d9d8f8c7d559545f8de)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 48cb9bd..3241e58 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1312,12 +1312,16 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
* and then reading from it using vstride=1, width=4, hstride=0.
* These computations hold good for 4x multisampling as well.
*/
- emit(BRW_OPCODE_AND, t1,
- fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
- fs_reg(0xc0));
- emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
+ fs_inst *inst;
+ inst = emit(BRW_OPCODE_AND, t1,
+ fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
+ fs_reg(0xc0));
+ inst->force_writemask_all = true;
+ inst = emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
+ inst->force_writemask_all = true;
/* This works for both SIMD8 and SIMD16 */
- emit(MOV(t2, brw_imm_v(0x3210)));
+ inst = emit(MOV(t2, brw_imm_v(0x3210)));
+ inst->force_writemask_all = true;
/* This special instruction takes care of setting vstride=1,
* width=4, hstride=0 of t2 during an ADD instruction.
*/
commit 8f4e03c3978c1436d48752ca38e2831fa43e1159
Author: Matt Turner <mattst88@gmail.com>
Date: Thu Apr 17 11:53:22 2014 -0700
i965/fs: Don't use brw_imm_* unnecessarily.
Using brw_imm_* creates a source with file=HW_REG, and the scheduler
inserts barrier dependencies when it sees HW_REG. None of these are
hardware-registers in the sense that they're special and scheduling
shouldn't touch them. A few of the modified cases already have HW_REGs
for other sources, so it won't allow extra flexibility in some cases.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit c938be8ad272a06bc0e91c4e718b61a0c5de400e)
(This patch was cherry-picked to make the next commit apply cleanly.)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b69c21e..48cb9bd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1313,8 +1313,8 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
* These computations hold good for 4x multisampling as well.
*/
emit(BRW_OPCODE_AND, t1,
- fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
- fs_reg(brw_imm_d(0xc0)));
+ fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
+ fs_reg(0xc0));
emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
/* This works for both SIMD8 and SIMD16 */
emit(MOV(t2, brw_imm_v(0x3210)));
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 02511b6..4a23aec 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1533,7 +1533,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
fs_reg chan = coordinate;
chan.reg_offset += i;
- inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
+ inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_G;
/* Our parameter comes in as 1.0/width or 1.0/height,
@@ -2396,7 +2396,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
unsigned mlen = 0;
/* Initialize the sample mask in the message header. */
- emit(MOV(brw_uvec_mrf(8, mlen, 0), brw_imm_ud(0)))
+ emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
->force_writemask_all = true;
if (fp->UsesKill) {
@@ -2442,7 +2442,7 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
unsigned mlen = 0;
/* Initialize the sample mask in the message header. */
- emit(MOV(brw_uvec_mrf(8, mlen, 0), brw_imm_ud(0)))
+ emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
->force_writemask_all = true;
if (fp->UsesKill) {
commit 258f35441a6a572e681c698b60836aa22b949ea4
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Jul 10 17:48:39 2014 -0700
i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.
gen8_fs_generator uses these to decide whether to set the execution size
to 8 or 16, so we incorrectly made both of these MOVs the full width in
SIMD16 shaders. (It happened to work out on Gen4-7.)
Setting them should also help inform optimization passes what's really
going on, which could help avoid bugs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 799a273..b69c21e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1263,19 +1263,21 @@ fs_visitor::emit_samplepos_setup(ir_variable *ir)
stride(retype(brw_vec1_grf(c->sample_pos_reg, 0),
BRW_REGISTER_TYPE_B), 16, 8, 2);
- emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
+ fs_inst *inst = emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
if (dispatch_width == 16) {
- fs_inst *inst = emit(MOV(half(int_sample_x, 1),
- fs_reg(suboffset(sample_pos_reg, 16))));
+ inst->force_uncompressed = true;
+ inst = emit(MOV(half(int_sample_x, 1),
+ fs_reg(suboffset(sample_pos_reg, 16))));
inst->force_sechalf = true;
}
/* Compute gl_SamplePosition.x */
compute_sample_position(pos, int_sample_x);
pos.reg_offset++;
- emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
+ inst = emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
if (dispatch_width == 16) {
- fs_inst *inst = emit(MOV(half(int_sample_y, 1),
- fs_reg(suboffset(sample_pos_reg, 17))));
+ inst->force_uncompressed = true;
+ inst = emit(MOV(half(int_sample_y, 1),
+ fs_reg(suboffset(sample_pos_reg, 17))));
inst->force_sechalf = true;
}
/* Compute gl_SamplePosition.y */
commit cb04294b42ff8fac269eae3b76ad0814bd984dfe
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Jul 10 17:49:36 2014 -0700
i965: Set execution size to 8 for instructions with force_sechalf set.
Both inst->force_uncompressed and inst->force_sechalf mean that the
generated instruction should be uncompressed and have an execution size
of 8. We don't require the visitor to set both flags - setting
inst->force_sechalf by itself is supposed to be enough.
On Gen4-7, guess_execution_size() demoted instructions to 8-wide based
on the default compression state. On Gen8+, we instead set a default
execution size, which worked great...except that we forgot to check
inst->force_sechalf when deciding whether to use 8 or 16.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 1c62126612752f6eedb66f705cc3ff1e11beea5d)
diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
index 97f6404..b96860e 100644
--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
@@ -973,7 +973,7 @@ gen8_fs_generator::generate_code(exec_list *instructions)
default_state.mask_control = ir->force_writemask_all;
default_state.flag_subreg_nr = ir->flag_subreg;
- if (dispatch_width == 16 && !ir->force_uncompressed)
+ if (dispatch_width == 16 && !ir->force_uncompressed && !ir->force_sechalf)
default_state.exec_size = BRW_EXECUTE_16;
else
default_state.exec_size = BRW_EXECUTE_8;
commit d389a863f2f4bd424baf264bfb71950b1dfe32f5
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Jun 23 22:07:38 2014 -0700
i965/vec4: Constant propagate into 2-src math instructions on Gen8.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 7192207de18a7a7e127a8a5910626af96f001993)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index c0eff68..ce9b36c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -73,7 +73,8 @@ is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
}
static bool
-try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
+try_constant_propagation(struct brw_context *brw, vec4_instruction *inst,
+ int arg, src_reg *values[4])
{
/* For constant propagation, we only handle the same constant
* across all 4 channels. Some day, we should handle the 8-bit
@@ -110,6 +111,12 @@ try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
inst->src[arg] = value;
return true;
+ case SHADER_OPCODE_POW:
+ case SHADER_OPCODE_INT_QUOTIENT:
+ case SHADER_OPCODE_INT_REMAINDER:
+ if (brw->gen < 8)
+ break;
+ /* fallthrough */
case BRW_OPCODE_DP2:
case BRW_OPCODE_DP3:
case BRW_OPCODE_DP4:
@@ -357,7 +364,7 @@ vec4_visitor::opt_copy_propagation()
if (c != 4)
continue;
- if (try_constant_propagation(inst, i, values) ||
+ if (try_constant_propagation(brw, inst, i, values) ||
try_copy_propagation(inst, i, values))
progress = true;
}
commit 7fcfdfb17b187c2370a0c31da32908973d526eb3
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Jun 23 22:07:20 2014 -0700
i965/fs: Constant propagate into 2-src math instructions on Gen8.
total instructions in shared programs: 1878133 -> 1876986 (-0.06%)
instructions in affected programs: 153007 -> 151860 (-0.75%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 038eb649b30dfddaf40888ea28b5e88de3af2214)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index ee73d26..ef149c8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -361,7 +361,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
static bool
-try_constant_propagate(fs_inst *inst, acp_entry *entry)
+try_constant_propagate(struct brw_context *brw, fs_inst *inst,
+ acp_entry *entry)
{
bool progress = false;
@@ -389,6 +390,12 @@ try_constant_propagate(fs_inst *inst, acp_entry *entry)
progress = true;
break;
+ case SHADER_OPCODE_POW:
+ case SHADER_OPCODE_INT_QUOTIENT:
+ case SHADER_OPCODE_INT_REMAINDER:
+ if (brw->gen < 8)
+ break;
+ /* fallthrough */
case BRW_OPCODE_BFI1:
case BRW_OPCODE_ASR:
case BRW_OPCODE_SHL:
@@ -530,7 +537,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block,
foreach_list(entry_node, &acp[inst->src[i].reg % ACP_HASH_SIZE]) {
acp_entry *entry = (acp_entry *)entry_node;
- if (try_constant_propagate(inst, entry))
+ if (try_constant_propagate(brw, inst, entry))
progress = true;
if (try_copy_propagate(inst, i, entry))
commit 8612a12a62ce1ed3f8989ca3e969e9992429206e
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Jun 23 22:05:03 2014 -0700
i965/fs: Make try_constant_propagate() static.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit aca4a951ea2bab855bcc2491a3b8996b54639ebd)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 053046b..7618cc7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -368,7 +368,6 @@ public:
bool opt_cse_local(bblock_t *block, exec_list *aeb);
bool opt_copy_propagate();
bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
- bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
exec_list *acp);
void opt_drop_redundant_mov_to_flags();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 2cce13c..ee73d26 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -360,8 +360,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
}
-bool
-fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
+static bool
+try_constant_propagate(fs_inst *inst, acp_entry *entry)
{
bool progress = false;
commit 8f787d3ca286760c16c4cdec3de7978c8098c3c0
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Jun 23 13:30:15 2014 -0700
i965/fs: Don't fix_math_operand() on Gen >= 8.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 48f1143c64e46b3d11dc318d7825b6167a2b78e5)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index efaf11e..799a273 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1393,7 +1393,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
* Gen 6 hardware ignores source modifiers (negate and abs) on math
* instructions, so we also move to a temp to set those up.
*/
- if (brw->gen >= 6)
+ if (brw->gen == 6 || brw->gen == 7)
src = fix_math_operand(src);
fs_inst *inst = emit(opcode, dst, src);
@@ -1425,7 +1425,9 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
return NULL;
}
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ inst = emit(opcode, dst, src0, src1);
+ } else if (brw->gen >= 6) {
src0 = fix_math_operand(src0);
src1 = fix_math_operand(src1);
commit b323fa8957f3b755f8d8be5ec23f18279da47ef0
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Jun 23 13:30:14 2014 -0700
i965/vec4: Don't fix_math_operand() on Gen >= 8.
The emit_math?_gen? functions serve to implement workarounds for the
math instruction, none of which exist on Gen8+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit b24e1cc6049d997e8f78283dcf6a75e99541faed)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 147d915..88ab512 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -365,7 +365,9 @@ vec4_visitor::emit_math(opcode opcode, dst_reg dst, src_reg src)
return;
}
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ emit(opcode, dst, src);
+ } else if (brw->gen >= 6) {
emit_math1_gen6(opcode, dst, src);
} else {
emit_math1_gen4(opcode, dst, src);
@@ -417,7 +419,9 @@ vec4_visitor::emit_math(enum opcode opcode,
return;
}
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ emit(opcode, dst, src0, src1);
+ } else if (brw->gen >= 6) {
emit_math2_gen6(opcode, dst, src0, src1);
} else {
emit_math2_gen4(opcode, dst, src0, src1);
commit d5d94598cb25723f9a4b00220d33122c4188f2ae
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Jun 23 13:30:13 2014 -0700
i965/vec4: Don't return void from a void function.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 0e800dfe75d75c2c5c12bb3762aa9723854a241e)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 54a40dd..147d915 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -366,9 +366,9 @@ vec4_visitor::emit_math(opcode opcode, dst_reg dst, src_reg src)
}
if (brw->gen >= 6) {
- return emit_math1_gen6(opcode, dst, src);
+ emit_math1_gen6(opcode, dst, src);
} else {
- return emit_math1_gen4(opcode, dst, src);
+ emit_math1_gen4(opcode, dst, src);
}
}
@@ -418,9 +418,9 @@ vec4_visitor::emit_math(enum opcode opcode,
}
if (brw->gen >= 6) {
- return emit_math2_gen6(opcode, dst, src0, src1);
+ emit_math2_gen6(opcode, dst, src0, src1);
} else {
- return emit_math2_gen4(opcode, dst, src0, src1);
+ emit_math2_gen4(opcode, dst, src0, src1);
}
}
commit 2efd0a3479d856e3ef76ad2873c14f4c4a4180b1
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Jul 15 21:27:08 2014 -0700
i965: Don't copy propagate abs into Broadwell logic instructions.
It's not clear what abs on logical instructions means on Broadwell, and
it doesn't appear to do anything sensible.
Fixes 270 Piglit tests (the bitand/bitor/bitxor tests with abs).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81157
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a2de6562783ea87ca5fbcb67dbd36c2f345f2054)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 629d2b1..2cce13c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -340,12 +340,9 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
if (has_source_modifiers && entry->dst.type != inst->src[arg].type)
return false;
- if (brw->gen >= 8) {
- if (entry->src.negate) {
- if (is_logic_op(inst->opcode)) {
- return false;
- }
- }
+ if (brw->gen >= 8 && (entry->src.negate || entry->src.abs) &&
+ is_logic_op(inst->opcode)) {
+ return false;
}
inst->src[arg].file = entry->src.file;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
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