xserver-xorg-video-intel: Changes to 'debian-experimental'
NEWS | 48
configure.ac | 7
debian/changelog | 6
src/Makefile.am | 10
src/i915_pciids.h | 25
src/intel_module.c | 16
src/legacy/i810/Makefile.am | 2
src/legacy/i810/i810_common.h | 4
src/legacy/i810/i810_cursor.c | 4
src/legacy/i810/i810_memory.c | 2
src/legacy/i810/i810_ring.h | 2
src/legacy/i810/xvmc/Makefile.am | 4
src/render_program/Makefile.am | 23
src/render_program/exa_wm_src_affine.g8b | 4
src/render_program/exa_wm_src_sample_argb.g8b | 3
src/render_program/exa_wm_src_sample_planar.g8b | 5
src/render_program/exa_wm_write.g8b | 17
src/render_program/exa_wm_yuv_rgb.g8b | 12
src/sna/Makefile.am | 19
src/sna/brw/Makefile.am | 3
src/sna/fb/fbgc.c | 1
src/sna/fb/fbseg.c | 1
src/sna/gen2_render.c | 52
src/sna/gen3_render.c | 50
src/sna/gen4_render.c | 28
src/sna/gen4_vertex.c | 1
src/sna/gen5_render.c | 26
src/sna/gen6_common.h | 9
src/sna/gen6_render.c | 33
src/sna/gen7_render.c | 59
src/sna/gen8_eu.c | 1379 ++++++++
src/sna/gen8_eu.h | 19
src/sna/gen8_render.c | 3909 ++++++++++++++++++++++++
src/sna/gen8_render.h | 1132 ++++++
src/sna/gen8_vertex.c | 296 +
src/sna/gen8_vertex.h | 14
src/sna/kgem.c | 74
src/sna/kgem.h | 16
src/sna/kgem_debug_gen2.c | 1
src/sna/sna.h | 14
src/sna/sna_accel.c | 488 +-
src/sna/sna_blt.c | 31
src/sna/sna_composite.c | 9
src/sna/sna_damage.c | 9
src/sna/sna_display.c | 157
src/sna/sna_display_fake.c | 53
src/sna/sna_dri.c | 42
src/sna/sna_driver.c | 70
src/sna/sna_glyphs.c | 15
src/sna/sna_render.c | 66
src/sna/sna_render.h | 56
src/sna/sna_render_inline.h | 8
src/sna/sna_trapezoids.c | 5
src/sna/sna_trapezoids_boxes.c | 3
src/sna/sna_trapezoids_mono.c | 10
src/sna/sna_video.c | 25
src/sna/sna_video_sprite.c | 5
src/uxa/Makefile.am | 14
src/uxa/i965_3d.c | 1
src/uxa/i965_render.c | 11
src/uxa/intel.h | 10
src/uxa/intel_display.c | 1
src/uxa/intel_dri.c | 19
src/uxa/intel_driver.c | 11
src/uxa/intel_uxa.c | 4
src/uxa/uxa-accel.c | 3
src/uxa/uxa-glyphs.c | 4
src/uxa/uxa-render.c | 1
src/uxa/uxa-unaccel.c | 4
test/.gitignore | 4
test/Makefile.am | 8
test/basic-copyarea-size.c | 2
test/basic-copyarea.c | 6
test/basic-fillrect.c | 6
test/basic-putimage.c | 6
test/basic-rectangle.c | 6
test/basic-stippledrect.c | 239 +
test/basic-stress.c | 2
test/basic-string.c | 6
test/basic-tiledrect.c | 236 +
test/lowlevel-blt-bench.c | 2
test/mixed-stress.c | 2
test/render-composite-solid-mask.c | 118
test/render-composite-solid.c | 6
test/render-copy-alphaless.c | 6
test/render-copyarea-mask.c | 163 +
test/render-copyarea-size.c | 2
test/render-copyarea.c | 6
test/render-fill-copy.c | 6
test/render-fill.c | 6
test/render-trapezoid-image.c | 6
test/render-trapezoid.c | 6
test/test.h | 7
test/test_display.c | 16
test/test_render.c | 2
tools/Makefile.am | 4
tools/virtual.c | 131
97 files changed, 8761 insertions(+), 714 deletions(-)
New commits:
commit d1f9b84d0c03c7e26284dbe16f0c5b276e2efd49
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Mon Jan 6 14:42:14 2014 +0100
bump changelog
diff --git a/debian/changelog b/debian/changelog
index ca85022..3f4a883 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,9 @@
-xserver-xorg-video-intel (2:2.99.906-1) UNRELEASED; urgency=low
+xserver-xorg-video-intel (2:2.99.907-1) UNRELEASED; urgency=low
+ [ Timo Aaltonen ]
+ * New upstream prerelease.
+
+ [ Maarten Lankhorst ]
* New upstream prerelease.
-- Timo Aaltonen <tjaalton@ubuntu.com> Tue, 01 Oct 2013 14:07:22 +0300
commit 4d8f78bc95f8dd36693f74365dbc3c442fbbf8a9
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Jan 2 15:01:38 2014 +0000
sna/gen7+: Emit invalidate between operations if rendering to source/mask
Fixes regression from
commit c79cb18407273dc7798618390bd0b7d69b0f80d6 [2.99.907]
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 20 11:17:20 2013 +0000
sna/gen7: Try to reduce flushes between primitive continuations
Reported-by: Simon Munton <simon.j.munton@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73208
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index 572e3e3..e45555b 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -1114,8 +1114,7 @@ gen7_emit_state(struct sna *sna,
need_stall = sna->render_state.gen7.surface_table != wm_binding_table;
- need_invalidate = need_stall &&
- (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo));
+ need_invalidate = kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo);
if (ALWAYS_INVALIDATE)
need_invalidate = true;
diff --git a/src/sna/gen8_render.c b/src/sna/gen8_render.c
index a8b4ea8..309398d 100644
--- a/src/sna/gen8_render.c
+++ b/src/sna/gen8_render.c
@@ -1130,8 +1130,7 @@ gen8_emit_state(struct sna *sna,
need_stall = sna->render_state.gen8.surface_table != wm_binding_table;
- need_invalidate = need_stall &&
- (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo));
+ need_invalidate = kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo);
if (ALWAYS_INVALIDATE)
need_invalidate = true;
commit c4b88d602640b3e2e46c61928ab194dc9f6b390d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Dec 18 10:33:52 2013 +0000
2.99.907 snapshot
diff --git a/NEWS b/NEWS
index e4e980d..7bef0bc 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,51 @@
+Snapshot 2.99.907 (2013-12-30)
+==============================
+The highlight here is that things seem to be quietening down on the bug
+reporting front. All is not quiet as you will see below, and maybe it is
+just the holiday season that is approaching*, but there has been a
+remarkable falloff in bug reports. Lets hope this trend holds and we can
+make a stable release shortly!
+
+* This was intended to be sent a couple of weeks ago and the holiday season
+has been very quiet....
+
+Oh, and acceleration support for Intel's next generation of
+integrated processor graphics has landed, codenamed Broadwell.
+
+ * Fix potential X server infinite recursion (crash) from a gen2 bug fix
+ Regression in 2.99.906
+ https://bugs.freedesktop.org/show_bug.cgi?id=71605
+
+ * Workaround a missing pipeline flush within Ivybridge, that would
+ leave black rectangles randomly over the output
+ https://bugs.freedesktop.org/show_bug.cgi?id=68410
+
+ * Fix tiled fills. gen2-3 and gen4+ had two different bugs that
+ both broke rendering with small 8x8 patterns in some circumstances
+ https://bugs.freedesktop.org/show_bug.cgi?id=71260
+
+ * Fix reads from a cropped video image using a packed pixel format.
+
+ * Another clear the clear hint after DRI2 SwapBuffers, like the bug fixed
+ in 2.99.903. Failure to clear the hint would cause read backs of the
+ frontbuffer (Xvnc) to be blank.
+ https://bugs.freedesktop.org/show_bug.cgi?id=72194
+
+ * Disable VSync on Baytrail
+ https://bugs.freedesktop.org/show_bug.cgi?id=69869
+
+ * Handle partial uploads with TearFree correctly
+ https://bugs.freedesktop.org/show_bug.cgi?id=72343
+ https://bugs.freedesktop.org/show_bug.cgi?id=72430
+
+ * Avoid recusing through DRI event handlers whilst processing TearFree,
+ leading to a double free (and memory corruption)
+ https://bugs.freedesktop.org/show_bug.cgi?id=72690
+
+ * Hide the gen4 render corruption by crippling the GPU
+ https://bugs.freedesktop.org/show_bug.cgi?id=55500
+
+
Snapshot 2.99.906 (2013-11-13)
==============================
Several stability fixes required after the recent tweaking of the core
diff --git a/configure.ac b/configure.ac
index 9eece7a..9ceb37d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-intel],
- [2.99.906],
+ [2.99.907],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
commit 9289e2c56b7f0cc78c5123691ad96611f0e04bed
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Dec 16 11:39:20 2013 +0000
sna/gen4: Sacrifice performance to workaround render corruption
The long running saga of trying to find an acceptable workaround for the
gen4 rendering corruption (seems to be a read-write hazard failure inside
the gpu) is failing, the only w/a found so far is to send a single
rectangle through the GPU at a time.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index a87af39..637137e 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -63,7 +63,7 @@
#define NO_FILL_BOXES 0
#define NO_VIDEO 0
-#define MAX_FLUSH_VERTICES 6
+#define MAX_FLUSH_VERTICES 1 /* was 6, https://bugs.freedesktop.org/show_bug.cgi?id=55500 */
#define GEN4_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
commit 660fbdac8da1f43749007f126201681023a677e1
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun Dec 15 10:41:22 2013 +0000
sna: Remove stale assertion
Now that we do not remove the move-to-gpu for a plain read from the
TearFree buffer, it is viable to use that buffer as source for cloning.
So we need to kill the stale assertion.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 5df49b3..f1be82a 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -1762,7 +1762,6 @@ sna_pixmap_make_cow(struct sna *sna,
struct sna_cow *cow;
assert(src_priv->gpu_bo);
- assert(src_priv->move_to_gpu == NULL);
if (!USE_COW)
return false;
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 15e32df..5810dd1 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -4357,6 +4357,7 @@ static bool wait_for_shadow(struct sna *sna, struct sna_pixmap *priv, unsigned f
return true;
assert(sna->mode.shadow_active);
+ assert(bo == sna->mode.shadow);
assert(priv->gpu_bo->refcnt >= 1);
sna->mode.shadow = priv->gpu_bo;
commit 989198f3ddc763000702bd1eaeb54002e18a8f04
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun Dec 15 09:45:24 2013 +0000
intel-virtual-output: Disable build if timerfd is not present
Otherwise the build breaks on *BSD.
Reported-by: Yuta SATOH <nigoro.gentoo@0x100.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72707
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/configure.ac b/configure.ac
index dcb09fb..9eece7a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -184,6 +184,7 @@ PKG_CHECK_MODULES(TOOL, [xinerama xrandr xdamage xfixes xcursor xtst xrender xex
if test "x$tools" = "xyes"; then
AC_CHECK_HEADER([sys/ipc.h], [], [tools=no])
AC_CHECK_HEADER([sys/shm.h], [], [tools=no])
+ AC_CHECK_HEADER([sys/timerfd.h], [], [tools=no])
if test "$ac_cv_header_sys_ipc_h" = "yes" -a "$ac_cv_header_sys_shm_h" = "yes"; then
AC_MSG_CHECKING(whether shmctl IPC_RMID allows subsequent attaches)
commit c8e339edd31859820907115c8d618b0fec3ef227
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun Dec 15 09:39:54 2013 +0000
sna: Avoid recursive out-of-order operations in the middle of TearFree
During TearFree, if we have to wait for the shadow flip to complete, we
run the event handler for the device. This can then cause us to evaluate
pending completed vblank events, which may in turn then attempt to use
the shadow bo and recurse into the TearFree handler. Try to prevent this
and requeue the vblank event.
Reported-by: Pascal de Bruijn <pmjdebruijn@pcode.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72690
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index 34d2044..bf970e0 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -1353,6 +1353,24 @@ void sna_dri_vblank_handler(struct sna *sna, struct drm_event_vblank *event)
if (draw == NULL)
goto done;
+ if (sna->mode.shadow_flip && !sna->mode.shadow_damage) {
+ drmVBlank vbl;
+
+ /* recursed from wait_for_shadow(), simply requeue */
+ VG_CLEAR(vbl);
+ vbl.request.type =
+ DRM_VBLANK_RELATIVE |
+ DRM_VBLANK_EVENT |
+ pipe_select(info->pipe);
+ vbl.request.sequence = 1;
+ vbl.request.signal = (unsigned long)info;
+
+ if (sna_wait_vblank(sna, &vbl))
+ goto done;
+
+ return;
+ }
+
switch (info->type) {
case DRI2_FLIP:
/* If we can still flip... */
@@ -1617,6 +1635,8 @@ static void sna_dri_flip_event(struct sna *sna,
flip->fe_tv_usec,
flip->type));
+ assert(!sna->mode.shadow_flip);
+
if (flip->scanout[1].bo) {
struct dri_bo *c = NULL;
commit f350a1369b3bd39ba0db8639f036864fe5df2f98
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Dec 12 16:49:02 2013 +0000
sna/gen4+: Drop new assertion that we only finish a vbo after use in this batch
A full vbo might not be discarded and so upon first use in the following
batch we decided to finish the old vbo and allocate a new. This can
happen before we even emit any relocations and so the assert is bogus.
Reported-by: Jiri Slaby <jirislaby@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/gen4_vertex.c b/src/sna/gen4_vertex.c
index 1ea10b0..38f4cf3 100644
--- a/src/sna/gen4_vertex.c
+++ b/src/sna/gen4_vertex.c
@@ -88,7 +88,6 @@ int gen4_vertex_finish(struct sna *sna)
assert(sna->render.vertex_offset == 0);
assert(sna->render.vertex_used);
assert(sna->render.vertex_used <= sna->render.vertex_size);
- assert(sna->render.nvertex_reloc);
sna_vertex_wait__locked(&sna->render);
diff --git a/src/sna/gen8_vertex.c b/src/sna/gen8_vertex.c
index dcafcd1..dfa4cce 100644
--- a/src/sna/gen8_vertex.c
+++ b/src/sna/gen8_vertex.c
@@ -84,7 +84,6 @@ int gen8_vertex_finish(struct sna *sna)
assert(sna->render.vertex_offset == 0);
assert(sna->render.vertex_used);
assert(sna->render.vertex_used <= sna->render.vertex_size);
- assert(sna->render.nvertex_reloc);
sna_vertex_wait__locked(&sna->render);
commit 7c62925ba7f18f55ee34b946bddba84a07b83985
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Dec 11 21:30:06 2013 +0000
sna: Remove unused variable
sna_display.c: In function 'sna_crtc_redisplay__fallback':
sna_display.c:4104:19: warning: unused variable 'sna_crtc' [-Wunused-variable]
struct sna_crtc *sna_crtc = to_sna_crtc(crtc);
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 44e0feb..15e32df 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -4101,7 +4101,6 @@ static void
sna_crtc_redisplay__fallback(xf86CrtcPtr crtc, RegionPtr region, struct kgem_bo *bo)
{
struct sna *sna = to_sna(crtc->scrn);
- struct sna_crtc *sna_crtc = to_sna_crtc(crtc);
ScreenPtr screen = sna->scrn->pScreen;
PictFormatPtr format;
PicturePtr src, dst;
commit 7e76f21a4d9d8f5424c257e6e7686d5bb0bb6cf7
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Jul 22 18:56:03 2013 +0100
intel: Recognise gen8
Assign gen=8 to the Broadwell PCI IDs, no marketing names are known at
this point in time.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/intel_module.c b/src/intel_module.c
index d739aa7..fb8734a 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -110,6 +110,10 @@ static const struct intel_device_info intel_haswell_info = {
.gen = 075,
};
+static const struct intel_device_info intel_broadwell_info = {
+ .gen = 0100,
+};
+
static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -262,6 +266,9 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_VLV_D_IDS(&intel_valleyview_info),
INTEL_VLV_M_IDS(&intel_valleyview_info),
+ INTEL_BDW_D_IDS(&intel_broadwell_info),
+ INTEL_BDW_M_IDS(&intel_broadwell_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
#endif
commit f7d1c2b8d1883280e7916bb4473ff6436b186950
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Jul 23 08:17:58 2013 +0100
sna: Enable scanline waits for Broadwell
Broadwell uses the same mechanism as Haswell for vsync.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index e4dca71..44e0feb 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -3977,7 +3977,7 @@ sna_wait_for_scanline(struct sna *sna,
DBG(("%s: pipe=%d, y1=%d, y2=%d, full_height?=%d\n",
__FUNCTION__, pipe, y1, y2, full_height));
- if (sna->kgem.gen >= 0100)
+ if (sna->kgem.gen >= 0110)
ret = false;
else if (sna->kgem.gen >= 075)
ret = sna_emit_wait_for_scanline_hsw(sna, crtc, pipe, y1, y2, full_height);
commit e017542d10e875260e3eef1b0369f4ea106df0f5
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Dec 6 22:11:32 2012 +0000
sna/gen8: Initial backend for Broadwell
Should match the functionality of the earlier generations, but untuned.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am
index 1298625..9d36787 100644
--- a/src/render_program/Makefile.am
+++ b/src/render_program/Makefile.am
@@ -174,6 +174,14 @@ INTEL_G7B = \
exa_wm_yuv_rgb.g7b \
$(NULL)
+INTEL_G8B = \
+ exa_wm_src_affine.g8b \
+ exa_wm_src_sample_argb.g8b \
+ exa_wm_src_sample_planar.g8b \
+ exa_wm_write.g8b \
+ exa_wm_yuv_rgb.g8b \
+ $(NULL)
+
EXTRA_DIST = \
$(INTEL_G4A) \
$(INTEL_G4I) \
@@ -185,11 +193,12 @@ EXTRA_DIST = \
$(INTEL_G6B) \
$(INTEL_G6I) \
$(INTEL_G7A) \
- $(INTEL_G7B)
+ $(INTEL_G7B) \
+ $(INTEL_G8B)
if HAVE_GEN4ASM
-SUFFIXES = .g4a .g4b .g5a .g5b .g6a .g6b .g7a .g7b
+SUFFIXES = .g4a .g4b .g5a .g5b .g6a .g6b .g7a .g7b .g8b
.g4a.g4b:
$(AM_V_GEN)m4 -I$(srcdir) -s $< > $*.g4m && @INTEL_GEN4ASM@ -o $@ $*.g4m && @INTEL_GEN4ASM@ -g 5 -o $@.gen5 $*.g4m && rm $*.g4m
@@ -201,17 +210,17 @@ SUFFIXES = .g4a .g4b .g5a .g5b .g6a .g6b .g7a .g7b
.g7a.g7b:
$(AM_V_GEN)m4 -I$(srcdir) -s $< > $*.g7m && @INTEL_GEN4ASM@ -g 7 -o $@ $*.g7m && rm $*.g7m
+.g7a.g8b:
+ $(AM_V_GEN)m4 -I$(srcdir) -s $< > $*.g8m && @INTEL_GEN4ASM@ -g 8 -o $@ $*.g8m && rm $*.g8m
$(INTEL_G4B): $(INTEL_GEN4ASM) $(INTEL_G4I)
$(INTEL_G5B): $(INTEL_GEN4ASM) $(INTEL_G4I)
$(INTEL_G6B): $(INTEL_GEN4ASM) $(INTEL_G4I) $(INTEL_G6I)
$(INTEL_G7B): $(INTEL_GEN4ASM) $(INTEL_G4I) $(INTEL_G6I)
+$(INTEL_G8B): $(INTEL_GEN4ASM) $(INTEL_G4I) $(INTEL_G6I)
-BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G5B) $(INTEL_G6B) $(INTEL_G7B)
+BUILT_SOURCES=$(INTEL_G4B) $(INTEL_G4B_GEN5) $(INTEL_G5B) $(INTEL_G6B) $(INTEL_G7B) $(INTEL_G8B)
clean-local:
- -rm -f $(INTEL_G4B) $(INTEL_G4B_GEN5)
- -rm -f $(INTEL_G5B)
- -rm -f $(INTEL_G6B)
- -rm -f $(INTEL_G7B)
+ -rm -f $(BUILT_SOURCES)
endif
diff --git a/src/render_program/exa_wm_src_affine.g8b b/src/render_program/exa_wm_src_affine.g8b
new file mode 100644
index 0000000..2a55d70
--- /dev/null
+++ b/src/render_program/exa_wm_src_affine.g8b
@@ -0,0 +1,4 @@
+ { 0x0060005a, 0x28403ae8, 0x3a0000c0, 0x008d0040 },
+ { 0x0060005a, 0x28603ae8, 0x3a0000c0, 0x008d0080 },
+ { 0x0060005a, 0x28803ae8, 0x3a0000d0, 0x008d0040 },
+ { 0x0060005a, 0x28a03ae8, 0x3a0000d0, 0x008d0080 },
diff --git a/src/render_program/exa_wm_src_sample_argb.g8b b/src/render_program/exa_wm_src_sample_argb.g8b
new file mode 100644
index 0000000..2349b3d
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_argb.g8b
@@ -0,0 +1,3 @@
+ { 0x00000001, 0x2008060c, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x28200208, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a8c0001 },
diff --git a/src/render_program/exa_wm_src_sample_planar.g8b b/src/render_program/exa_wm_src_sample_planar.g8b
new file mode 100644
index 0000000..3a5e25c
--- /dev/null
+++ b/src/render_program/exa_wm_src_sample_planar.g8b
@@ -0,0 +1,5 @@
+ { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 },
+ { 0x00600001, 0x28200208, 0x008d0000, 0x00000000 },
+ { 0x02800031, 0x22000a48, 0x0e000820, 0x0a2c0001 },
+ { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a2c0003 },
+ { 0x02800031, 0x22400a48, 0x0e000820, 0x0a2c0005 },
diff --git a/src/render_program/exa_wm_write.g8b b/src/render_program/exa_wm_write.g8b
new file mode 100644
index 0000000..6943307
--- /dev/null
+++ b/src/render_program/exa_wm_write.g8b
@@ -0,0 +1,17 @@
+ { 0x00600001, 0x28403ae8, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x28603ae8, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x28803ae8, 0x008d0200, 0x00000000 },
+ { 0x00600001, 0x28a03ae8, 0x008d0220, 0x00000000 },
+ { 0x00600001, 0x28c03ae8, 0x008d0240, 0x00000000 },
+ { 0x00600001, 0x28e03ae8, 0x008d0260, 0x00000000 },
+ { 0x00600001, 0x29003ae8, 0x008d0280, 0x00000000 },
+ { 0x00600001, 0x29203ae8, 0x008d02a0, 0x00000000 },
+ { 0x05800031, 0x24000a40, 0x0e000840, 0x90031000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
diff --git a/src/render_program/exa_wm_yuv_rgb.g8b b/src/render_program/exa_wm_yuv_rgb.g8b
new file mode 100644
index 0000000..0da262c
--- /dev/null
+++ b/src/render_program/exa_wm_yuv_rgb.g8b
@@ -0,0 +1,12 @@
+ { 0x00800040, 0x23003ae8, 0x3e8d0200, 0xbd808081 },
+ { 0x00800041, 0x23003ae8, 0x3e8d0300, 0x3f94fdf4 },
+ { 0x00800040, 0x22c03ae8, 0x3e8d01c0, 0xbf008084 },
+ { 0x00800040, 0x23403ae8, 0x3e8d0240, 0xbf008084 },
+ { 0x00800001, 0x24003ae0, 0x008d0300, 0x00000000 },
+ { 0x80800048, 0x21c03ae8, 0x3e8d02c0, 0x3fcc49ba },
+ { 0x00800001, 0x24003ae0, 0x008d0300, 0x00000000 },
+ { 0x00800048, 0x24003ae0, 0x3e8d02c0, 0xbf5020c5 },
+ { 0x80800048, 0x22003ae8, 0x3e8d0340, 0xbec8b439 },
+ { 0x00800001, 0x24003ae0, 0x008d0300, 0x00000000 },
+ { 0x80800048, 0x22403ae8, 0x3e8d0340, 0x40011687 },
+ { 0x00800001, 0x22803ee8, 0x38000000, 0x3f800000 },
diff --git a/src/sna/Makefile.am b/src/sna/Makefile.am
index 3377b9c..16679c1 100644
--- a/src/sna/Makefile.am
+++ b/src/sna/Makefile.am
@@ -100,6 +100,12 @@ libsna_la_SOURCES = \
gen6_render.h \
gen7_render.c \
gen7_render.h \
+ gen8_eu.c \
+ gen8_eu.h \
+ gen8_render.c \
+ gen8_render.h \
+ gen8_vertex.c \
+ gen8_vertex.h \
$(NULL)
if DRI2
diff --git a/src/sna/gen4_vertex.c b/src/sna/gen4_vertex.c
index 0585c4c..1ea10b0 100644
--- a/src/sna/gen4_vertex.c
+++ b/src/sna/gen4_vertex.c
@@ -88,6 +88,7 @@ int gen4_vertex_finish(struct sna *sna)
assert(sna->render.vertex_offset == 0);
assert(sna->render.vertex_used);
assert(sna->render.vertex_used <= sna->render.vertex_size);
+ assert(sna->render.nvertex_reloc);
sna_vertex_wait__locked(&sna->render);
@@ -125,7 +126,6 @@ int gen4_vertex_finish(struct sna *sna)
}
}
-
size = 256*1024;
assert(!sna->render.active);
sna->render.vertices = NULL;
diff --git a/src/sna/gen8_eu.c b/src/sna/gen8_eu.c
new file mode 100644
index 0000000..7b6d887
--- /dev/null
+++ b/src/sna/gen8_eu.c
@@ -0,0 +1,1379 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <string.h>
+
+#include "compiler.h"
+#include "brw/brw.h"
+#include "gen8_eu.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
+#endif
+
+/* EU ISA */
+
+#define MRF_HACK_START 111
+
+struct gen8_instruction {
+ uint32_t data[4];
+};
+
+static inline unsigned
+__gen8_mask(unsigned high, unsigned low)
+{
+ assert(high >= low);
+ return (1 << (high - low + 1)) - 1;
+}
+
+/**
+ * Fetch a set of contiguous bits from the instruction.
+ *
+ * Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
+ */
+static inline unsigned
+__gen8_bits(struct gen8_instruction *insn, unsigned high, unsigned low)
+{
+ /* We assume the field doesn't cross 32-bit boundaries. */
+ const unsigned word = high / 32;
+
+ assert(word == low / 32);
+
+ high %= 32;
+ low %= 32;
+
+ return (insn->data[word] >> low) & __gen8_mask(high, low);
+}
+
+/**
+ * Set bits in the instruction, with proper shifting and masking.
+ *
+ * Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
+ */
+static inline void
+__gen8_set_bits(struct gen8_instruction *insn,
+ unsigned high,
+ unsigned low,
+ unsigned value)
+{
+ const unsigned word = high / 32;
+ unsigned mask;
+
+ assert(word == low / 32);
+
+ high %= 32;
+ low %= 32;
+ assert(value < __gen8_mask(high, low) + 1);
+
+ mask = __gen8_mask(high, low) << low;
+ insn->data[word] &= ~mask;
+ insn->data[word] |= (value << low) & mask;
+
+ assert(__gen8_bits(insn, 32*word+high, 32*word+low) == value);
+}
+
+#define F(name, high, low) \
+static inline void __gen8_set_##name(struct gen8_instruction *insn, unsigned v) \
+{ \
+ __gen8_set_bits(insn, high, low, v); \
+} \
+static inline unsigned __gen8_##name(struct gen8_instruction *insn) \
+{ \
+ return __gen8_bits(insn, high, low); \
+}
+
+/**
+* Direct addressing only:
+* @{
+*/
+F(src1_da_reg_nr, 108, 101);
+F(src0_da_reg_nr, 76, 69);
+F(dst_da1_hstride, 62, 61);
+F(dst_da_reg_nr, 60, 53);
+F(dst_da16_subreg_nr, 52, 52);
+F(dst_da1_subreg_nr, 52, 48);
+F(da16_writemask, 51, 48); /* Dst.ChanEn */
+/** @} */
+
+F(src1_vert_stride, 120, 117)
+F(src1_da1_width, 116, 114)
+F(src1_da16_swiz_w, 115, 114)
+F(src1_da16_swiz_z, 113, 112)
+F(src1_da1_hstride, 113, 112)
+F(src1_address_mode, 111, 111)
+/** Src1.SrcMod @{ */
+F(src1_negate, 110, 110)
+F(src1_abs, 109, 109)
+/** @} */
+F(src1_da16_subreg_nr, 100, 100)
+F(src1_da1_subreg_nr, 100, 96)
+F(src1_da16_swiz_y, 99, 98)
+F(src1_da16_swiz_x, 97, 96)
+F(src1_reg_type, 94, 91)
+F(src1_reg_file, 90, 89)
+F(src0_vert_stride, 88, 85)
+F(src0_da1_width, 84, 82)
+F(src0_da16_swiz_w, 83, 82)
+F(src0_da16_swiz_z, 81, 80)
+F(src0_da1_hstride, 81, 80)
+F(src0_address_mode, 79, 79)
+/** Src0.SrcMod @{ */
+F(src0_negate, 78, 78)
+F(src0_abs, 77, 77)
+/** @} */
+F(src0_da16_subreg_nr, 68, 68)
+F(src0_da1_subreg_nr, 68, 64)
+F(src0_da16_swiz_y, 67, 66)
+F(src0_da16_swiz_x, 65, 64)
+F(dst_address_mode, 63, 63)
+F(src0_reg_type, 46, 43)
+F(src0_reg_file, 42, 41)
+F(dst_reg_type, 40, 37)
+F(dst_reg_file, 36, 35)
+F(mask_control, 34, 34)
+F(flag_reg_nr, 33, 33)
+F(flag_subreg_nr, 32, 32)
+F(saturate, 31, 31)
+F(branch_control, 30, 30)
+F(debug_control, 30, 30)
+F(cmpt_control, 29, 29)
+F(acc_wr_control, 28, 28)
+F(cond_modifier, 27, 24)
+F(exec_size, 23, 21)
+F(pred_inv, 20, 20)
+F(pred_control, 19, 16)
+F(thread_control, 15, 14)
+F(qtr_control, 13, 12)
+F(nib_control, 11, 11)
+F(dep_control, 10, 9)
+F(access_mode, 8, 8)
+/* Bit 7 is Reserved (for future Opcode expansion) */
+F(opcode, 6, 0)
+
+/**
+* Three-source instructions:
+* @{
+*/
+F(src2_3src_reg_nr, 125, 118)
+F(src2_3src_subreg_nr, 117, 115)
+F(src2_3src_swizzle, 114, 107)
+F(src2_3src_rep_ctrl, 106, 106)
+F(src1_3src_reg_nr, 104, 97)
+F(src1_3src_subreg_hi, 96, 96)
+F(src1_3src_subreg_lo, 95, 94)
+F(src1_3src_swizzle, 93, 86)
+F(src1_3src_rep_ctrl, 85, 85)
+F(src0_3src_reg_nr, 83, 76)
+F(src0_3src_subreg_nr, 75, 73)
+F(src0_3src_swizzle, 72, 65)
+F(src0_3src_rep_ctrl, 64, 64)
+F(dst_3src_reg_nr, 63, 56)
+F(dst_3src_subreg_nr, 55, 53)
+F(dst_3src_writemask, 52, 49)
+F(dst_3src_type, 48, 46)
+F(src_3src_type, 45, 43)
+F(src2_3src_negate, 42, 42)
+F(src2_3src_abs, 41, 41)
+F(src1_3src_negate, 40, 40)
+F(src1_3src_abs, 39, 39)
+F(src0_3src_negate, 38, 38)
+F(src0_3src_abs, 37, 37)
+/** @} */
+
+/**
+* Fields for SEND messages:
+* @{
+*/
+F(eot, 127, 127)
+F(mlen, 124, 121)
+F(rlen, 120, 116)
+F(header_present, 115, 115)
+F(function_control, 114, 96)
+F(sfid, 27, 24)
+F(math_function, 27, 24)
+/** @} */
+
+/**
+* URB message function control bits:
+* @{
+*/
+F(urb_per_slot_offset, 113, 113)
+F(urb_interleave, 111, 111)
+F(urb_global_offset, 110, 100)
+F(urb_opcode, 99, 96)
+/** @} */
+
+/**
+* Sampler message function control bits:
+* @{
+*/
+F(sampler_simd_mode, 114, 113)
+F(sampler_msg_type, 112, 108)
+F(sampler, 107, 104)
+F(binding_table_index, 103, 96)
+/** @} */
+
+/**
+ * Data port message function control bits:
+ * @ {
+ */
+F(dp_category, 114, 114)
+F(dp_message_type, 113, 110)
+F(dp_message_control, 109, 104)
+F(dp_binding_table_index, 103, 96)
+/** @} */
+
+/**
+ * Thread Spawn message function control bits:
+ * @ {
+ */
+F(ts_resource_select, 100, 100)
+F(ts_request_type, 97, 97)
+F(ts_opcode, 96, 96)
+/** @} */
+
+/**
+ * Video Motion Estimation message function control bits:
+ * @ {
+ */
+F(vme_message_type, 110, 109)
+F(vme_binding_table_index, 103, 96)
+/** @} */
+
+/**
+ * Check & Refinement Engine message function control bits:
+ * @ {
+ */
+F(cre_message_type, 110, 109)
+F(cre_binding_table_index, 103, 96)
+/** @} */
+
+#undef F
+
+/**
+* Flow control instruction bits:
+* @{
+*/
+static inline unsigned __gen8_uip(struct gen8_instruction *insn)
+{
+ return insn->data[2];
+}
+
+static inline void __gen8_set_uip(struct gen8_instruction *insn, unsigned uip)
+{
+ insn->data[2] = uip;
+}
+
+static inline unsigned __gen8_jip(struct gen8_instruction *insn)
+{
+ return insn->data[3];
+}
+
+static inline void __gen8_set_jip(struct gen8_instruction *insn, unsigned jip)
+{
+ insn->data[3] = jip;
+}
+/** @} */
+
+static inline int __gen8_src1_imm_d(struct gen8_instruction *insn)
+{
+ return insn->data[3];
+}
+
+static inline unsigned __gen8_src1_imm_ud(struct gen8_instruction *insn)
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