xserver-xorg-video-intel: Changes to 'debian-experimental'
configure.ac | 57 -
debian/changelog | 6
man/intel.man | 11
src/backlight.c | 52 +
src/backlight.h | 3
src/compat-api.h | 10
src/i915_pciids.h | 17
src/intel_device.c | 59 -
src/intel_driver.h | 23
src/intel_module.c | 50 -
src/legacy/i810/i810_driver.c | 2
src/sna/Makefile.am | 1
src/sna/brw/brw_eu.c | 4
src/sna/brw/brw_eu.h | 2
src/sna/brw/brw_test_gen4.c | 12
src/sna/brw/brw_test_gen5.c | 14
src/sna/brw/brw_test_gen6.c | 6
src/sna/brw/brw_test_gen7.c | 2
src/sna/brw/brw_wm.c | 4
src/sna/fb/fbpict.c | 12
src/sna/gen4_render.c | 2
src/sna/gen4_vertex.c | 8
src/sna/gen5_render.c | 4
src/sna/gen6_render.c | 135 ++-
src/sna/gen7_render.c | 18
src/sna/gen8_eu.c | 32
src/sna/gen8_render.c | 76 +-
src/sna/gen8_render.h | 30
src/sna/kgem.c | 959 ++++++++++++++++++--------
src/sna/kgem.h | 71 +
src/sna/sna.h | 23
src/sna/sna_accel.c | 691 +++++++++++--------
src/sna/sna_blt.c | 149 ++--
src/sna/sna_composite.c | 26
src/sna/sna_damage.h | 56 +
src/sna/sna_display.c | 626 +++++++++++++----
src/sna/sna_dri2.c | 382 ++++------
src/sna/sna_dri3.c | 2
src/sna/sna_driver.c | 126 ++-
src/sna/sna_glyphs.c | 10
src/sna/sna_io.c | 67 +
src/sna/sna_present.c | 29
src/sna/sna_render.c | 116 ++-
src/sna/sna_render.h | 8
src/sna/sna_render_inline.h | 24
src/sna/sna_transform.c | 8
src/sna/sna_trapezoids.c | 21
src/sna/sna_trapezoids.h | 74 +-
src/sna/sna_trapezoids_boxes.c | 3
src/sna/sna_trapezoids_imprecise.c | 783 ++++++++++-----------
src/sna/sna_trapezoids_mono.c | 209 +++++
src/sna/sna_trapezoids_precise.c | 879 ++++++++++++++++--------
src/sna/sna_video.c | 1
src/sna/sna_video_hwmc.c | 2
src/sna/sna_video_textured.c | 9
src/sna/xassert.h | 42 +
src/uxa/Makefile.am | 14
src/uxa/i830_3d.c | 1
src/uxa/i830_render.c | 83 +-
src/uxa/i915_3d.c | 1
src/uxa/i915_render.c | 101 +-
src/uxa/i915_video.c | 12
src/uxa/i965_3d.c | 1
src/uxa/i965_render.c | 99 +-
src/uxa/i965_video.c | 50 -
src/uxa/intel.h | 293 +-------
src/uxa/intel_batchbuffer.c | 10
src/uxa/intel_batchbuffer.h | 4
src/uxa/intel_display.c | 142 +++
src/uxa/intel_dri.c | 155 ----
src/uxa/intel_dri3.c | 21
src/uxa/intel_driver.c | 99 +-
src/uxa/intel_glamor.c | 274 -------
src/uxa/intel_glamor.h | 71 -
src/uxa/intel_hwmc.c | 8
src/uxa/intel_memory.c | 140 +++
src/uxa/intel_present.c | 16
src/uxa/intel_uxa.c | 369 ++--------
src/uxa/intel_uxa.h | 299 ++++++++
src/uxa/intel_uxa_video.c | 388 ++++++++++
src/uxa/intel_video.c | 1320 +++++--------------------------------
src/uxa/intel_video.h | 156 +++-
src/uxa/intel_video_overlay.c | 554 +++++++++++++++
src/uxa/intel_video_overlay.h | 51 +
src/uxa/uxa-accel.c | 295 +-------
src/uxa/uxa-glamor.h | 65 -
src/uxa/uxa-glyphs.c | 28
src/uxa/uxa-render.c | 91 --
src/uxa/uxa.c | 11
src/uxa/uxa.h | 16
test/.gitignore | 1
test/DrawSegments.c | 249 ++++++
test/Makefile.am | 1
tools/virtual.c | 4
94 files changed, 6469 insertions(+), 5072 deletions(-)
New commits:
commit 46245adadcfea7391c6a93cfea63de47fb80aaf5
Author: maximilian attems <maks@debian.org>
Date: Sat Nov 22 19:00:11 2014 +0100
update changelog
Signed-off-by: maximilian attems <maks@debian.org>
diff --git a/debian/changelog b/debian/changelog
index 311f090..32eca67 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+xserver-xorg-video-intel (2:2.99.916+git20141119-1~exp1) UNRELEASED; urgency=medium
+
+ * New upstream snapshot.
+
+ -- maximilian attems <maks@debian.org> Sat, 22 Nov 2014 18:58:52 +0100
+
xserver-xorg-video-intel (2:2.99.916-1~exp1) experimental; urgency=medium
[ Vincent Cheng ]
commit 0f15b8b45bb6de10ce1926db303247a5bd3c1c08
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 19 18:42:32 2014 +0000
sna/transform: Correctly check for imprecise fractional translations
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_transform.c b/src/sna/sna_transform.c
index 3b54df4..b62b323 100644
--- a/src/sna/sna_transform.c
+++ b/src/sna/sna_transform.c
@@ -135,14 +135,14 @@ sna_transform_is_imprecise_integer_translation(const PictTransform *t,
int f;
f = pixman_fixed_fraction(t->matrix[0][2]);
- if (f < IntToxFixed(1)/4 || f > IntToxFixed(3)/4) {
- DBG(("%s: imprecise, fractional translation X\n", __FUNCTION__));
+ if (f > IntToxFixed(1)/4 && f < IntToxFixed(3)/4) {
+ DBG(("%s: imprecise, fractional translation X: %x\n", __FUNCTION__, f));
return false;
}
f = pixman_fixed_fraction(t->matrix[1][2]);
- if (f < IntToxFixed(1)/4 || f > IntToxFixed(3)/4) {
- DBG(("%s: imprecise, fractional translation Y\n", __FUNCTION__));
+ if (f > IntToxFixed(1)/4 && f < IntToxFixed(3)/4) {
+ DBG(("%s: imprecise, fractional translation Y: %x\n", __FUNCTION__, f));
return false;
}
}
commit 7725c423cda217e0dbd95003bb7a80b4b3a73bb4
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 19 18:30:20 2014 +0000
sna/dri2: Improve precision of completion event for no-op swaps
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_dri2.c b/src/sna/sna_dri2.c
index 5e9f284..d0760fc 100644
--- a/src/sna/sna_dri2.c
+++ b/src/sna/sna_dri2.c
@@ -1948,8 +1948,8 @@ static void frame_swap_complete(struct sna_dri2_event *frame, int type)
assert(frame->client);
swap = sna_crtc_last_swap(frame->crtc);
- DBG(("%s: draw=%ld, pipe=%d, frame=%lld [msc=%lld], tv=%d.%06d\n",
- __FUNCTION__, (long)frame->draw, frame->pipe,
+ DBG(("%s(type=%d): draw=%ld, pipe=%d, frame=%lld [msc=%lld], tv=%d.%06d\n",
+ __FUNCTION__, type, (long)frame->draw, frame->pipe,
(long long)swap->msc,
(long long)draw_current_msc(frame->draw, frame->crtc, swap->msc),
swap->tv_sec, swap->tv_usec));
@@ -1967,8 +1967,8 @@ static void fake_swap_complete(struct sna *sna, ClientPtr client,
const struct ust_msc *swap;
swap = sna_crtc_last_swap(crtc);
- DBG(("%s: draw=%ld, pipe=%d, frame=%lld [msc %lld], tv=%d.%06d\n",
- __FUNCTION__, (long)draw->id, crtc ? sna_crtc_to_pipe(crtc) : -1,
+ DBG(("%s(type=%d): draw=%ld, pipe=%d, frame=%lld [msc %lld], tv=%d.%06d\n",
+ __FUNCTION__, type, (long)draw->id, crtc ? sna_crtc_to_pipe(crtc) : -1,
(long long)swap->msc,
(long long)draw_current_msc(draw, crtc, swap->msc),
swap->tv_sec, swap->tv_usec));
@@ -2802,6 +2802,7 @@ sna_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
union drm_wait_vblank vbl;
xf86CrtcPtr crtc = NULL;
struct sna_dri2_event *info = NULL;
+ int type = DRI2_EXCHANGE_COMPLETE;
CARD64 current_msc;
DBG(("%s: draw=%lu %dx%d, pixmap=%ld %dx%d, back=%u (refs=%d/%d, flush=%d) , front=%u (refs=%d/%d, flush=%d)\n",
@@ -2973,15 +2974,17 @@ blit:
DBG(("%s -- blit\n", __FUNCTION__));
if (info)
sna_dri2_event_free(info);
- if (can_xchg(sna, draw, front, back))
+ if (can_xchg(sna, draw, front, back)) {
sna_dri2_xchg(draw, front, back);
- else
+ } else {
__sna_dri2_copy_region(sna, draw, NULL, back, front, false);
+ type = DRI2_BLIT_COMPLETE;
+ }
skip:
DBG(("%s: unable to show frame, unblocking client\n", __FUNCTION__));
if (crtc == NULL)
crtc = sna_mode_first_crtc(sna);
- fake_swap_complete(sna, client, draw, crtc, DRI2_BLIT_COMPLETE, func, data);
+ fake_swap_complete(sna, client, draw, crtc, type, func, data);
*target_msc = 0; /* offscreen, so zero out target vblank count */
return TRUE;
}
commit f367f3dee5e2ecba265a8ff7e98e196189793613
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 19 18:19:13 2014 +0000
sna/dri2: Add more DBG to explain invalid frames
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_dri2.c b/src/sna/sna_dri2.c
index f3395ce..5e9f284 100644
--- a/src/sna/sna_dri2.c
+++ b/src/sna/sna_dri2.c
@@ -2831,11 +2831,18 @@ sna_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
assert(get_private(front)->bo->refcnt);
assert(get_private(back)->bo->refcnt);
- if (get_private(front)->pixmap != get_drawable_pixmap(draw))
+ if (get_private(front)->pixmap != get_drawable_pixmap(draw)) {
+ DBG(("%s: decoupled DRI2 front pixmap=%ld, actual pixmap=%ld\n",
+ __FUNCTION__,
+ get_private(front)->pixmap->drawable.serialNumber,
+ get_drawable_pixmap(draw)->drawable.serialNumber));
goto skip;
+ }
- if (get_private(back)->stale)
+ if (get_private(back)->stale) {
+ DBG(("%s: stale back buffer\n", __FUNCTION__));
goto skip;
+ }
assert(sna_pixmap_from_drawable(draw)->flush);
@@ -2849,8 +2856,15 @@ sna_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
priv->front = NULL;
}
if (win->clipList.extents.x2 <= win->clipList.extents.x1 ||
- win->clipList.extents.y2 <= win->clipList.extents.y1)
+ win->clipList.extents.y2 <= win->clipList.extents.y1) {
+ DBG(("%s: window clipped (%d, %d), (%d, %d)\n",
+ __FUNCTION__,
+ win->clipList.extents.x1,
+ win->clipList.extents.y1,
+ win->clipList.extents.x2,
+ win->clipList.extents.y2));
goto skip;
+ }
}
/* Drawable not displayed... just complete the swap */
commit 05a1aba1ab5d288918d6689080170fc83a80db61
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 19 18:12:10 2014 +0000
sna: DBG compile fix
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index 72ffb04..bea2295 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -3287,7 +3287,7 @@ expire:
goto retry;
ERR(("%s: failed to write batch (handle=%d): %d\n",
- __FUNCTION__, handle, -ret));
+ __FUNCTION__, bo->handle, -ret));
return ret;
}
commit a90cc3b3889fafbd91c11c42d068a9d6474e218b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Nov 18 08:37:25 2014 +0000
sna: Tweak alignment constraints on gen8 to allow BLT
The previous commits prevent us from using the BLT if the destination
address is misaligned. Honour that restriction when creating buffers as
well, so that they are always usuable by the BLT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index fe225d2..72ffb04 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -1797,6 +1797,8 @@ inline static uint32_t kgem_pitch_alignment(struct kgem *kgem, unsigned flags)
return 256;
if (flags & CREATE_SCANOUT)
return 64;
+ if (kgem->gen >= 0100)
+ return 32;
return 8;
}
@@ -7234,7 +7236,7 @@ struct kgem_bo *kgem_create_buffer_2d(struct kgem *kgem,
assert(width > 0 && height > 0);
assert(ret != NULL);
stride = ALIGN(width, 2) * bpp >> 3;
- stride = ALIGN(stride, 4);
+ stride = ALIGN(stride, kgem->gen >= 0100 ? 32 : 4);
DBG(("%s: %dx%d, %d bpp, stride=%d\n",
__FUNCTION__, width, height, bpp, stride));
commit 8dee52997891108eec8e4df12dd02f3a060d9cb8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 19 13:38:20 2014 +0000
sna: Add more checks and asserts for BLT capable bo
Before we use the BLT for core acceleration, double check that we can.
This should catch the case where we attempt to operate on SHM pixmaps
which do not meet the restrictions.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index 13f52e4..a5784af 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -5198,6 +5198,9 @@ sna_put_xybitmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
assert_pixmap_contains_box(pixmap, RegionExtents(region));
if (damage)
sna_damage_add_to_pixmap(damage, region, pixmap);
@@ -5210,6 +5213,7 @@ sna_put_xybitmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
y += dy + drawable->y;
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
/* Region is pre-clipped and translated into pixmap space */
box = region_rects(region);
@@ -5358,6 +5362,9 @@ sna_put_xypixmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
assert_pixmap_contains_box(pixmap, RegionExtents(region));
if (damage)
sna_damage_add_to_pixmap(damage, region, pixmap);
@@ -5370,6 +5377,7 @@ sna_put_xypixmap_blt(DrawablePtr drawable, GCPtr gc, RegionPtr region,
y += dy + drawable->y;
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
skip = h * BitmapBytePad(w + left);
for (i = 1 << (gc->depth-1); i; i >>= 1, bits += skip) {
@@ -8214,6 +8222,7 @@ sna_copy_bitmap_blt(DrawablePtr _bitmap, DrawablePtr drawable, GCPtr gc,
br13 |= copy_ROP[gc->alu] << 16;
kgem_set_mode(&sna->kgem, KGEM_BLT, arg->bo);
+ assert(kgem_bo_can_blt(&sna->kgem, arg->bo));
do {
int bx1 = (box->x1 + sx) & ~7;
int bx2 = (box->x2 + sx + 7) & ~7;
@@ -8436,6 +8445,7 @@ sna_copy_plane_blt(DrawablePtr source, DrawablePtr drawable, GCPtr gc,
br13 |= copy_ROP[gc->alu] << 16;
kgem_set_mode(&sna->kgem, KGEM_BLT, arg->bo);
+ assert(kgem_bo_can_blt(&sna->kgem, arg->bo));
do {
int bx1 = (box->x1 + sx) & ~7;
int bx2 = (box->x2 + sx + 7) & ~7;
@@ -8722,6 +8732,10 @@ sna_copy_plane(DrawablePtr src, DrawablePtr dst, GCPtr gc,
goto fallback;
}
}
+
+ if (!kgem_bo_can_blt(&sna->kgem, arg.bo))
+ return false;
+
RegionUninit(®ion);
return sna_do_copy(src, dst, gc,
src_x, src_y,
@@ -12159,9 +12173,14 @@ sna_poly_fill_rect_tiled_8x8_blt(DrawablePtr drawable,
if (tile_bo->tiling)
return false;
+ if (!kgem_bo_can_blt(&sna->kgem, bo) ||
+ !kgem_bo_can_blt(&sna->kgem, tile_bo))
+ return false;
+
assert(tile_bo->pitch == 8 * drawable->bitsPerPixel >> 3);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 10+2*3) ||
!kgem_check_reloc(&sna->kgem, 2) ||
!kgem_check_many_bo_fenced(&sna->kgem, bo, tile_bo, NULL)) {
@@ -13097,6 +13116,7 @@ sna_poly_fill_rect_stippled_8x8_blt(DrawablePtr drawable,
}
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 10 + 2*3) ||
!kgem_check_bo_fenced(&sna->kgem, bo) ||
!kgem_check_reloc(&sna->kgem, 1)) {
@@ -13475,6 +13495,7 @@ sna_poly_fill_rect_stippled_1_blt(DrawablePtr drawable,
get_drawable_deltas(drawable, pixmap, &dx, &dy);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
br00 = 3 << 20;
br13 = bo->pitch;
@@ -14389,6 +14410,7 @@ sna_poly_fill_rect_stippled_n_blt__imm(DrawablePtr drawable,
get_drawable_deltas(drawable, pixmap, &dx, &dy);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
br00 = XY_MONO_SRC_COPY_IMM | 3 << 20;
br13 = bo->pitch;
@@ -14533,6 +14555,7 @@ sna_poly_fill_rect_stippled_n_blt(DrawablePtr drawable,
get_drawable_deltas(drawable, pixmap, &dx, &dy);
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
br00 = XY_MONO_SRC_COPY | 3 << 20;
br13 = bo->pitch;
@@ -14660,10 +14683,9 @@ sna_poly_fill_rect_stippled_blt(DrawablePtr drawable,
{
PixmapPtr stipple = gc->stipple;
+ PixmapPtr pixmap = get_drawable_pixmap(drawable);
if (bo->tiling == I915_TILING_Y) {
- PixmapPtr pixmap = get_drawable_pixmap(drawable);
-
DBG(("%s: converting bo from Y-tiling\n", __FUNCTION__));
/* This is cheating, but only the gpu_bo can be tiled */
assert(bo == __sna_pixmap_get_bo(pixmap));
@@ -14675,6 +14697,9 @@ sna_poly_fill_rect_stippled_blt(DrawablePtr drawable,
}
}
+ if (!kgem_bo_can_blt(&to_sna_from_pixmap(pixmap)->kgem, bo))
+ return false;
+
if (!sna_drawable_move_to_cpu(&stipple->drawable, MOVE_READ))
return false;
@@ -15221,6 +15246,9 @@ sna_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
if (get_drawable_deltas(drawable, pixmap, &dx, &dy))
RegionTranslate(clip, dx, dy);
_x += drawable->x + dx;
@@ -15239,6 +15267,7 @@ sna_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 20) ||
!kgem_check_bo_fenced(&sna->kgem, bo) ||
!kgem_check_reloc(&sna->kgem, 1)) {
@@ -15938,6 +15967,9 @@ sna_reversed_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
if (get_drawable_deltas(drawable, pixmap, &dx, &dy))
RegionTranslate(clip, dx, dy);
_x += drawable->x + dx;
@@ -15956,6 +15988,7 @@ sna_reversed_glyph_blt(DrawablePtr drawable, GCPtr gc,
}
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
if (!kgem_check_batch(&sna->kgem, 20) ||
!kgem_check_bo_fenced(&sna->kgem, bo) ||
!kgem_check_reloc(&sna->kgem, 1)) {
@@ -16397,6 +16430,9 @@ sna_push_pixels_solid_blt(GCPtr gc,
}
}
+ if (!kgem_bo_can_blt(&sna->kgem, bo))
+ return false;
+
if (get_drawable_deltas(drawable, pixmap, &dx, &dy))
RegionTranslate(region, dx, dy);
@@ -16410,6 +16446,7 @@ sna_push_pixels_solid_blt(GCPtr gc,
region->extents.x2, region->extents.y2));
kgem_set_mode(&sna->kgem, KGEM_BLT, bo);
+ assert(kgem_bo_can_blt(&sna->kgem, bo));
/* Region is pre-clipped and translated into pixmap space */
box = region_rects(region);
commit 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date: Wed Nov 19 15:10:05 2014 +0200
sna: gen8 BLT broken when address has bit 4 set
With bit 4 set in address, the gen8 blitter fails and blits errorneously
into the cacheline preceeding the destination and similarly when reading from
the source, corrupting memory.
v2: Update the destination base offset pattern as revealed
by igt/tests/gem_userptr_blits/destination-bo-align
v3: Check base address as well
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: xunx.fang@intel.com [v2]
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
diff --git a/src/sna/kgem.h b/src/sna/kgem.h
index 6adae3b..3275b4f 100644
--- a/src/sna/kgem.h
+++ b/src/sna/kgem.h
@@ -551,6 +551,13 @@ static inline bool kgem_bo_blt_pitch_is_ok(struct kgem *kgem,
struct kgem_bo *bo)
{
int pitch = bo->pitch;
+
+ if (kgem->gen >= 0100 && pitch & (1 << 4)) { /* bdw is broken */
+ DBG(("%s: can not blt to handle=%d, pitch=%d\n",
+ __FUNCTION__, bo->handle, pitch));
+ return false;
+ }
+
if (kgem->gen >= 040 && bo->tiling)
pitch /= 4;
if (pitch > MAXSHORT) {
@@ -573,6 +580,12 @@ static inline bool kgem_bo_can_blt(struct kgem *kgem,
return false;
}
+ if (kgem->gen >= 0100 && bo->proxy && bo->delta & (1 << 4)) {
+ DBG(("%s: can not blt to handle=%d, delta=%d\n",
+ __FUNCTION__, bo->handle, bo->delta));
+ return false;
+ }
+
return kgem_bo_blt_pitch_is_ok(kgem, bo);
}
commit 29aab766f4b59c71181875880c8c943b93008bdf
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Nov 18 20:54:39 2014 +0000
sna/dri2: Remove unused function
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_dri2.c b/src/sna/sna_dri2.c
index c8c71c5..f3395ce 100644
--- a/src/sna/sna_dri2.c
+++ b/src/sna/sna_dri2.c
@@ -64,15 +64,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
static inline struct kgem_bo *ref(struct kgem_bo *bo)
{
- assert(bo->refcnt);
- bo->refcnt++;
- return bo;
-}
-
-static inline void unref(struct kgem_bo *bo)
-{
- assert(bo->refcnt > 1);
- bo->refcnt--;
+ return kgem_bo_reference(bo);
}
struct sna_dri2_private {
commit b6eeb7a1f7efa591504070b606be655e27e6e9c2
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 5 13:03:41 2014 +0000
Disable DRI3 by default
The external libraries, both in git, and especially shipping already
enabled in distributions, are buggy and lead to server crashes and
lockups. Caveat emptor.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/configure.ac b/configure.ac
index 328b4e9..cbfc472 100644
--- a/configure.ac
+++ b/configure.ac
@@ -339,10 +339,10 @@ AC_ARG_ENABLE(dri2,
[DRI2=$enableval],
[DRI2=yes])
AC_ARG_ENABLE(dri3,
- AS_HELP_STRING([--disable-dri3],
- [Disable DRI3 support [[default=yes]]]),
+ AS_HELP_STRING([--enable-dri3],
+ [Enable DRI3 support [[default=no]]]),
[DRI3=$enableval],
- [DRI3=yes])
+ [DRI3=no])
AC_ARG_ENABLE(xvmc, AS_HELP_STRING([--disable-xvmc],
[Disable XvMC support [[default=yes]]]),
commit 6c2707d7bbc0ebb422be66618b6f78887c46446e
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Nov 13 08:37:13 2014 +0000
sna: Unroll pwrite using our cached mmappings
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index e8d71d8..fe225d2 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -517,6 +517,36 @@ retry_wc:
return bo->map__wc = (void *)(uintptr_t)wc.addr_ptr;
}
+static void *__kgem_bo_map__cpu(struct kgem *kgem, struct kgem_bo *bo)
+{
+ struct drm_i915_gem_mmap mmap_arg;
+ int err;
+
+retry:
+ VG_CLEAR(mmap_arg);
+ mmap_arg.handle = bo->handle;
+ mmap_arg.offset = 0;
+ mmap_arg.size = bytes(bo);
+ if ((err = do_ioctl(kgem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg))) {
+ assert(err != EINVAL);
+
+ if (__kgem_throttle_retire(kgem, 0))
+ goto retry;
+
+ if (kgem_cleanup_cache(kgem))
+ goto retry;
+
+ ERR(("%s: failed to mmap handle=%d, %d bytes, into CPU domain: %d\n",
+ __FUNCTION__, bo->handle, bytes(bo), -err));
+ return NULL;
+ }
+
+ VG(VALGRIND_MAKE_MEM_DEFINED(mmap_arg.addr_ptr, bytes(bo)));
+
+ DBG(("%s: caching CPU vma for %d\n", __FUNCTION__, bo->handle));
+ return bo->map__cpu = (void *)(uintptr_t)mmap_arg.addr_ptr;
+}
+
static int gem_write(int fd, uint32_t handle,
int offset, int length,
const void *src)
@@ -638,6 +668,7 @@ static void kgem_bo_maybe_retire(struct kgem *kgem, struct kgem_bo *bo)
bool kgem_bo_write(struct kgem *kgem, struct kgem_bo *bo,
const void *data, int length)
{
+ void *ptr;
int err;
assert(bo->refcnt);
@@ -646,6 +677,22 @@ bool kgem_bo_write(struct kgem *kgem, struct kgem_bo *bo,
assert(length <= bytes(bo));
retry:
+ ptr = NULL;
+ if (bo->domain == DOMAIN_CPU || (kgem->has_llc && !bo->scanout)) {
+ ptr = bo->map__cpu;
+ if (ptr == NULL)
+ ptr = __kgem_bo_map__cpu(kgem, bo);
+ } else if (kgem->has_wc_mmap) {
+ ptr = bo->map__wc;
+ if (ptr == NULL)
+ ptr = __kgem_bo_map__wc(kgem, bo);
+ }
+ if (ptr) {
+ /* XXX unsynchronized? */
+ memcpy(ptr, data, length);
+ return true;
+ }
+
if ((err = gem_write(kgem->fd, bo->handle, 0, length, data))) {
assert(err != EINVAL);
@@ -3149,24 +3196,50 @@ static void kgem_cleanup(struct kgem *kgem)
kgem_close_inactive(kgem);
}
-static int kgem_batch_write(struct kgem *kgem, uint32_t handle, uint32_t size)
+static int
+kgem_batch_write(struct kgem *kgem,
+ struct kgem_bo *bo,
+ uint32_t size)
{
+ char *ptr;
int ret;
- ASSERT_IDLE(kgem, handle);
+ ASSERT_IDLE(kgem, bo->handle);
#if DBG_NO_EXEC
{
uint32_t batch[] = { MI_BATCH_BUFFER_END, 0};
- return gem_write(kgem->fd, handle, 0, sizeof(batch), batch);
+ return gem_write(kgem->fd, bo->handle, 0, sizeof(batch), batch);
}
#endif
-
+ assert(!bo->scanout);
retry:
+ ptr = NULL;
+ if (bo->domain == DOMAIN_CPU || kgem->has_llc) {
+ ptr = bo->map__cpu;
+ if (ptr == NULL)
+ ptr = __kgem_bo_map__cpu(kgem, bo);
+ } else if (kgem->has_wc_mmap) {
+ ptr = bo->map__wc;
+ if (ptr == NULL)
+ ptr = __kgem_bo_map__wc(kgem, bo);
+ }
+ if (ptr) {
+ memcpy(ptr, kgem->batch, sizeof(uint32_t)*kgem->nbatch);
+ if (kgem->surface != kgem->batch_size) {
+ ret = PAGE_ALIGN(sizeof(uint32_t) * kgem->batch_size);
+ ret -= sizeof(uint32_t) * kgem->surface;
+ ptr += size - ret;
+ memcpy(ptr, kgem->batch + kgem->surface,
+ (kgem->batch_size - kgem->surface)*sizeof(uint32_t));
+ }
+ return 0;
+ }
+
/* If there is no surface data, just upload the batch */
if (kgem->surface == kgem->batch_size) {
- if ((ret = gem_write__cachealigned(kgem->fd, handle,
+ if ((ret = gem_write__cachealigned(kgem->fd, bo->handle,
0, sizeof(uint32_t)*kgem->nbatch,
kgem->batch)) == 0)
return 0;
@@ -3177,7 +3250,7 @@ retry:
/* Are the batch pages conjoint with the surface pages? */
if (kgem->surface < kgem->nbatch + PAGE_SIZE/sizeof(uint32_t)) {
assert(size == PAGE_ALIGN(kgem->batch_size*sizeof(uint32_t)));
- if ((ret = gem_write__cachealigned(kgem->fd, handle,
+ if ((ret = gem_write__cachealigned(kgem->fd, bo->handle,
0, kgem->batch_size*sizeof(uint32_t),
kgem->batch)) == 0)
return 0;
@@ -3186,7 +3259,7 @@ retry:
}
/* Disjoint surface/batch, upload separately */
- if ((ret = gem_write__cachealigned(kgem->fd, handle,
+ if ((ret = gem_write__cachealigned(kgem->fd, bo->handle,
0, sizeof(uint32_t)*kgem->nbatch,
kgem->batch)))
goto expire;
@@ -3194,7 +3267,7 @@ retry:
ret = PAGE_ALIGN(sizeof(uint32_t) * kgem->batch_size);
ret -= sizeof(uint32_t) * kgem->surface;
assert(size-ret >= kgem->nbatch*sizeof(uint32_t));
- if (gem_write(kgem->fd, handle,
+ if (gem_write(kgem->fd, bo->handle,
size - ret, (kgem->batch_size - kgem->surface)*sizeof(uint32_t),
kgem->batch + kgem->surface))
goto expire;
@@ -3388,7 +3461,7 @@ out_16384:
if (bo) {
write:
kgem_fixup_relocs(kgem, bo, shrink);
- if (kgem_batch_write(kgem, bo->handle, size)) {
+ if (kgem_batch_write(kgem, bo, size)) {
kgem_bo_destroy(kgem, bo);
return NULL;
}
@@ -6251,36 +6324,6 @@ void *kgem_bo_map__wc(struct kgem *kgem, struct kgem_bo *bo)
return __kgem_bo_map__wc(kgem, bo);
}
-static void *__kgem_bo_map__cpu(struct kgem *kgem, struct kgem_bo *bo)
-{
- struct drm_i915_gem_mmap mmap_arg;
- int err;
-
-retry:
- VG_CLEAR(mmap_arg);
- mmap_arg.handle = bo->handle;
- mmap_arg.offset = 0;
- mmap_arg.size = bytes(bo);
- if ((err = do_ioctl(kgem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg))) {
- assert(err != EINVAL);
-
- if (__kgem_throttle_retire(kgem, 0))
- goto retry;
-
- if (kgem_cleanup_cache(kgem))
- goto retry;
-
- ERR(("%s: failed to mmap handle=%d, %d bytes, into CPU domain: %d\n",
- __FUNCTION__, bo->handle, bytes(bo), -err));
- return NULL;
- }
-
- VG(VALGRIND_MAKE_MEM_DEFINED(mmap_arg.addr_ptr, bytes(bo)));
-
- DBG(("%s: caching CPU vma for %d\n", __FUNCTION__, bo->handle));
- return bo->map__cpu = (void *)(uintptr_t)mmap_arg.addr_ptr;
-}
-
void *kgem_bo_map__cpu(struct kgem *kgem, struct kgem_bo *bo)
{
DBG(("%s(handle=%d, size=%d, map=%p:%p)\n",
commit f9f85b88032b2458d4d24ceca450fdaa65e6b94d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 12 11:50:33 2014 +0000
sna: Reorder PARAMs based on upstream inclusion
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/kgem.c b/src/sna/kgem.c
index dd91801..e8d71d8 100644
--- a/src/sna/kgem.c
+++ b/src/sna/kgem.c
@@ -140,7 +140,7 @@ search_snoop_cache(struct kgem *kgem, unsigned int num_pages, unsigned flags);
#define LOCAL_I915_PARAM_HAS_NO_RELOC 25
#define LOCAL_I915_PARAM_HAS_HANDLE_LUT 26
#define LOCAL_I915_PARAM_HAS_WT 27
-#define LOCAL_I915_PARAM_MMAP_VERSION 29
+#define LOCAL_I915_PARAM_MMAP_VERSION 30
#define LOCAL_I915_EXEC_IS_PINNED (1<<10)
#define LOCAL_I915_EXEC_NO_RELOC (1<<11)
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index d098642..0b7e838 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -5034,7 +5034,7 @@ sna_cursor_pre_init(struct sna *sna)
#define DRM_CAP_CURSOR_WIDTH 8
#define DRM_CAP_CURSOR_HEIGHT 9
-#define I915_PARAM_HAS_COHERENT_PHYS_GTT 30
+#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
sna->cursor.max_size = 64;
commit 13fa1f1a26aed83cd8fccafb9a0bdb096f69534b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Nov 12 10:54:36 2014 +0000
sna/gen7: Be paranoid and force a pipecontrol stall at least every 4 flushes
The documentation warns of potential GPU hangs if we emit more than 4
pipecontrol flushes without a CS stall. This is highly unlikely given
how frequently we must inject stalls into the pipeline, but force a
stall just in case!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index 2d8f296..2ecfd64 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -1069,6 +1069,7 @@ gen7_emit_pipe_invalidate(struct sna *sna)
GEN7_PIPE_CONTROL_CS_STALL);
OUT_BATCH(0);
OUT_BATCH(0);
+ sna->render_state.gen7.pipe_controls_since_stall = 0;
}
inline static void
@@ -1077,9 +1078,11 @@ gen7_emit_pipe_flush(struct sna *sna, bool need_stall)
unsigned stall;
stall = 0;
- if (need_stall)
- stall = (GEN7_PIPE_CONTROL_CS_STALL |
- GEN7_PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ if (need_stall) {
+ stall = GEN7_PIPE_CONTROL_CS_STALL;
+ sna->render_state.gen7.pipe_controls_since_stall = 0;
+ } else
+ sna->render_state.gen7.pipe_controls_since_stall++;
OUT_BATCH(GEN7_PIPE_CONTROL | (4 - 2));
OUT_BATCH(GEN7_PIPE_CONTROL_WC_FLUSH | stall);
@@ -1095,6 +1098,7 @@ gen7_emit_pipe_stall(struct sna *sna)
GEN7_PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0);
OUT_BATCH(0);
+ sna->render_state.gen7.pipe_controls_since_stall = 0;
}
static void
@@ -1124,6 +1128,9 @@ gen7_emit_state(struct sna *sna,
need_stall &= gen7_emit_drawing_rectangle(sna, op);
if (ALWAYS_STALL)
need_stall = true;
+ if (sna->kgem.gen < 075 &&
+ sna->render_state.gen7.pipe_controls_since_stall >= 3)
+ need_stall = true;
if (need_invalidate) {
gen7_emit_pipe_invalidate(sna);
@@ -3746,6 +3753,7 @@ gen7_render_clear(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo)
}
static void gen7_render_reset(struct sna *sna)
{
+ sna->render_state.gen7.pipe_controls_since_stall = 0;
sna->render_state.gen7.emit_flush = false;
sna->render_state.gen7.needs_invariant = true;
sna->render_state.gen7.ve_id = 3 << 2;
diff --git a/src/sna/sna_render.h b/src/sna/sna_render.h
index 823b86c..6e1fa48 100644
--- a/src/sna/sna_render.h
+++ b/src/sna/sna_render.h
@@ -508,6 +508,7 @@ struct gen7_render_state {
uint16_t last_primitive;
int16_t floats_per_vertex;
uint16_t surface_table;
+ uint16_t pipe_controls_since_stall;
bool needs_invariant;
bool emit_flush;
commit b2492fa45beaf3c676eea2d5d75e35d60b91d769
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Nov 10 13:30:15 2014 +0000
sna: Only reshow unhidden cursors after modesetting
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna.h b/src/sna/sna.h
index 9d139ed..8129eae 100644
--- a/src/sna/sna.h
+++ b/src/sna/sna.h
@@ -326,6 +326,7 @@ struct sna {
uint32_t fg, bg;
int size;
+ int active;
int last_x;
int last_y;
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index f16a46c..d098642 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -4728,6 +4728,7 @@ sna_show_cursors(ScrnInfoPtr scrn)
}
}
sigio_unblock(sigio);
+ sna->cursor.active = true;
}
static void
@@ -4792,6 +4793,7 @@ sna_hide_cursors(ScrnInfoPtr scrn)
int sigio, c;
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