xserver-xorg-video-ati: Changes to 'debian-unstable'
configure.ac | 10 +++++-----
debian/changelog | 7 +++++++
debian/rules | 2 +-
man/radeon.man | 9 ++++++---
src/ati_pciids_gen.h | 35 ++++++++++++++++++++++++++++++++++-
src/drmmode_display.c | 5 ++++-
src/evergreen_exa.c | 20 +++++++++++++-------
src/evergreen_textured_videofuncs.c | 15 ++++++++++-----
src/pcidb/ati_pciids.csv | 35 ++++++++++++++++++++++++++++++++++-
src/r600_exa.c | 5 +++--
src/radeon.h | 2 +-
src/radeon_bo_helper.c | 2 +-
src/radeon_chipinfo_gen.h | 35 ++++++++++++++++++++++++++++++++++-
src/radeon_chipset_gen.h | 35 ++++++++++++++++++++++++++++++++++-
src/radeon_dri2.c | 32 ++++++++++++++------------------
src/radeon_drm.h | 2 ++
src/radeon_exa_funcs.c | 5 +++--
src/radeon_glamor.c | 13 +++++++++++++
src/radeon_glamor.h | 4 ++++
src/radeon_kms.c | 30 +++++++++++++++++++-----------
src/radeon_pci_chipset_gen.h | 35 ++++++++++++++++++++++++++++++++++-
src/radeon_pci_device_match_gen.h | 35 ++++++++++++++++++++++++++++++++++-
src/radeon_probe.c | 10 ++++++++++
src/radeon_probe.h | 2 +-
src/radeon_video.c | 9 ++++++++-
25 files changed, 329 insertions(+), 65 deletions(-)
New commits:
commit 3d0f6fffe56f5016addfc44f894121ea85c7713c
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Tue Jan 28 11:56:27 2014 +0100
New upstream release.
Explicitly disable glamor for now to prevent a FTBFS.
diff --git a/debian/changelog b/debian/changelog
index e5425b0..bd9517e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+xserver-xorg-video-ati (1:7.3.0-1) UNRELEASED; urgency=low
+
+ * New upstream release.
+ * Explicitly disable glamor for now to prevent a FTBFS.
+
+ -- Maarten Lankhorst <maarten.lankhorst@ubuntu.com> Tue, 28 Jan 2014 11:49:28 +0100
+
xserver-xorg-video-ati (1:7.2.0-1) unstable; urgency=low
[ Maarten Lankhorst ]
diff --git a/debian/rules b/debian/rules
index 6d9d6a8..d76a0b9 100755
--- a/debian/rules
+++ b/debian/rules
@@ -3,7 +3,7 @@
XXV=xserver-xorg-video
override_dh_auto_configure:
- dh_auto_configure --builddirectory=build/ -- --libdir=/usr/lib
+ dh_auto_configure --builddirectory=build/ -- --libdir=/usr/lib --disable-glamor
# Kill *.la files, and forget no-one:
override_dh_install:
commit 0333f5bda27dc0ec2edc180c7a4dc9a432f13f97
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Jan 24 10:19:49 2014 -0500
radeon: bump version for release
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/configure.ac b/configure.ac
index 729a6fa..9c444f0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-ati],
- [7.2.99],
+ [7.3.0],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-ati])
commit fc4167f2a85d9cba65078d8fc6f08c7a619ad66e
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Jan 24 10:17:08 2014 -0500
Require glamor 0.6.0
This is required for Xv support and a number of important
performance improvements.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/configure.ac b/configure.ac
index 835b7b9..729a6fa 100644
--- a/configure.ac
+++ b/configure.ac
@@ -107,7 +107,7 @@ AC_ARG_ENABLE(glamor,
AC_MSG_RESULT([$GLAMOR])
AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno)
if test "x$GLAMOR" != "xno"; then
- PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.5.0])
+ PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0])
PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
fi
commit f2a0a5cf6c5a21e2a02280e110a4eb8e6609dace
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Jan 22 11:04:42 2014 +0900
Don't require the glamoregl module to be pre-loaded with xserver >= 1.15
The issues with loading it on demand have been fixed in xserver 1.15.
Inspired by Jérôme Glisse on IRC.
diff --git a/src/radeon_glamor.c b/src/radeon_glamor.c
index bd731a8..1d666d1 100644
--- a/src/radeon_glamor.c
+++ b/src/radeon_glamor.c
@@ -105,12 +105,14 @@ radeon_glamor_pre_init(ScrnInfoPtr scrn)
return FALSE;
}
+#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,15,0,0,0)
if (!xf86LoaderCheckSymbol("glamor_egl_init")) {
xf86DrvMsg(scrn->scrnIndex, s ? X_ERROR : X_WARNING,
"glamor requires Load \"glamoregl\" in "
"Section \"Module\", disabling.\n");
return FALSE;
}
+#endif
/* Load glamor module */
if ((glamor_module = xf86LoadSubModule(scrn, GLAMOR_EGL_MODULE_NAME))) {
commit 3213df16d61302148be0088c8f93c6a5a88558f1
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Jan 8 11:30:59 2014 +0900
dri2: Make last_vblank_seq local unsigned to match dpms_last_seq
Without this, I was occasionally running into gnome-shell hangs due to
wildly off vblank sequence values. Doesn't seem to happen anymore with
this change.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 79d8f39..d47b035 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -890,7 +890,7 @@ CARD32 radeon_dri2_extrapolate_msc_delay(xf86CrtcPtr crtc, CARD64 *target_msc,
RADEONInfoPtr info = RADEONPTR(pScrn);
int nominal_frame_rate = drmmode_crtc->dpms_last_fps;
CARD64 last_vblank_ust = drmmode_crtc->dpms_last_ust;
- int last_vblank_seq = drmmode_crtc->dpms_last_seq;
+ uint32_t last_vblank_seq = drmmode_crtc->dpms_last_seq;
int interpolated_vblanks = drmmode_crtc->interpolated_vblanks;
int target_seq;
CARD64 now, target_time, delta_t;
commit bcc454ea2fb239e13942270faec7801270615b9c
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon Jan 6 09:52:50 2014 -0500
radeon/exa: Always use a scratch surface for UTS to vram
If we don't, we may hit a buffer that crosses the
visible vram boundary resulting in a sigbus when the
CPU accesses the buffer beyond the PCI aperture.
This will introduce an extra copy in certain cases.
This is based on Michel's patch from bug 44099 updated
for all asic families.
Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=44099
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index abb5076..d788bfc 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1658,13 +1658,14 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- /* If we know the BO won't be busy, don't bother with a scratch */
+ /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
- if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
+ if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+ !(dst_domain & RADEON_GEM_DOMAIN_VRAM))
goto copy;
}
}
diff --git a/src/r600_exa.c b/src/r600_exa.c
index a354ccd..8d11ce7 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1538,13 +1538,14 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- /* If we know the BO won't be busy, don't bother with a scratch */
+ /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
- if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
+ if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+ !(dst_domain & RADEON_GEM_DOMAIN_VRAM))
goto copy;
}
/* use cpu copy for fast fb access */
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index d9340c5..d901305 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -403,13 +403,14 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
}
#endif
- /* If we know the BO won't be busy, don't bother with a scratch */
+ /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
- if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
+ if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+ !(dst_domain & RADEON_GEM_DOMAIN_VRAM))
goto copy;
}
/* use cpu copy for fast fb access */
commit 04ef035c9315b4a6fbf1b14720be87cee4099a9f
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Tue Dec 24 15:14:35 2013 -0500
drm/radeon: fix SUMO2 pci id
0x9649 is sumo2, not sumo.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index b34dfe6..eb57992 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -460,7 +460,7 @@
#define PCI_CHIP_SUMO2_9645 0x9645
#define PCI_CHIP_SUMO_9647 0x9647
#define PCI_CHIP_SUMO_9648 0x9648
-#define PCI_CHIP_SUMO_9649 0x9649
+#define PCI_CHIP_SUMO2_9649 0x9649
#define PCI_CHIP_SUMO_964A 0x964A
#define PCI_CHIP_SUMO_964B 0x964B
#define PCI_CHIP_SUMO_964C 0x964C
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 7f52d67..8469a2a 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -461,7 +461,7 @@
"0x9645","SUMO2_9645","SUMO2",1,1,,,1,"SUMO2"
"0x9647","SUMO_9647","SUMO",1,1,,,1,"SUMO"
"0x9648","SUMO_9648","SUMO",1,1,,,1,"SUMO"
-"0x9649","SUMO_9649","SUMO",1,1,,,1,"SUMO"
+"0x9649","SUMO2_9649","SUMO2",1,1,,,1,"SUMO2"
"0x964A","SUMO_964A","SUMO",,1,,,1,"SUMO"
"0x964B","SUMO_964B","SUMO",,1,,,1,"SUMO"
"0x964C","SUMO_964C","SUMO",,1,,,1,"SUMO"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index be038b6..fc9474b 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -380,7 +380,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9645, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
{ 0x9647, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x9648, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
- { 0x9649, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
+ { 0x9649, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
{ 0x964A, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
{ 0x964B, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
{ 0x964C, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 0cd484e..afab6b0 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -380,7 +380,7 @@ SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_SUMO2_9645, "SUMO2" },
{ PCI_CHIP_SUMO_9647, "SUMO" },
{ PCI_CHIP_SUMO_9648, "SUMO" },
- { PCI_CHIP_SUMO_9649, "SUMO" },
+ { PCI_CHIP_SUMO2_9649, "SUMO2" },
{ PCI_CHIP_SUMO_964A, "SUMO" },
{ PCI_CHIP_SUMO_964B, "SUMO" },
{ PCI_CHIP_SUMO_964C, "SUMO" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 23dcca6..da4440b 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -380,7 +380,7 @@ static PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_SUMO2_9645, PCI_CHIP_SUMO2_9645, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_9647, PCI_CHIP_SUMO_9647, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_9648, PCI_CHIP_SUMO_9648, RES_SHARED_VGA },
- { PCI_CHIP_SUMO_9649, PCI_CHIP_SUMO_9649, RES_SHARED_VGA },
+ { PCI_CHIP_SUMO2_9649, PCI_CHIP_SUMO2_9649, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964A, PCI_CHIP_SUMO_964A, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964B, PCI_CHIP_SUMO_964B, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964C, PCI_CHIP_SUMO_964C, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index b3e58a9..d4b3763 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -380,7 +380,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9645, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9647, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9648, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9649, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9649, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964C, 0 ),
commit bfbff3b246db509c820df17b8fcf5899882ffcfa
Author: Robert Millan <rmh@freebsd.org>
Date: Fri Dec 20 11:03:14 2013 +0000
radeon: Restore kernel module load on FreeBSD.
Since the introduction of a call to drmCheckModesettingSupported()
in radeon_kernel_mode_enabled(), with abort condition if such call
fails, the drmOpen() call in radeon_open_drm_master() no longer
takes the responsibility of loading the radeon kernel module.
However at least on FreeBSD (and GNU/kFreeBSD), X is still relied
on to load the modules it needs. This commit restores the old
behaviour of loading kernel modules on these systems.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72852
Signed-off-by: Robert Millan <rmh@freebsd.org>
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index baca574..2d3c58e 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -50,6 +50,10 @@
#include "xf86drmMode.h"
#include "dri.h"
+#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
+#include <xf86_OSproc.h>
+#endif
+
#ifdef XSERVER_PLATFORM_BUS
#include <xf86platformBus.h>
#endif
@@ -92,6 +96,12 @@ static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci
busIdString = DRICreatePCIBusID(pci_dev);
ret = drmCheckModesettingSupported(busIdString);
+#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
+ if (ret) {
+ if (xf86LoadKernelModule("radeonkms"))
+ ret = drmCheckModesettingSupported(busIdString);
+ }
+#endif
free(busIdString);
if (ret) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0,
commit 796c9a0cb587f528326bede11fa3f3eb7d3edaf1
Author: Robert Millan <rmh@freebsd.org>
Date: Fri Dec 20 10:55:09 2013 +0000
radeon: Set first parameter of drmOpen() to NULL
Since the introduction of a call to drmCheckModesettingSupported()
in radeon_kernel_mode_enabled(), with abort condition if such call
fails, the first argument to drmOpen() call in radeon_open_drm_master()
has become a no-op red herring.
Such argument (a kernel module name) is supposed to result in load
of specified kernel module. However, this will never happen. The
problem is that if the code containing drmOpen() call is reached, it
means that drmCheckModesettingSupported() check has previously
succeeded, which implies the module is already loaded.
So, drmOpen() will never load a kernel module. But it gives the
impression that it will.
In order to avoid this confusion, this commit replaces it with NULL,
like xf86-video-intel driver does.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72849
Signed-off-by: Robert Millan <rmh@freebsd.org>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 44a0139..21a420f 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -607,7 +607,7 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
dev->domain, dev->bus, dev->dev, dev->func);
#endif
- info->dri2.drm_fd = drmOpen("radeon", busid);
+ info->dri2.drm_fd = drmOpen(NULL, busid);
if (info->dri2.drm_fd == -1) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
commit d571d6af70ef27efd1ed6420eb892bdde963ed7a
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Tue Sep 24 11:39:10 2013 -0400
radeon/kms: add Hawaii pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 17222c1..b34dfe6 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -743,3 +743,15 @@
#define PCI_CHIP_KAVERI_131B 0x131B
#define PCI_CHIP_KAVERI_131C 0x131C
#define PCI_CHIP_KAVERI_131D 0x131D
+#define PCI_CHIP_HAWAII_67A0 0x67A0
+#define PCI_CHIP_HAWAII_67A1 0x67A1
+#define PCI_CHIP_HAWAII_67A2 0x67A2
+#define PCI_CHIP_HAWAII_67A8 0x67A8
+#define PCI_CHIP_HAWAII_67A9 0x67A9
+#define PCI_CHIP_HAWAII_67AA 0x67AA
+#define PCI_CHIP_HAWAII_67B0 0x67B0
+#define PCI_CHIP_HAWAII_67B1 0x67B1
+#define PCI_CHIP_HAWAII_67B8 0x67B8
+#define PCI_CHIP_HAWAII_67B9 0x67B9
+#define PCI_CHIP_HAWAII_67BA 0x67BA
+#define PCI_CHIP_HAWAII_67BE 0x67BE
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index abde9d4..7f52d67 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -744,3 +744,15 @@
"0x131B","KAVERI_131B","KAVERI",,1,,,1,"KAVERI"
"0x131C","KAVERI_131C","KAVERI",,1,,,1,"KAVERI"
"0x131D","KAVERI_131D","KAVERI",,1,,,1,"KAVERI"
+"0x67A0","HAWAII_67A0","HAWAII",,,,,,"HAWAII"
+"0x67A1","HAWAII_67A1","HAWAII",,,,,,"HAWAII"
+"0x67A2","HAWAII_67A2","HAWAII",,,,,,"HAWAII"
+"0x67A8","HAWAII_67A8","HAWAII",,,,,,"HAWAII"
+"0x67A9","HAWAII_67A9","HAWAII",,,,,,"HAWAII"
+"0x67AA","HAWAII_67AA","HAWAII",,,,,,"HAWAII"
+"0x67B0","HAWAII_67B0","HAWAII",,,,,,"HAWAII"
+"0x67B1","HAWAII_67B1","HAWAII",,,,,,"HAWAII"
+"0x67B8","HAWAII_67B8","HAWAII",,,,,,"HAWAII"
+"0x67B9","HAWAII_67B9","HAWAII",,,,,,"HAWAII"
+"0x67BA","HAWAII_67BA","HAWAII",,,,,,"HAWAII"
+"0x67BE","HAWAII_67BE","HAWAII",,,,,,"HAWAII"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index bd4d85f..be038b6 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -663,4 +663,16 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x131B, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
{ 0x131C, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
{ 0x131D, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 },
+ { 0x67A0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67A1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67A2, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67A8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67A9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67AA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67B0, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67B1, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67B8, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67B9, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67BA, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
+ { 0x67BE, CHIP_FAMILY_HAWAII, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 40f2d9c..0cd484e 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -663,5 +663,17 @@ SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_KAVERI_131B, "KAVERI" },
{ PCI_CHIP_KAVERI_131C, "KAVERI" },
{ PCI_CHIP_KAVERI_131D, "KAVERI" },
+ { PCI_CHIP_HAWAII_67A0, "HAWAII" },
+ { PCI_CHIP_HAWAII_67A1, "HAWAII" },
+ { PCI_CHIP_HAWAII_67A2, "HAWAII" },
+ { PCI_CHIP_HAWAII_67A8, "HAWAII" },
+ { PCI_CHIP_HAWAII_67A9, "HAWAII" },
+ { PCI_CHIP_HAWAII_67AA, "HAWAII" },
+ { PCI_CHIP_HAWAII_67B0, "HAWAII" },
+ { PCI_CHIP_HAWAII_67B1, "HAWAII" },
+ { PCI_CHIP_HAWAII_67B8, "HAWAII" },
+ { PCI_CHIP_HAWAII_67B9, "HAWAII" },
+ { PCI_CHIP_HAWAII_67BA, "HAWAII" },
+ { PCI_CHIP_HAWAII_67BE, "HAWAII" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index e8b5f13..23dcca6 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -663,5 +663,17 @@ static PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_KAVERI_131B, PCI_CHIP_KAVERI_131B, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_131C, PCI_CHIP_KAVERI_131C, RES_SHARED_VGA },
{ PCI_CHIP_KAVERI_131D, PCI_CHIP_KAVERI_131D, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67A0, PCI_CHIP_HAWAII_67A0, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67A1, PCI_CHIP_HAWAII_67A1, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67A2, PCI_CHIP_HAWAII_67A2, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67A8, PCI_CHIP_HAWAII_67A8, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67A9, PCI_CHIP_HAWAII_67A9, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67AA, PCI_CHIP_HAWAII_67AA, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67B0, PCI_CHIP_HAWAII_67B0, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67B1, PCI_CHIP_HAWAII_67B1, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67B8, PCI_CHIP_HAWAII_67B8, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67B9, PCI_CHIP_HAWAII_67B9, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67BA, PCI_CHIP_HAWAII_67BA, RES_SHARED_VGA },
+ { PCI_CHIP_HAWAII_67BE, PCI_CHIP_HAWAII_67BE, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 4b0de84..b3e58a9 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -663,5 +663,17 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_131D, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A2, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67A9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67AA, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67B9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BA, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HAWAII_67BE, 0 ),
{ 0, 0, 0 }
};
commit e38a92e00d015a6b80a1f3a16d58c61f084b066f
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Tue Sep 24 11:35:00 2013 -0400
radeon: add support for Hawaii
Disabled by default until the acceleration code stablizes.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/man/radeon.man b/man/radeon.man
index b642e45..1363d8b 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -205,6 +205,9 @@ KAVERI APUs
.TP 12
.B KABINI
KABINI APUs
+.TP 12
+.B HAWAII
+Radeon R9 series
.PD
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 5b85acc..44a0139 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -489,7 +489,8 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
info->is_fast_fb = TRUE;
}
- if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
+ if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL,
+ info->ChipFamily == CHIP_FAMILY_HAWAII) ||
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for KMS\n");
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index de0135d..cea6695 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -110,6 +110,7 @@ typedef enum {
CHIP_FAMILY_BONAIRE,
CHIP_FAMILY_KAVERI,
CHIP_FAMILY_KABINI,
+ CHIP_FAMILY_HAWAII,
CHIP_FAMILY_LAST
} RADEONChipFamily;
commit e4cd0f4392ea11c93088ad429f36eaaf9bcbf505
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Wed Oct 30 15:21:26 2013 -0400
radeon: enable tiling on SI by default (v2)
Now that mesa 9.2 is out with support for tiling
on SI asics, we can enable it here. Tiling improves
memory bandwidth utilization.
V2: update man page
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/man/radeon.man b/man/radeon.man
index 40a38ec..b642e45 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -245,7 +245,7 @@ this enables 1D tiling mode.
The default value is
.B on
for R/RV3XX, R/RV4XX, R/RV5XX, RS6XX, RS740, R/RV6XX, R/RV7XX, RS780, RS880,
-EVERGREEN, CAYMAN, and ARUBA and
+EVERGREEN, CAYMAN, ARUBA, and Southern Islands and
.B off
for R/RV/RS1XX, R/RV/RS2XX, RS3XX, and RS690/RS780/RS880 when fast fb feature is enabled.
.TP
@@ -254,11 +254,11 @@ The framebuffer can be addressed either in linear, 1D, or 2D tiled modes. 2D til
provide significant performance benefits over 1D tiling with 3D applications. Tiling
will be disabled if the drm module is too old or if the current display configuration
does not support it. KMS ColorTiling2D is only supported on R600 and newer chips and requires
-Mesa 9.0 or newer.
+Mesa 9.0 or newer for R6xx-ARUBA and Mesa 9.2 or newer for Southern Islands.
.br
The default value is
.B on
-for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, and ARUBA.
+for R/RV6XX, R/RV7XX, RS780, RS880, EVERGREEN, CAYMAN, ARUBA, and Southern Islands.
.TP
.BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
Enable DRI2 page flipping. The default is
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 255906b..5b85acc 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -860,17 +860,17 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
Bool colorTilingDefault =
xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) &&
info->ChipFamily >= CHIP_FAMILY_R300 &&
- /* this ARUBA check could be removed sometime after a big mesa release
+ /* this check could be removed sometime after a big mesa release
* with proper bit, in the meantime you need to set tiling option in
* xorg configuration files
*/
- info->ChipFamily <= CHIP_FAMILY_ARUBA &&
+ info->ChipFamily <= CHIP_FAMILY_HAINAN &&
!info->is_fast_fb;
/* 2D color tiling */
if (info->ChipFamily >= CHIP_FAMILY_R600) {
info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D,
- info->ChipFamily <= CHIP_FAMILY_ARUBA);
+ info->ChipFamily <= CHIP_FAMILY_HAINAN);
}
if (info->ChipFamily >= CHIP_FAMILY_R600) {
commit 3b38701a72fa1cad1e4610a2f4330b3da4cc6391
Author: Vadim Girlin <vadimgirlin@gmail.com>
Date: Fri Nov 1 10:36:39 2013 -0400
radeon: disable 2D tiling on buffers < 128 pixels
Seems to run into alignment problems with certain
card configurations.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=70675
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index 539590c..ed964d7 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -124,7 +124,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
surface.last_level = 0;
surface.bpe = cpp;
surface.nsamples = 1;
- if (height < 64) {
+ if (height < 128) {
/* disable 2d tiling for small surface to work around
* the fact that ddx align height to 8 pixel for old
* obscure reason i can't remember
commit 0c921edf0162fed616cea9d02e168b719243bcd2
Author: Jerome Glisse <jglisse@redhat.com>
Date: Wed Oct 30 13:01:02 2013 -0400
radeon/glamor: with new pixmap for dri2 drawable no need to create new texture
When creating a new pixmap/bo for dri2 drawable there is no need to create a
new texture, instead the texture associated with the new pixmap should be use
otherwise there is a missmatch between the bo backing the texture for the
drawable and the bo used by dri2 client.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/configure.ac b/configure.ac
index 0fe0991..835b7b9 100644
--- a/configure.ac
+++ b/configure.ac
@@ -107,7 +107,7 @@ AC_ARG_ENABLE(glamor,
AC_MSG_RESULT([$GLAMOR])
AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno)
if test "x$GLAMOR" != "xno"; then
- PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.5.1])
+ PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.5.0])
PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
fi
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index a211960..79d8f39 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -66,6 +66,10 @@
#define FALLBACK_SWAP_DELAY 16
+#ifdef USE_GLAMOR
+#include <glamor.h>
+#endif
+
typedef DRI2BufferPtr BufferPtr;
struct dri2_buffer_priv {
@@ -89,7 +93,6 @@ static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap)
PixmapPtr old = get_drawable_pixmap(drawable);
#ifdef USE_GLAMOR
ScreenPtr screen = drawable->pScreen;
- ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
struct radeon_pixmap *priv = radeon_get_pixmap_private(pixmap);
GCPtr gc;
@@ -118,21 +121,13 @@ static PixmapPtr fixup_glamor(DrawablePtr drawable, PixmapPtr pixmap)
}
radeon_set_pixmap_private(pixmap, NULL);
- screen->DestroyPixmap(pixmap);
/* And redirect the pixmap to the new bo (for 3D). */
+ glamor_egl_exchange_buffers(old, pixmap);
radeon_set_pixmap_private(old, priv);
+ screen->DestroyPixmap(pixmap);
old->refcnt++;
- /* This creating should not fail, as we already created its
- * successfully. But if it happens, we put a warning indicator
- * here, and the old pixmap will still be a glamor pixmap, and
- * latter the pixmap_flink will get a 0 name, then the X server
- * will pass a BadAlloc to the client.*/
- if (!radeon_glamor_create_textured_pixmap(old))
- xf86DrvMsg(scrn->scrnIndex, X_WARNING,
- "Failed to get DRI drawable for glamor pixmap.\n");
-
screen->ModifyPixmapHeader(old,
old->drawable.width,
old->drawable.height,
commit f1dc677e79cd7a88d7379a934ebc7d87a3b18805
Author: Christopher James Halse Rogers <raof@ubuntu.com>
Date: Mon Sep 23 12:25:29 2013 -0700
EXA/evergreen: Paranoia around linear tiling. (v2)
The last two bytes of tiling_mode contain the actual tiling mode; the rest are
extra tiling configuration bits. These configuration bits are not necessarily
zero for a linear buffer, so mask them out before checking for linearity
v2: Also fix up evergreen_textured_videofuncs.c
agd5f: remove trailing whitespace
Signed-off-by: Christopher James Halse Rogers <raof@ubuntu.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index ccd102d..abb5076 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -156,7 +156,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (accel_state->planemask & 0xff000000)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
- if (accel_state->dst_obj.tiling_flags == 0) {
+ if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR) {
cb_conf.array_mode = 0;
cb_conf.non_disp_tiling = 1;
}
@@ -335,7 +336,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- if (accel_state->src_obj[0].tiling_flags == 0)
+ if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR)
tex_res.array_mode = 0;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
@@ -378,7 +380,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
if (accel_state->planemask & 0xff000000)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
- if (accel_state->dst_obj.tiling_flags == 0) {
+ if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR) {
cb_conf.array_mode = 0;
cb_conf.non_disp_tiling = 1;
}
@@ -1001,7 +1004,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.base_level = 0;
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
- if (accel_state->src_obj[unit].tiling_flags == 0)
+ if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR)
tex_res.array_mode = 0;
evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain);
@@ -1449,7 +1453,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
cb_conf.rop = 3;
cb_conf.pmask = 0xf;
- if (accel_state->dst_obj.tiling_flags == 0) {
+ if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR) {
cb_conf.array_mode = 0;
cb_conf.non_disp_tiling = 1;
}
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index be00ecf..20805ff 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -246,7 +246,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- if (accel_state->src_obj[0].tiling_flags == 0)
+ if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR)
tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
@@ -279,7 +280,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = pPriv->planev_offset;
tex_res.mip_base = pPriv->planev_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
- if (accel_state->src_obj[0].tiling_flags == 0)
+ if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR)
tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
@@ -302,7 +304,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.base = pPriv->planeu_offset;
tex_res.mip_base = pPriv->planeu_offset;
tex_res.size = tex_res.pitch * (pPriv->h >> 1);
- if (accel_state->src_obj[0].tiling_flags == 0)
+ if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR)
tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
@@ -342,7 +345,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
tex_res.interlaced = 0;
- if (accel_state->src_obj[0].tiling_flags == 0)
+ if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR)
tex_res.array_mode = 1;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
@@ -397,7 +401,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.blend_clamp = 1;
cb_conf.pmask = 0xf;
cb_conf.rop = 3;
- if (accel_state->dst_obj.tiling_flags == 0) {
+ if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
+ RADEON_TILING_LINEAR) {
cb_conf.array_mode = 1;
cb_conf.non_disp_tiling = 1;
}
diff --git a/src/radeon_drm.h b/src/radeon_drm.h
index 042e822..2bbd8fa 100644
--- a/src/radeon_drm.h
+++ b/src/radeon_drm.h
@@ -800,6 +800,8 @@ struct drm_radeon_gem_create {
uint32_t flags;
};
+#define RADEON_TILING_MASK 0xff
+#define RADEON_TILING_LINEAR 0x0
#define RADEON_TILING_MACRO 0x1
#define RADEON_TILING_MICRO 0x2
#define RADEON_TILING_SWAP_16BIT 0x4
commit 67fb82a3f0759b171fea21b475a70fa825693570
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Tue Oct 1 09:35:30 2013 -0400
radeon: fix the non-glamor build harder...
I need to stop pushing patches first thing in the morning.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/radeon_glamor.h b/src/radeon_glamor.h
index 0806f56..36addd7 100644
--- a/src/radeon_glamor.h
+++ b/src/radeon_glamor.h
@@ -91,7 +91,7 @@ static inline Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap) { return
static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }
-static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen) { return NULL; }
+static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; }
#endif
#endif /* RADEON_GLAMOR_H */
commit afc0374fdec3e24ece25805724459463e9a19f5e
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Tue Oct 1 09:32:02 2013 -0400
drm/radeon: fix non-glamor build
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/radeon_glamor.h b/src/radeon_glamor.h
index 6758400..0806f56 100644
--- a/src/radeon_glamor.h
+++ b/src/radeon_glamor.h
@@ -91,7 +91,7 @@ static inline Bool radeon_glamor_pixmap_is_offscreen(PixmapPtr pixmap) { return
static inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }
-static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen) { return NULL }
+static inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen) { return NULL; }
#endif
#endif /* RADEON_GLAMOR_H */
commit 2d791370dfc5570eb74d7a1fb3baf4d4c8ecf243
Author: Dave Airlie <airlied@redhat.com>
Date: Mon Sep 23 07:57:15 2013 +0100
radeon: use glamor Xv support if present.
This creates adaptors using glamor if possible.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/src/radeon_glamor.c b/src/radeon_glamor.c
index 7f00d5b..bd731a8 100644
--- a/src/radeon_glamor.c
+++ b/src/radeon_glamor.c
@@ -355,3 +355,8 @@ radeon_glamor_flush(ScrnInfoPtr pScrn)
if (info->use_glamor)
glamor_block_handler(pScrn->pScreen);
}
+
+XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt)
+{
+ return glamor_xv_init(pScreen, num_adapt);
+}
diff --git a/src/radeon_glamor.h b/src/radeon_glamor.h
index cb76ff4..6758400 100644
--- a/src/radeon_glamor.h
+++ b/src/radeon_glamor.h
@@ -27,6 +27,7 @@
#ifndef RADEON_GLAMOR_H
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