libdrm: Changes to 'debian-unstable'
Rebased ref, commits from common ancestor:
commit 396f92661c9d32085912cbae56849570d344dd1f
Author: Emilio Pozuelo Monfort <pochu@debian.org>
Date: Thu Jun 6 23:15:33 2013 +0200
Upload to unstable
diff --git a/debian/changelog b/debian/changelog
index 33c8206..5c001a9 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,11 @@
-libdrm (2.4.45-3) UNRELEASED; urgency=low
+libdrm (2.4.45-3) unstable; urgency=low
+
+ * Team upload.
* debian/patches/03_build_against_librt.diff:
+ Removed, no longer needed with our current glibc version.
Thanks to Julien Cristau for pointing it out.
+ * Upload to unstable.
-- Emilio Pozuelo Monfort <pochu@debian.org> Thu, 06 Jun 2013 23:13:12 +0200
commit 82ab991c5f25a6a4a33e72b9606ff79d7e1c4338
Author: Emilio Pozuelo Monfort <pochu@debian.org>
Date: Thu Jun 6 23:14:08 2013 +0200
Remove 03_build_against_librt.diff
diff --git a/debian/changelog b/debian/changelog
index c0c519a..33c8206 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,11 @@
+libdrm (2.4.45-3) UNRELEASED; urgency=low
+
+ * debian/patches/03_build_against_librt.diff:
+ + Removed, no longer needed with our current glibc version.
+ Thanks to Julien Cristau for pointing it out.
+
+ -- Emilio Pozuelo Monfort <pochu@debian.org> Thu, 06 Jun 2013 23:13:12 +0200
+
libdrm (2.4.45-2) experimental; urgency=low
[ Sven Joachim ]
diff --git a/debian/patches/03_build_against_librt.diff b/debian/patches/03_build_against_librt.diff
deleted file mode 100644
index 565b6c4..0000000
--- a/debian/patches/03_build_against_librt.diff
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/tests/Makefile.am
-+++ b/tests/Makefile.am
-@@ -10,6 +10,8 @@ check_PROGRAMS = \
- dristat \
- drmstat
-
-+dristat_LDADD = $(CLOCK_LIB)
-+
- SUBDIRS = modeprint
-
- if HAVE_LIBKMS
diff --git a/debian/patches/series b/debian/patches/series
index 2e425c0..8ca2297 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1,2 +1 @@
01_default_perms.diff
-03_build_against_librt.diff
commit 687b4feafcf2696727eb62c0d781ec0de42c723e
Author: Julien Cristau <jcristau@debian.org>
Date: Thu May 30 10:03:45 2013 +0200
Upload to experimental
diff --git a/debian/changelog b/debian/changelog
index 04a89c4..c0c519a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,9 +1,10 @@
-libdrm (2.4.45-2) UNRELEASED; urgency=low
+libdrm (2.4.45-2) experimental; urgency=low
+ [ Sven Joachim ]
* Only build-depend on valgrind on architectures where
valgrind is actually available.
- -- Sven Joachim <svenjoac@gmx.de> Fri, 17 May 2013 17:56:43 +0200
+ -- Julien Cristau <jcristau@debian.org> Thu, 30 May 2013 10:03:37 +0200
libdrm (2.4.45-1) experimental; urgency=low
commit c3b713090840df937677c0827aa76ca798ea9ff3
Author: Sven Joachim <svenjoac@gmx.de>
Date: Fri May 17 18:00:06 2013 +0200
Make valgrind build-dependency archictecture specific
diff --git a/debian/changelog b/debian/changelog
index fdc788c..04a89c4 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+libdrm (2.4.45-2) UNRELEASED; urgency=low
+
+ * Only build-depend on valgrind on architectures where
+ valgrind is actually available.
+
+ -- Sven Joachim <svenjoac@gmx.de> Fri, 17 May 2013 17:56:43 +0200
+
libdrm (2.4.45-1) experimental; urgency=low
* Team upload.
diff --git a/debian/control b/debian/control
index 8175dfc..ec12408 100644
--- a/debian/control
+++ b/debian/control
@@ -13,7 +13,7 @@ Build-Depends:
libpthread-stubs0-dev,
libudev-dev [linux-any],
libpciaccess-dev,
- valgrind,
+ valgrind [amd64 armel armhf i386 mips mipsel powerpc s390x],
Standards-Version: 3.9.4
Section: libs
Vcs-Git: git://git.debian.org/git/pkg-xorg/lib/libdrm
commit 157efcb996b5e5e366947ebd3cdd69f96a7c129f
Author: Emilio Pozuelo Monfort <pochu@debian.org>
Date: Thu May 16 00:17:04 2013 +0200
Upload 2.4.45 to experimental
diff --git a/debian/changelog b/debian/changelog
index 99ca0fc..fdc788c 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,6 @@
-libdrm (2.4.45-1) UNRELEASED; urgency=low
+libdrm (2.4.45-1) experimental; urgency=low
+
+ * Team upload.
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
@@ -11,7 +13,10 @@ libdrm (2.4.45-1) UNRELEASED; urgency=low
[ Timo Aaltonen ]
* control: Bump policy to 3.9.4, no changes.
- -- Julien Cristau <jcristau@debian.org> Tue, 25 Dec 2012 13:17:28 +0100
+ [ Emilio Pozuelo Monfort ]
+ * Upload to experimental.
+
+ -- Emilio Pozuelo Monfort <pochu@debian.org> Thu, 16 May 2013 00:09:59 +0200
libdrm (2.4.40-1) experimental; urgency=low
commit ef470fa9bd9a65897788519f67d4b8fa20750c60
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Wed May 15 21:57:50 2013 +0200
bump changelogs
diff --git a/ChangeLog b/ChangeLog
index 74b1902..51c7a9b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,119 @@
+commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed May 15 19:32:05 2013 +0200
+
+ configure.ac: bump version to 2.4.45 for release
+
+commit e5e51c2110ebf6e1edaa14b7567c5d6a79008a90
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed Apr 24 20:39:45 2013 +0200
+
+ radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
+
+ Signed-off-by: Marek Olšák <maraeo@gmail.com>
+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 96e90aabc4c0238de2f2d245899f991a3b996587
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon May 13 16:14:28 2013 -0400
+
+ radeon: add HAINAN pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit c56729cc1564bb4204ca30a18499a78a39f48892
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon May 13 16:15:17 2013 -0400
+
+ radeon: add HAINAN family
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 040f6b015ef7d9c1bda09f78a8873f6da45d5e95
+Author: Dave Airlie <airlied@redhat.com>
+Date: Thu May 9 12:55:42 2013 +1000
+
+ drm: add qxl drm header file
+
+ Now that this driver is merged add the header file.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 011999927f76a7e9ba8f047fae4b4e084da6c2c3
+Author: Xiang, Haihao <haihao.xiang@intel.com>
+Date: Wed Nov 14 12:46:39 2012 +0800
+
+ intel: Add support for VEBOX ring (v2)
+
+ v2: Fix the test for has_vebox
+
+ Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
+ Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
+
+commit b3a3a77823ada2eb37233678b5a49efaec9b75cb
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Thu Apr 25 16:36:15 2013 -0400
+
+ freedreno: add synchronization between mesa and ddx
+
+ Super-cheezy way to synchronization between mesa and ddx.. the
+ SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
+ GET_BUFINFO gives us a way to retrieve it. We use this to stash
+ the timestamp of the last ISSUEIBCMDS on the buffer.
+
+ To avoid an obscene amount of syscalls, we:
+ 1) Only set the timestamp for buffers w/ an flink name, ie.
+ only buffers shared across processes. This is enough to
+ catch the DRI2 buffers.
+ 2) Only set the timestamp for buffers submitted to the 3d ring
+ and only check the timestamps on buffers submitted to the
+ 2d ring. This should be enough to handle synchronizing of
+ presentation blit. We could do synchronization in the other
+ direction too, but that would be problematic if we are using
+ the 3d ring from DDX, since client side wouldn't know this.
+
+ The waiting on timestamp happens before flush, and setting of
+ timestamp happens after flush. It is transparent to the user
+ of libdrm_freedreno as all the tracking of buffers happens via
+ _emit_reloc()..
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit ec3c257eb6958da493aee6f010f51a07d7ba4160
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Apr 25 14:13:52 2013 -0400
+
+ radeon: add new richland pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 439d7d74320a148a2d53aec1ca28eba672ad9353
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Apr 25 14:12:50 2013 -0400
+
+ radeon: add new SI pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 12464a70ed502d9f401931156005afd717a9992f
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Mon Apr 22 14:50:57 2013 -0400
+
+ Add exynos_fimg2d_test to .gitignore
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit 86709ba5373730a438602459e104bf0a9a49559d
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Mon Apr 22 14:49:28 2013 -0400
+
+ freedreno: add gpu-id property
+
+ Gallium driver will need to query this to figure out whether to load the
+ a2xx or a3xx driver.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
commit 9768af201e9aba2093c80a8da3632fe9e4c044fe
Author: Jerome Glisse <jglisse@redhat.com>
Date: Thu Apr 18 15:01:19 2013 -0400
diff --git a/debian/changelog b/debian/changelog
index 51073b4..99ca0fc 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.44-1) UNRELEASED; urgency=low
+libdrm (2.4.45-1) UNRELEASED; urgency=low
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed May 15 19:32:05 2013 +0200
configure.ac: bump version to 2.4.45 for release
diff --git a/configure.ac b/configure.ac
index 803d99d..21f8d3f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.44],
+ [2.4.45],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit e5e51c2110ebf6e1edaa14b7567c5d6a79008a90
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed Apr 24 20:39:45 2013 +0200
radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index d1fdc4b..a74064c 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -159,7 +159,8 @@ static void surf_minify(struct radeon_surface *surf,
surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
@@ -565,7 +566,8 @@ static void eg_surf_minify(struct radeon_surface *surf,
surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
@@ -1459,7 +1461,8 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
}
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index 2babfd7..bbed56f 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -56,6 +56,7 @@
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
+#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
commit 96e90aabc4c0238de2f2d245899f991a3b996587
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon May 13 16:14:28 2013 -0400
radeon: add HAINAN pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 1530394..01c900f 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -391,3 +391,10 @@ CHIPSET(0x6620, OLAND_6620, OLAND)
CHIPSET(0x6621, OLAND_6621, OLAND)
CHIPSET(0x6623, OLAND_6623, OLAND)
CHIPSET(0x6631, OLAND_6631, OLAND)
+
+CHIPSET(0x6660, HAINAN_6660, HAINAN)
+CHIPSET(0x6663, HAINAN_6663, HAINAN)
+CHIPSET(0x6664, HAINAN_6664, HAINAN)
+CHIPSET(0x6665, HAINAN_6665, HAINAN)
+CHIPSET(0x6667, HAINAN_6667, HAINAN)
+CHIPSET(0x666F, HAINAN_666F, HAINAN)
commit c56729cc1564bb4204ca30a18499a78a39f48892
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon May 13 16:15:17 2013 -0400
radeon: add HAINAN family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 288b5e2..d1fdc4b 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -73,6 +73,7 @@ enum radeon_family {
CHIP_PITCAIRN,
CHIP_VERDE,
CHIP_OLAND,
+ CHIP_HAINAN,
CHIP_LAST,
};
commit 040f6b015ef7d9c1bda09f78a8873f6da45d5e95
Author: Dave Airlie <airlied@redhat.com>
Date: Thu May 9 12:55:42 2013 +1000
drm: add qxl drm header file
Now that this driver is merged add the header file.
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/include/drm/Makefile.am b/include/drm/Makefile.am
index 2923ab4..2bc34d2 100644
--- a/include/drm/Makefile.am
+++ b/include/drm/Makefile.am
@@ -36,8 +36,8 @@ klibdrminclude_HEADERS = \
savage_drm.h \
sis_drm.h \
via_drm.h \
- mach64_drm.h
-
+ mach64_drm.h \
+ qxl_drm.h
if HAVE_VMWGFX
klibdrminclude_HEADERS += vmwgfx_drm.h
diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h
new file mode 100644
index 0000000..5d7de70
--- /dev/null
+++ b/include/drm/qxl_drm.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2013 Red Hat
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef QXL_DRM_H
+#define QXL_DRM_H
+
+#include <stddef.h>
+#include "drm/drm.h"
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ *
+ * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
+ * compatibility Keep fields aligned to their size
+ */
+
+#define QXL_GEM_DOMAIN_CPU 0
+#define QXL_GEM_DOMAIN_VRAM 1
+#define QXL_GEM_DOMAIN_SURFACE 2
+
+#define DRM_QXL_ALLOC 0x00
+#define DRM_QXL_MAP 0x01
+#define DRM_QXL_EXECBUFFER 0x02
+#define DRM_QXL_UPDATE_AREA 0x03
+#define DRM_QXL_GETPARAM 0x04
+#define DRM_QXL_CLIENTCAP 0x05
+
+#define DRM_QXL_ALLOC_SURF 0x06
+
+struct drm_qxl_alloc {
+ uint32_t size;
+ uint32_t handle; /* 0 is an invalid handle */
+};
+
+struct drm_qxl_map {
+ uint64_t offset; /* use for mmap system call */
+ uint32_t handle;
+ uint32_t pad;
+};
+
+/*
+ * dest is the bo we are writing the relocation into
+ * src is bo we are relocating.
+ * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
+ * src_offset)
+ */
+#define QXL_RELOC_TYPE_BO 1
+#define QXL_RELOC_TYPE_SURF 2
+
+struct drm_qxl_reloc {
+ uint64_t src_offset; /* offset into src_handle or src buffer */
+ uint64_t dst_offset; /* offset in dest handle */
+ uint32_t src_handle; /* dest handle to compute address from */
+ uint32_t dst_handle; /* 0 if to command buffer */
+ uint32_t reloc_type;
+ uint32_t pad;
+};
+
+struct drm_qxl_command {
+ uint64_t command; /* void* */
+ uint64_t relocs; /* struct drm_qxl_reloc* */
+ uint32_t type;
+ uint32_t command_size;
+ uint32_t relocs_num;
+ uint32_t pad;
+};
+
+/* XXX: call it drm_qxl_commands? */
+struct drm_qxl_execbuffer {
+ uint32_t flags; /* for future use */
+ uint32_t commands_num;
+ uint64_t commands; /* struct drm_qxl_command* */
+};
+
+struct drm_qxl_update_area {
+ uint32_t handle;
+ uint32_t top;
+ uint32_t left;
+ uint32_t bottom;
+ uint32_t right;
+ uint32_t pad;
+};
+
+#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
+#define QXL_PARAM_MAX_RELOCS 2
+struct drm_qxl_getparam {
+ uint64_t param;
+ uint64_t value;
+};
+
+/* these are one bit values */
+struct drm_qxl_clientcap {
+ uint32_t index;
+ uint32_t pad;
+};
+
+struct drm_qxl_alloc_surf {
+ uint32_t format;
+ uint32_t width;
+ uint32_t height;
+ int32_t stride;
+ uint32_t handle;
+ uint32_t pad;
+};
+
+#define DRM_IOCTL_QXL_ALLOC \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
+
+#define DRM_IOCTL_QXL_MAP \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
+
+#define DRM_IOCTL_QXL_EXECBUFFER \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
+ struct drm_qxl_execbuffer)
+
+#define DRM_IOCTL_QXL_UPDATE_AREA \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
+ struct drm_qxl_update_area)
+
+#define DRM_IOCTL_QXL_GETPARAM \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
+ struct drm_qxl_getparam)
+
+#define DRM_IOCTL_QXL_CLIENTCAP \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
+ struct drm_qxl_clientcap)
+
+#define DRM_IOCTL_QXL_ALLOC_SURF \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
+ struct drm_qxl_alloc_surf)
+
+#endif
commit d54a4da2c89a72f308bb56e20265aa11a5093954
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Thu May 2 09:15:44 2013 +0200
bump changelog
diff --git a/ChangeLog b/ChangeLog
index 4f07fdb..74b1902 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,197 @@
+commit 9768af201e9aba2093c80a8da3632fe9e4c044fe
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Thu Apr 18 15:01:19 2013 -0400
+
+ libdrm 2.4.44
+
+commit 83e77461249d535a77c3ed055d198e26f0c1b390
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Thu Apr 18 15:26:59 2013 +0000
+
+ modetest: Add YUV420 support and fix YVU420 Cb/Cr ordering
+
+ YUV420 support is trivial to add since the code already supports
+ YVU420.
+
+ But it looks like the YVU420 support is a bit broken. The chroma
+ planes are passed in the wrong order to the fill functions, so
+ fix that while were at it.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 3f024f85d816a648473373bccc8ccc915951886a
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Thu Apr 18 15:26:57 2013 +0000
+
+ modetest: Pass format_info to fill_tiles functions
+
+ The fourcc is inside the format_info structure, so if we want to use
+ it inside the various fill_tiles functions, we need to pass down the
+ whole format_info, not just the rgb/yuv infos.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+commit 2c26a106fcfb692badef4c42faaed46508a3d1d3
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Wed Apr 17 19:18:05 2013 +0000
+
+ modetest: Reduce the length of the connector type string
+
+ Spelling out eDP or DP make for a ridicilously long string which plays
+ havoc with formatting. Just say eDP or DP.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+commit 8e56579b203a11c718c5e3da6fdb03b4f9b9fe56
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Wed Apr 17 19:18:04 2013 +0000
+
+ modetest: Print possible_crtcs for planes
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+commit fa2925aa342158037ef972f3ef095442fb1fe430
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Wed Apr 17 19:18:03 2013 +0000
+
+ modetest: Add support for all 16/32 bpp RGB formats
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+commit c2988eb211ecad2db60081f1000cf19b350703db
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Wed Apr 17 19:18:02 2013 +0000
+
+ modetest: Fix pitches, somewhat
+
+ libkms only has the xrgb8888 format, so we're overallocating the bo by
+ quite a lot in some cases. But we still need to get the pitch from the
+ libkms since it's the driver that decides how to align it.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+commit aa4afdf0b3be20aa6037b64f90983ea0146b2893
+Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Date: Thu Nov 1 09:38:42 2012 +0000
+
+ kms: Return a negative error code in kms_bo_create()
+
+ The function returns returns 0 on success or a negative value in case of an
+ error, except when given invalid attributes in which case it returns the
+ positive EINVAL value. Replace that with -EINVAL to allow the caller to detect
+ errors with a < 0 check.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
+
+commit 9fa4a4b1a894fa8fffe2075bc3376b7fa5e18104
+Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Date: Thu Nov 1 09:40:30 2012 +0000
+
+ kms: Make libkms.h usable in C++
+
+ Wrap the header in extern "C" { ... };.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
+
+commit e5d8a9c1d6375feb74feb52f419a025f1abf94d1
+Author: Rob Clark <robdclark@gmail.com>
+Date: Fri Apr 12 11:28:13 2013 -0400
+
+ freedreno: add shifted reloc
+
+ Needed for RB_COPY_DEST_BASE register on a3xx.
+
+ Signed-off-by: Rob Clark <robdclark@gmail.com>
+
+commit a36cdb858e21f287d7b51ded2f211f1c84bda90b
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Mon Apr 8 13:35:37 2013 -0400
+
+ radeon: add si tiling support v5
+
+ v2: Only writte tile index if flags for it is set
+ v3: Remove useless allow2d scanout flags
+ v4: Split radeon_drm.h update to its own patch
+ v5: update against lastest next tree for radeon
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+ Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+
+commit 309cb649a380d25a0eced4f3a0edb55d6b577099
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Mon Apr 8 13:34:54 2013 -0400
+
+ radeon: update radeon_drm.h to kernel last API additions v2
+
+ v2: sync with radeon-next tree for 3.10
+
+ http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+ Reviewed-by: Christian König <christian.koenig@amd.com>
+
+commit b7bb9e929786eb8bae86cf50f54dcb94bfa7ad46
+Author: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Wed Apr 3 18:25:12 2013 +0200
+
+ intel-decode: Fix gen6 HIER_DEPTH_BUFFER decoding
+
+ It accidentally used the cmd id for the gen7 command and had an
+ outdated lenght field. Spotted while trying to make sense of an ivb
+ error_state from mesa 7.11 ...
+
+ Reviewed-by: Eric Anholt <eric@anholt.net>
+ Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit ca678bc073462623cfc89dea80271bc361f1655f
+Author: Kenneth Graunke <kenneth@whitecape.org>
+Date: Fri Mar 1 15:37:01 2013 -0800
+
+ intel: Fix Haswell CRW PCI IDs.
+
+ The second digit was off by one, which meant we accidentally treated
+ GT(n) as GT(n-1). This also meant no support for GT1 at all.
+
+ Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 1eb2860b4bd0306dddc5b2f2dc7403aa65c5e476
+Author: Daniel Kurtz <djkurtz@chromium.org>
+Date: Thu Mar 28 14:05:40 2013 +0800
+
+ drm: Fix error message in drmWaitVBlank
+
+ If clock_gettime did fail, it would return -1 and set errno.
+ What we really want to strerror() is the errno.
+
+ Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
+
+commit 99105e765c31b598746b849e66e7a9106dcefa24
+Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
+Date: Wed Mar 27 14:06:43 2013 +0100
+
+ makefiles: Add missing headers.
+
+ I even compile time tested this on a panda with make dist!
+
+ Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
+
+commit 6113c3daa8826a11546693af07dee3313e09a167
+Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
+Date: Wed Mar 27 13:55:54 2013 +0100
+
+ Remove unused header xf86mm.h.
+
+ it's not even shipped in the tarball.
+
+ Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
+
commit c005f043dcb4df5ed8a36b9f4b70fcf9e92d52a5
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Wed Mar 27 10:42:20 2013 +0100
diff --git a/debian/changelog b/debian/changelog
index 8f03c70..51073b4 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.43-1) UNRELEASED; urgency=low
+libdrm (2.4.44-1) UNRELEASED; urgency=low
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
commit 011999927f76a7e9ba8f047fae4b4e084da6c2c3
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed Nov 14 12:46:39 2012 +0800
intel: Add support for VEBOX ring (v2)
v2: Fix the test for has_vebox
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7e9e9bd..aa983f3 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -303,6 +303,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_LLC 17
#define I915_PARAM_HAS_ALIASING_PPGTT 18
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
+#define I915_PARAM_HAS_VEBOX 22
typedef struct drm_i915_getparam {
int param;
@@ -649,6 +650,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_VEBOX (4<<0)
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
* Gen6+ only supports relative addressing to dynamic state (default) and
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index d21547e..3c73068 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -125,6 +125,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int has_wait_timeout : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
+ unsigned int has_vebox : 1;
bool fenced_relocs;
FILE *aub_file;
@@ -2213,6 +2214,10 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
if (!bufmgr_gem->has_bsd)
return -EINVAL;
break;
+ case I915_EXEC_VEBOX:
+ if (!bufmgr_gem->has_vebox)
+ return -EINVAL;
+ break;
case I915_EXEC_RENDER:
case I915_EXEC_DEFAULT:
break;
@@ -3126,6 +3131,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
} else
bufmgr_gem->has_llc = *gp.value;
+ gp.param = I915_PARAM_HAS_VEBOX;
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
+
if (bufmgr_gem->gen < 4) {
gp.param = I915_PARAM_NUM_FENCES_AVAIL;
gp.value = &bufmgr_gem->available_fences;
commit b3a3a77823ada2eb37233678b5a49efaec9b75cb
Author: Rob Clark <robclark@freedesktop.org>
Date: Thu Apr 25 16:36:15 2013 -0400
freedreno: add synchronization between mesa and ddx
Super-cheezy way to synchronization between mesa and ddx.. the
SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
GET_BUFINFO gives us a way to retrieve it. We use this to stash
the timestamp of the last ISSUEIBCMDS on the buffer.
To avoid an obscene amount of syscalls, we:
1) Only set the timestamp for buffers w/ an flink name, ie.
only buffers shared across processes. This is enough to
catch the DRI2 buffers.
2) Only set the timestamp for buffers submitted to the 3d ring
and only check the timestamps on buffers submitted to the
2d ring. This should be enough to handle synchronizing of
presentation blit. We could do synchronization in the other
direction too, but that would be problematic if we are using
the 3d ring from DDX, since client side wouldn't know this.
The waiting on timestamp happens before flush, and setting of
timestamp happens after flush. It is transparent to the user
of libdrm_freedreno as all the tracking of buffers happens via
_emit_reloc()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c
index 4f566e1..be386b4 100644
--- a/freedreno/freedreno_bo.c
+++ b/freedreno/freedreno_bo.c
@@ -165,12 +165,17 @@ struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
struct drm_gem_open req = {
.name = name,
};
+ struct fd_bo *bo;
if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) {
return NULL;
}
- return bo_from_handle(dev, req.size, req.handle);
+ bo = bo_from_handle(dev, req.size, req.handle);
+ if (bo)
+ bo->name = name;
+
+ return bo;
}
struct fd_bo * fd_bo_ref(struct fd_bo *bo)
@@ -272,3 +277,64 @@ uint32_t fd_bo_gpuaddr(struct fd_bo *bo, uint32_t offset)
}
return bo->gpuaddr + offset;
}
+
+/*
+ * Super-cheezy way to synchronization between mesa and ddx.. the
+ * SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
+ * GET_BUFINFO gives us a way to retrieve it. We use this to stash
+ * the timestamp of the last ISSUEIBCMDS on the buffer.
+ *
+ * To avoid an obscene amount of syscalls, we:
+ * 1) Only set the timestamp for buffers w/ an flink name, ie.
+ * only buffers shared across processes. This is enough to
+ * catch the DRI2 buffers.
+ * 2) Only set the timestamp for buffers submitted to the 3d ring
+ * and only check the timestamps on buffers submitted to the
+ * 2d ring. This should be enough to handle synchronizing of
+ * presentation blit. We could do synchronization in the other
+ * direction too, but that would be problematic if we are using
+ * the 3d ring from DDX, since client side wouldn't know this.
+ *
+ * The waiting on timestamp happens before flush, and setting of
+ * timestamp happens after flush. It is transparent to the user
+ * of libdrm_freedreno as all the tracking of buffers happens via
+ * _emit_reloc()..
+ */
+
+void fb_bo_set_timestamp(struct fd_bo *bo, uint32_t timestamp)
+{
+ if (bo->name) {
+ struct drm_kgsl_gem_active req = {
+ .handle = bo->handle,
+ .active = timestamp,
+ };
+ int ret;
+
+ ret = drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_SET_ACTIVE,
+ &req, sizeof(req));
+ if (ret) {
+ ERROR_MSG("set active failed: %s", strerror(errno));
+ }
+ }
+}
+
+uint32_t fd_bo_get_timestamp(struct fd_bo *bo)
+{
+ uint32_t timestamp = 0;
+ if (bo->name) {
+ struct drm_kgsl_gem_bufinfo req = {
+ .handle = bo->handle,
+ };
+ int ret;
+
+ ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
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