mesa: Changes to 'ubuntu-raring'
Makefile.am | 2
bin/.cherry-ignore | 16
configure.ac | 58 +-
debian/changelog | 9
debian/patches/CVE-2013-1872.patch | 78 ---
debian/patches/CVE-2013-1993.patch | 45 -
debian/patches/add-more-reserved-hsw-ids.diff | 231 ---------
debian/patches/add-vlv-ids.diff | 97 ---
debian/patches/fix-hsw-gt3-names.diff | 238 ---------
debian/patches/fix-missing-gt3-id.diff | 26 -
debian/patches/revert-a64c1eb9b110.diff | 3
debian/patches/series | 8
docs/relnotes-9.1.3.html | 4
docs/relnotes-9.1.4.html | 319 +++++++++++++
include/pci_ids/i965_pci_ids.h | 53 +-
include/pci_ids/radeonsi_pci_ids.h | 7
scons/custom.py | 3
src/egl/drivers/dri2/platform_android.c | 16
src/gallium/auxiliary/gallivm/lp_bld_debug.cpp | 4
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 6
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 13
src/gallium/auxiliary/util/u_vbuf.c | 3
src/gallium/drivers/nv50/nv50_context.c | 1
src/gallium/drivers/nvc0/nvc0_screen.c | 1
src/gallium/drivers/nvc0/nvc0_video.c | 8
src/gallium/drivers/nvc0/nvc0_video_ppp.c | 2
src/gallium/drivers/nvc0/nvc0_video_vp.c | 3
src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c | 8
src/gallium/drivers/r600/r600_state_common.c | 3
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 2
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 1
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 1
src/gallium/drivers/radeonsi/radeonsi_shader.c | 7
src/gallium/drivers/radeonsi/radeonsi_shader.h | 6
src/gallium/drivers/radeonsi/si_state.c | 8
src/gallium/drivers/radeonsi/si_state.h | 1
src/gallium/drivers/radeonsi/si_state_draw.c | 19
src/gallium/state_trackers/glx/xlib/glx_api.c | 26 -
src/gallium/state_trackers/glx/xlib/xm_api.c | 6
src/gallium/targets/dri-i915/Makefile.am | 10
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3
src/gallium/winsys/radeon/drm/radeon_winsys.h | 1
src/glsl/ast_to_hir.cpp | 48 +
src/glsl/builtin_variables.cpp | 2
src/glsl/glsl_parser.yy | 6
src/glx/XF86dri.c | 15
src/mapi/glapi/gen/es_EXT.xml | 23
src/mesa/drivers/common/meta.c | 4
src/mesa/drivers/dri/common/xmlpool/Makefile.am | 2
src/mesa/drivers/dri/i915/i915_state.c | 9
src/mesa/drivers/dri/i965/brw_cc.c | 5
src/mesa/drivers/dri/i965/brw_context.c | 6
src/mesa/drivers/dri/i965/brw_context.h | 9
src/mesa/drivers/dri/i965/brw_draw_upload.c | 8
src/mesa/drivers/dri/i965/brw_fs.cpp | 44 -
src/mesa/drivers/dri/i965/brw_fs.h | 3
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 6
src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp | 2
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 8
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp | 6
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 10
src/mesa/drivers/dri/i965/brw_lower_texture_gradients.cpp | 1
src/mesa/drivers/dri/i965/brw_misc_state.c | 2
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 39 +
src/mesa/drivers/dri/i965/brw_vec4.cpp | 2
src/mesa/drivers/dri/i965/gen6_cc.c | 5
src/mesa/drivers/dri/i965/gen6_urb.c | 18
src/mesa/drivers/dri/i965/gen7_urb.c | 35 -
src/mesa/drivers/dri/intel/intel_chipset.h | 113 +++-
src/mesa/drivers/dri/intel/intel_context.c | 62 ++
src/mesa/drivers/dri/intel/intel_context.h | 1
src/mesa/drivers/dri/intel/intel_fbo.c | 27 -
src/mesa/drivers/dri/intel/intel_fbo.h | 1
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 84 ++-
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 36 +
src/mesa/drivers/dri/intel/intel_screen.c | 10
src/mesa/drivers/dri/nouveau/nouveau_fbo.c | 10
src/mesa/drivers/dri/nouveau/nv04_state_raster.c | 3
src/mesa/drivers/dri/nouveau/nv10_state_raster.c | 4
src/mesa/drivers/dri/r200/r200_state.c | 3
src/mesa/drivers/dri/radeon/radeon_fbo.c | 24
src/mesa/drivers/dri/radeon/radeon_state.c | 4
src/mesa/drivers/x11/fakeglx.c | 24
src/mesa/main/api_arrayelt.c | 2
src/mesa/main/attrib.c | 1
src/mesa/main/bufferobj.c | 10
src/mesa/main/compiler.h | 2
src/mesa/main/config.h | 3
src/mesa/main/enable.c | 5
src/mesa/main/fbobject.c | 72 ++
src/mesa/main/fbobject.h | 5
src/mesa/main/framebuffer.c | 78 +--
src/mesa/main/get.c | 6
src/mesa/main/get_hash_params.py | 2
src/mesa/main/mtypes.h | 16
src/mesa/main/stencil.c | 9
src/mesa/main/stencil.h | 14
src/mesa/main/teximage.c | 27 -
src/mesa/main/varray.c | 29 +
src/mesa/main/varray.h | 2
src/mesa/main/version.h | 4
src/mesa/program/ir_to_mesa.cpp | 2
src/mesa/state_tracker/st_atom_constbuf.c | 20
src/mesa/state_tracker/st_atom_depth.c | 7
src/mesa/state_tracker/st_cb_fbo.c | 22
src/mesa/state_tracker/st_draw.c | 4
src/mesa/state_tracker/st_extensions.c | 76 +--
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2
src/mesa/swrast/s_stencil.c | 6
src/mesa/swrast/s_texrender.c | 38 -
src/mesa/vbo/vbo_exec.c | 20
src/mesa/vbo/vbo_exec.h | 1
src/mesa/vbo/vbo_exec_array.c | 20
src/mesa/vbo/vbo_primitive_restart.c | 3
114 files changed, 1327 insertions(+), 1261 deletions(-)
New commits:
commit b5b28e7749a3df393732f1edfcd8936b0778ff30
Author: Timo Aaltonen <tjaalton@ubuntu.com>
Date: Wed Jul 3 14:17:47 2013 +0300
New upstream bugfix release 9.1.4. (LP: #1197363)
* New upstream bugfix release 9.1.4. (LP: #1197363)
- fix a GPU hang with GT3. (LP: #1197316)
* Dropped patches that are included in this release
* revert-a64c1eb9b110.diff: updated.
diff --git a/debian/changelog b/debian/changelog
index 711cbd9..da5870d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,12 @@
+mesa (9.1.4-0ubuntu0.1) UNRELEASED; urgency=low
+
+ * New upstream bugfix release 9.1.4. (LP: #1197363)
+ - fix a GPU hang with GT3. (LP: #1197316)
+ * Dropped patches that are included in this release
+ * revert-a64c1eb9b110.diff: updated.
+
+ -- Timo Aaltonen <tjaalton@ubuntu.com> Wed, 03 Jul 2013 13:54:33 +0300
+
mesa (9.1.3-0ubuntu0.4) raring-proposed; urgency=low
* Added patches to add/fix Haswell pci-id's (LP: #1175533)
diff --git a/debian/patches/CVE-2013-1872.patch b/debian/patches/CVE-2013-1872.patch
deleted file mode 100644
index 530b851..0000000
--- a/debian/patches/CVE-2013-1872.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-Description: fix denial of service and possible code execution via
- out-of-bands access
-Origin: backport, http://cgit.freedesktop.org/mesa/mesa/commit/?id=0677ea063cd96adefe87c1fb01ef7c66d905535b
-Bug: https://bugs.freedesktop.org/show_bug.cgi?id=59429
-
-Index: mesa-9.1.3/src/mesa/drivers/dri/i965/brw_fs.cpp
-===================================================================
---- mesa-9.1.3.orig/src/mesa/drivers/dri/i965/brw_fs.cpp 2013-06-18 13:53:12.200524978 -0400
-+++ mesa-9.1.3/src/mesa/drivers/dri/i965/brw_fs.cpp 2013-06-18 13:53:12.196524978 -0400
-@@ -786,6 +786,7 @@
- import_uniforms_callback,
- variable_ht);
- this->params_remap = v->params_remap;
-+ this->nr_params_remap = v->nr_params_remap;
- }
-
- /* Our support for uniforms is piggy-backed on the struct
-@@ -1458,6 +1459,7 @@
- {
- if (dispatch_width == 8) {
- this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
-+ this->nr_params_remap = c->prog_data.nr_params;
-
- for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
- this->params_remap[i] = -1;
-@@ -1472,7 +1474,14 @@
- if (inst->src[i].file != UNIFORM)
- continue;
-
-- assert(constant_nr < (int)c->prog_data.nr_params);
-+ /* Section 5.11 of the OpenGL 4.3 spec says:
-+ *
-+ * "Out-of-bounds reads return undefined values, which include
-+ * values from other variables of the active program or zero."
-+ */
-+ if (constant_nr < 0 || constant_nr >= (int)c->prog_data.nr_params) {
-+ constant_nr = 0;
-+ }
-
- /* For now, set this to non-negative. We'll give it the
- * actual new number in a moment, in order to keep the
-@@ -1520,6 +1529,10 @@
- if (inst->src[i].file != UNIFORM)
- continue;
-
-+ /* as above alias to 0 */
-+ if (constant_nr < 0 || constant_nr >= (int)this->nr_params_remap) {
-+ constant_nr = 0;
-+ }
- assert(this->params_remap[constant_nr] != -1);
- inst->src[i].reg = this->params_remap[constant_nr];
- inst->src[i].reg_offset = 0;
-Index: mesa-9.1.3/src/mesa/drivers/dri/i965/brw_fs.h
-===================================================================
---- mesa-9.1.3.orig/src/mesa/drivers/dri/i965/brw_fs.h 2013-06-18 13:53:12.200524978 -0400
-+++ mesa-9.1.3/src/mesa/drivers/dri/i965/brw_fs.h 2013-06-18 13:53:12.196524978 -0400
-@@ -431,6 +431,7 @@
- * uniform index.
- */
- int *params_remap;
-+ int nr_params_remap;
-
- struct hash_table *variable_ht;
- fs_reg frag_depth;
-Index: mesa-9.1.3/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
-===================================================================
---- mesa-9.1.3.orig/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 2013-06-18 13:53:12.200524978 -0400
-+++ mesa-9.1.3/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 2013-06-18 13:53:12.196524978 -0400
-@@ -2273,6 +2273,9 @@
- this->virtual_grf_use = NULL;
- this->live_intervals_valid = false;
-
-+ this->params_remap = NULL;
-+ this->nr_params_remap = 0;
-+
- this->force_uncompressed_stack = 0;
- this->force_sechalf_stack = 0;
- }
diff --git a/debian/patches/CVE-2013-1993.patch b/debian/patches/CVE-2013-1993.patch
deleted file mode 100644
index 377839f..0000000
--- a/debian/patches/CVE-2013-1993.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-Description: fix denial of service and possible code execution via
- integer overflows
-Origin: upstream, http://cgit.freedesktop.org/mesa/mesa/commit?id=2e5a268f18be30df15aed0b44b01a18a37fb5df4
-Origin: upstream, http://cgit.freedesktop.org/mesa/mesa/commit?id=306f630e676eb901789dd09a0f30d7e7fa941ebe
-
-Index: mesa-9.1.3/src/glx/XF86dri.c
-===================================================================
---- mesa-9.1.3.orig/src/glx/XF86dri.c 2013-02-26 15:00:02.000000000 -0500
-+++ mesa-9.1.3/src/glx/XF86dri.c 2013-06-18 13:50:48.892526345 -0400
-@@ -43,6 +43,7 @@
- #include <X11/extensions/Xext.h>
- #include <X11/extensions/extutil.h>
- #include "xf86dristr.h"
-+#include <limits.h>
-
- static XExtensionInfo _xf86dri_info_data;
- static XExtensionInfo *xf86dri_info = &_xf86dri_info_data;
-@@ -201,7 +202,11 @@
- }
-
- if (rep.length) {
-- if (!(*busIdString = calloc(rep.busIdStringLength + 1, 1))) {
-+ if (rep.busIdStringLength < INT_MAX)
-+ *busIdString = calloc(rep.busIdStringLength + 1, 1);
-+ else
-+ *busIdString = NULL;
-+ if (*busIdString == NULL) {
- _XEatData(dpy, ((rep.busIdStringLength + 3) & ~3));
- UnlockDisplay(dpy);
- SyncHandle();
-@@ -300,9 +305,11 @@
- *ddxDriverPatchVersion = rep.ddxDriverPatchVersion;
-
- if (rep.length) {
-- if (!
-- (*clientDriverName =
-- calloc(rep.clientDriverNameLength + 1, 1))) {
-+ if (rep.clientDriverNameLength < INT_MAX)
-+ *clientDriverName = calloc(rep.clientDriverNameLength + 1, 1);
-+ else
-+ *clientDriverName = NULL;
-+ if (*clientDriverName == NULL) {
- _XEatData(dpy, ((rep.clientDriverNameLength + 3) & ~3));
- UnlockDisplay(dpy);
- SyncHandle();
diff --git a/debian/patches/add-more-reserved-hsw-ids.diff b/debian/patches/add-more-reserved-hsw-ids.diff
deleted file mode 100644
index 294e389..0000000
--- a/debian/patches/add-more-reserved-hsw-ids.diff
+++ /dev/null
@@ -1,231 +0,0 @@
-commit ce67fb4715e0c2fab01de33da475ef4705622020
-Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
-Date: Mon May 13 17:53:39 2013 -0300
-
- i965: Adding more reserved PCI IDs for Haswell.
-
- At DDX commit Chris mentioned the tendency we have of finding out more
- PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
-
- NOTE: This is a candidate for stable branches.
-
- Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
- Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
- Acked-by: Kenneth Graunke <kenneth@whitecape.org>
-
-diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
-index 3e9765c..808eb4e 100644
---- a/include/pci_ids/i965_pci_ids.h
-+++ b/include/pci_ids/i965_pci_ids.h
-@@ -35,6 +35,12 @@ CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3)
- CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1)
- CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2)
- CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3)
-+CHIPSET(0x040B, HASWELL_B_GT1, hsw_gt1)
-+CHIPSET(0x041B, HASWELL_B_GT2, hsw_gt2)
-+CHIPSET(0x042B, HASWELL_B_GT3, hsw_gt3)
-+CHIPSET(0x040E, HASWELL_E_GT1, hsw_gt1)
-+CHIPSET(0x041E, HASWELL_E_GT2, hsw_gt2)
-+CHIPSET(0x042E, HASWELL_E_GT3, hsw_gt3)
- CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1)
- CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2)
- CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3)
-@@ -44,6 +50,12 @@ CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3)
- CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1)
- CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2)
- CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3)
-+CHIPSET(0x0C0B, HASWELL_SDV_B_GT1, hsw_gt1)
-+CHIPSET(0x0C1B, HASWELL_SDV_B_GT2, hsw_gt2)
-+CHIPSET(0x0C2B, HASWELL_SDV_B_GT3, hsw_gt3)
-+CHIPSET(0x0C0E, HASWELL_SDV_E_GT1, hsw_gt1)
-+CHIPSET(0x0C1E, HASWELL_SDV_E_GT2, hsw_gt2)
-+CHIPSET(0x0C2E, HASWELL_SDV_E_GT3, hsw_gt3)
- CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1)
- CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2)
- CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3)
-@@ -53,6 +65,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3)
- CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
- CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
- CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3)
-+CHIPSET(0x0A0B, HASWELL_ULT_B_GT1, hsw_gt1)
-+CHIPSET(0x0A1B, HASWELL_ULT_B_GT2, hsw_gt2)
-+CHIPSET(0x0A2B, HASWELL_ULT_B_GT3, hsw_gt3)
-+CHIPSET(0x0A0E, HASWELL_ULT_E_GT1, hsw_gt1)
-+CHIPSET(0x0A1E, HASWELL_ULT_E_GT2, hsw_gt2)
-+CHIPSET(0x0A2E, HASWELL_ULT_E_GT3, hsw_gt3)
- CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1)
- CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2)
- CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3)
-@@ -62,6 +80,12 @@ CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3)
- CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
- CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
- CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3)
-+CHIPSET(0x0D0B, HASWELL_CRW_B_GT1, hsw_gt1)
-+CHIPSET(0x0D1B, HASWELL_CRW_B_GT2, hsw_gt2)
-+CHIPSET(0x0D2B, HASWELL_CRW_B_GT3, hsw_gt3)
-+CHIPSET(0x0D0E, HASWELL_CRW_E_GT1, hsw_gt1)
-+CHIPSET(0x0D1E, HASWELL_CRW_E_GT2, hsw_gt2)
-+CHIPSET(0x0D2E, HASWELL_CRW_E_GT3, hsw_gt3)
- CHIPSET(0x0F31, BAYTRAIL_M_1, byt)
- CHIPSET(0x0F32, BAYTRAIL_M_2, byt)
- CHIPSET(0x0F33, BAYTRAIL_M_3, byt)
-diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
-index ee735bb..1e98cf4 100644
---- a/src/mesa/drivers/dri/intel/intel_chipset.h
-+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
-@@ -102,6 +102,12 @@
- #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
- #define PCI_CHIP_HASWELL_S_GT2 0x041A
- #define PCI_CHIP_HASWELL_S_GT3 0x042A
-+#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
-+#define PCI_CHIP_HASWELL_B_GT2 0x041B
-+#define PCI_CHIP_HASWELL_B_GT3 0x042B
-+#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
-+#define PCI_CHIP_HASWELL_E_GT2 0x041E
-+#define PCI_CHIP_HASWELL_E_GT3 0x042E
- #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
- #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
- #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
-@@ -111,6 +117,12 @@
- #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
- #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
- #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
-+#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
-+#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
-+#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
-+#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
-+#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
-+#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
- #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
- #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
- #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
-@@ -120,6 +132,12 @@
- #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
- #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
- #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
-+#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
-+#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
-+#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
-+#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
-+#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
-+#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
- #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
- #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
- #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
-@@ -129,6 +147,12 @@
- #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
- #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
- #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
-+#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
-+#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
-+#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
-+#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
-+#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
-+#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
-
- #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
- devid == PCI_CHIP_I915_GM || \
-@@ -209,39 +233,63 @@
- #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
- devid == PCI_CHIP_HASWELL_M_GT1 || \
- devid == PCI_CHIP_HASWELL_S_GT1 || \
-+ devid == PCI_CHIP_HASWELL_B_GT1 || \
-+ devid == PCI_CHIP_HASWELL_E_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
-+ devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
-+ devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
-+ devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
-+ devid == PCI_CHIP_HASWELL_ULT_E_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
-- devid == PCI_CHIP_HASWELL_CRW_S_GT1)
-+ devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
-+ devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
-+ devid == PCI_CHIP_HASWELL_CRW_E_GT1)
- #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
- devid == PCI_CHIP_HASWELL_M_GT2 || \
- devid == PCI_CHIP_HASWELL_S_GT2 || \
-+ devid == PCI_CHIP_HASWELL_B_GT2 || \
-+ devid == PCI_CHIP_HASWELL_E_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
-+ devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
-+ devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
-+ devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
-+ devid == PCI_CHIP_HASWELL_ULT_E_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-- devid == PCI_CHIP_HASWELL_CRW_S_GT2)
-+ devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
-+ devid == PCI_CHIP_HASWELL_CRW_B_GT2 || \
-+ devid == PCI_CHIP_HASWELL_CRW_E_GT2)
- #define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \
- devid == PCI_CHIP_HASWELL_M_GT3 || \
- devid == PCI_CHIP_HASWELL_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_B_GT3 || \
-+ devid == PCI_CHIP_HASWELL_E_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
-+ devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
-+ devid == PCI_CHIP_HASWELL_ULT_E_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
-- devid == PCI_CHIP_HASWELL_CRW_S_GT3)
-+ devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
-+ devid == PCI_CHIP_HASWELL_CRW_E_GT3)
-
- #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid) || \
-diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
-index 88cc247..ab7f80b 100644
---- a/src/mesa/drivers/dri/intel/intel_context.c
-+++ b/src/mesa/drivers/dri/intel/intel_context.c
-@@ -235,6 +235,32 @@ intelGetString(struct gl_context * ctx, GLenum name)
- case PCI_CHIP_HASWELL_CRW_S_GT3:
- chipset = "Intel(R) Haswell Server";
- break;
-+ case PCI_CHIP_HASWELL_B_GT1:
-+ case PCI_CHIP_HASWELL_B_GT2:
-+ case PCI_CHIP_HASWELL_B_GT3:
-+ case PCI_CHIP_HASWELL_SDV_B_GT1:
-+ case PCI_CHIP_HASWELL_SDV_B_GT2:
-+ case PCI_CHIP_HASWELL_SDV_B_GT3:
-+ case PCI_CHIP_HASWELL_ULT_B_GT1:
-+ case PCI_CHIP_HASWELL_ULT_B_GT2:
-+ case PCI_CHIP_HASWELL_ULT_B_GT3:
-+ case PCI_CHIP_HASWELL_CRW_B_GT1:
-+ case PCI_CHIP_HASWELL_CRW_B_GT2:
-+ case PCI_CHIP_HASWELL_CRW_B_GT3:
-+ case PCI_CHIP_HASWELL_E_GT1:
-+ case PCI_CHIP_HASWELL_E_GT2:
-+ case PCI_CHIP_HASWELL_E_GT3:
-+ case PCI_CHIP_HASWELL_SDV_E_GT1:
-+ case PCI_CHIP_HASWELL_SDV_E_GT2:
-+ case PCI_CHIP_HASWELL_SDV_E_GT3:
-+ case PCI_CHIP_HASWELL_ULT_E_GT1:
-+ case PCI_CHIP_HASWELL_ULT_E_GT2:
-+ case PCI_CHIP_HASWELL_ULT_E_GT3:
-+ case PCI_CHIP_HASWELL_CRW_E_GT1:
-+ case PCI_CHIP_HASWELL_CRW_E_GT2:
-+ case PCI_CHIP_HASWELL_CRW_E_GT3:
-+ chipset = "Intel(R) Haswell";
-+ break;
- default:
- chipset = "Unknown Intel Chipset";
- break;
diff --git a/debian/patches/add-vlv-ids.diff b/debian/patches/add-vlv-ids.diff
deleted file mode 100644
index 5aae0ca..0000000
--- a/debian/patches/add-vlv-ids.diff
+++ /dev/null
@@ -1,97 +0,0 @@
-commit e7965598b7cc1123847e5c87ab16745145e849e2
-Author: Kenneth Graunke <kenneth@whitecape.org>
-Date: Wed Oct 3 14:26:29 2012 -0700
-
- i965: Enable the Bay Trail platform.
-
- This patch adds PCI IDs for Bay Trail (sometimes called Valley View).
- As far as the 3D driver is concerned, it's very similar to Ivybridge,
- so the existing code should work just fine.
-
- Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
-
-diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
-index 1e388f8..9a2da61 100644
---- a/include/pci_ids/i965_pci_ids.h
-+++ b/include/pci_ids/i965_pci_ids.h
-@@ -62,3 +62,8 @@ CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
- CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
- CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
- CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0F31, BAYTRAIL_M_1, byt)
-+CHIPSET(0x0F32, BAYTRAIL_M_2, byt)
-+CHIPSET(0x0F33, BAYTRAIL_M_3, byt)
-+CHIPSET(0x0157, BAYTRAIL_M_4, byt)
-+CHIPSET(0x0155, BAYTRAIL_D, byt)
-diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
-index 885f6c2..04753dd 100644
---- a/src/mesa/drivers/dri/intel/intel_chipset.h
-+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
-@@ -87,6 +87,12 @@
- #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
- #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
-
-+#define PCI_CHIP_BAYTRAIL_M_1 0x0F31
-+#define PCI_CHIP_BAYTRAIL_M_2 0x0F32
-+#define PCI_CHIP_BAYTRAIL_M_3 0x0F33
-+#define PCI_CHIP_BAYTRAIL_M_4 0x0157
-+#define PCI_CHIP_BAYTRAIL_D 0x0155
-+
- #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
- #define PCI_CHIP_HASWELL_GT2 0x0412
- #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
-@@ -190,7 +196,14 @@
-
- #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
-
-+#define IS_BAYTRAIL(devid) (devid == PCI_CHIP_BAYTRAIL_M_1 || \
-+ devid == PCI_CHIP_BAYTRAIL_M_2 || \
-+ devid == PCI_CHIP_BAYTRAIL_M_3 || \
-+ devid == PCI_CHIP_BAYTRAIL_M_4 || \
-+ devid == PCI_CHIP_BAYTRAIL_D)
-+
- #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
-+ IS_BAYTRAIL(devid) || \
- IS_HASWELL(devid))
-
- #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
-diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
-index ba7d4b6..0a1dd75 100644
---- a/src/mesa/drivers/dri/intel/intel_context.c
-+++ b/src/mesa/drivers/dri/intel/intel_context.c
-@@ -186,6 +186,13 @@ intelGetString(struct gl_context * ctx, GLenum name)
- case PCI_CHIP_IVYBRIDGE_S_GT2:
- chipset = "Intel(R) Ivybridge Server";
- break;
-+ case PCI_CHIP_BAYTRAIL_M_1:
-+ case PCI_CHIP_BAYTRAIL_M_2:
-+ case PCI_CHIP_BAYTRAIL_M_3:
-+ case PCI_CHIP_BAYTRAIL_M_4:
-+ case PCI_CHIP_BAYTRAIL_D:
-+ chipset = "Intel(R) Bay Trail";
-+ break;
- case PCI_CHIP_HASWELL_GT1:
- case PCI_CHIP_HASWELL_GT2:
- case PCI_CHIP_HASWELL_GT2_PLUS:
-@@ -682,6 +689,9 @@ intelInitContext(struct intel_context *intel,
-
- if (IS_HASWELL(devID)) {
- intel->is_haswell = true;
-+ } else if (IS_BAYTRAIL(devID)) {
-+ intel->is_baytrail = true;
-+ intel->gt = 1;
- } else if (IS_G4X(devID)) {
- intel->is_g4x = true;
- } else if (IS_945(devID)) {
-diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
-index 4591ab7..c0f07ff 100644
---- a/src/mesa/drivers/dri/intel/intel_context.h
-+++ b/src/mesa/drivers/dri/intel/intel_context.h
-@@ -236,6 +236,7 @@ struct intel_context
- int gt;
- bool needs_ff_sync;
- bool is_haswell;
-+ bool is_baytrail;
- bool is_g4x;
- bool is_945;
- bool has_separate_stencil;
diff --git a/debian/patches/fix-hsw-gt3-names.diff b/debian/patches/fix-hsw-gt3-names.diff
deleted file mode 100644
index 234b776..0000000
--- a/debian/patches/fix-hsw-gt3-names.diff
+++ /dev/null
@@ -1,238 +0,0 @@
-commit f1d2b373177dbbb582cefb0d6c88994073fab652
-Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
-Date: Fri Aug 10 12:06:37 2012 -0300
-
- i965: make GT3 machines work as GT3 instead of GT2
-
- We were not allowed to say the "GT3" name, but we really needed to
- have the PCI IDs because too many people had such machines, so we had
- to make the GT3 machines work as GT2.
-
- Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :)
-
- NOTE: This is a candidate for stable branches.
-
- Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
- Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
-
-diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
-index 9a2da61..3e9765c 100644
---- a/include/pci_ids/i965_pci_ids.h
-+++ b/include/pci_ids/i965_pci_ids.h
-@@ -28,40 +28,40 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
- CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2)
- CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
- CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
--CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0422, HASWELL_GT3, hsw_gt3)
- CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
- CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
--CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3)
- CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1)
- CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2)
--CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3)
- CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1)
- CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2)
--CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3)
- CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1)
- CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2)
--CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3)
- CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1)
- CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2)
--CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3)
- CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1)
- CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2)
--CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3)
- CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1)
- CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2)
--CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3)
- CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
- CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
--CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3)
- CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1)
- CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2)
--CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3)
- CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1)
- CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2)
--CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3)
- CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
- CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
--CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
-+CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3)
- CHIPSET(0x0F31, BAYTRAIL_M_1, byt)
- CHIPSET(0x0F32, BAYTRAIL_M_2, byt)
- CHIPSET(0x0F33, BAYTRAIL_M_3, byt)
-diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
-index 04753dd..df025ac 100644
---- a/src/mesa/drivers/dri/intel/intel_chipset.h
-+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
-@@ -95,40 +95,40 @@
-
- #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
- #define PCI_CHIP_HASWELL_GT2 0x0412
--#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
-+#define PCI_CHIP_HASWELL_GT3 0x0422
- #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
- #define PCI_CHIP_HASWELL_M_GT2 0x0416
--#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
-+#define PCI_CHIP_HASWELL_M_GT3 0x0426
- #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
- #define PCI_CHIP_HASWELL_S_GT2 0x041A
--#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
-+#define PCI_CHIP_HASWELL_S_GT3 0x042A
- #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
- #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
--#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
-+#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
- #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
- #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
--#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
-+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
- #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
- #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
--#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
-+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
- #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
- #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
--#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
-+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
- #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
- #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
--#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
-+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
- #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
- #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
--#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
-+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
- #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
- #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
--#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
-+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
- #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
- #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
--#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
-+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
- #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
- #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
--#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
-+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
-
- #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
- devid == PCI_CHIP_I915_GM || \
-@@ -229,21 +229,23 @@
- devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-- devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
-- devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
-- devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
-+ devid == PCI_CHIP_HASWELL_CRW_S_GT2)
-+
-+#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_M_GT3 || \
-+ devid == PCI_CHIP_HASWELL_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_SDV_GT3 || \
-+ devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
-+ devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_ULT_GT3 || \
-+ devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
-+ devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
-+ devid == PCI_CHIP_HASWELL_CRW_GT3 || \
-+ devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
-+ devid == PCI_CHIP_HASWELL_CRW_S_GT3)
-
- #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
-- IS_HSW_GT2(devid))
-+ IS_HSW_GT2(devid) || \
-+ IS_HSW_GT3(devid))
-
- #define IS_965(devid) (IS_GEN4(devid) || \
- IS_G4X(devid) || \
-diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
-index 0a1dd75..88cc247 100644
---- a/src/mesa/drivers/dri/intel/intel_context.c
-+++ b/src/mesa/drivers/dri/intel/intel_context.c
-@@ -195,44 +195,44 @@ intelGetString(struct gl_context * ctx, GLenum name)
- break;
- case PCI_CHIP_HASWELL_GT1:
- case PCI_CHIP_HASWELL_GT2:
-- case PCI_CHIP_HASWELL_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_GT3:
- case PCI_CHIP_HASWELL_SDV_GT1:
- case PCI_CHIP_HASWELL_SDV_GT2:
-- case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_SDV_GT3:
- case PCI_CHIP_HASWELL_ULT_GT1:
- case PCI_CHIP_HASWELL_ULT_GT2:
-- case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_ULT_GT3:
- case PCI_CHIP_HASWELL_CRW_GT1:
- case PCI_CHIP_HASWELL_CRW_GT2:
-- case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_CRW_GT3:
- chipset = "Intel(R) Haswell Desktop";
- break;
- case PCI_CHIP_HASWELL_M_GT1:
- case PCI_CHIP_HASWELL_M_GT2:
-- case PCI_CHIP_HASWELL_M_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_M_GT3:
- case PCI_CHIP_HASWELL_SDV_M_GT1:
- case PCI_CHIP_HASWELL_SDV_M_GT2:
-- case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_SDV_M_GT3:
- case PCI_CHIP_HASWELL_ULT_M_GT1:
- case PCI_CHIP_HASWELL_ULT_M_GT2:
-- case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_ULT_M_GT3:
- case PCI_CHIP_HASWELL_CRW_M_GT1:
- case PCI_CHIP_HASWELL_CRW_M_GT2:
-- case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_CRW_M_GT3:
- chipset = "Intel(R) Haswell Mobile";
- break;
- case PCI_CHIP_HASWELL_S_GT1:
- case PCI_CHIP_HASWELL_S_GT2:
-- case PCI_CHIP_HASWELL_S_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_S_GT3:
- case PCI_CHIP_HASWELL_SDV_S_GT1:
- case PCI_CHIP_HASWELL_SDV_S_GT2:
-- case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_SDV_S_GT3:
- case PCI_CHIP_HASWELL_ULT_S_GT1:
- case PCI_CHIP_HASWELL_ULT_S_GT2:
-- case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_ULT_S_GT3:
- case PCI_CHIP_HASWELL_CRW_S_GT1:
- case PCI_CHIP_HASWELL_CRW_S_GT2:
-- case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
-+ case PCI_CHIP_HASWELL_CRW_S_GT3:
- chipset = "Intel(R) Haswell Server";
- break;
- default:
-@@ -684,6 +684,8 @@ intelInitContext(struct intel_context *intel,
- intel->gt = 1;
- else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID))
- intel->gt = 2;
-+ else if (IS_HSW_GT3(devID))
-+ intel->gt = 3;
- else
- intel->gt = 0;
-
diff --git a/debian/patches/fix-missing-gt3-id.diff b/debian/patches/fix-missing-gt3-id.diff
deleted file mode 100644
index ed5560a..0000000
--- a/debian/patches/fix-missing-gt3-id.diff
+++ /dev/null
@@ -1,26 +0,0 @@
-commit 888fc7a89197972aac614fc19d1c82ed1adbb3f2
-Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
-Date: Mon May 13 17:53:38 2013 -0300
-
- i965: Add missing Haswell GT3 Desktop to IS_HSW_GT3 check.
-
- NOTE: This is a candidate for stable branches.
-
- Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
- Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
-
-diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
-index df025ac..ee735bb 100644
---- a/src/mesa/drivers/dri/intel/intel_chipset.h
-+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
-@@ -230,8 +230,8 @@
- devid == PCI_CHIP_HASWELL_CRW_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2)
--
--#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_M_GT3 || \
-+#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \
-+ devid == PCI_CHIP_HASWELL_M_GT3 || \
- devid == PCI_CHIP_HASWELL_S_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
diff --git a/debian/patches/revert-a64c1eb9b110.diff b/debian/patches/revert-a64c1eb9b110.diff
index d9c0149..9b3d8da 100644
--- a/debian/patches/revert-a64c1eb9b110.diff
+++ b/debian/patches/revert-a64c1eb9b110.diff
@@ -1,6 +1,6 @@
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
-@@ -219,45 +219,6 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0,
+@@ -219,46 +219,6 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0,
return inst;
}
@@ -14,6 +14,7 @@
- if (intel->gen >= 7) {
- inst = new(mem_ctx) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
- dst, surf_index, offset);
+- inst->regs_written = 1;
- instructions.push_tail(inst);
- } else {
- int base_mrf = 13;
diff --git a/debian/patches/series b/debian/patches/series
index 8bad209..d569956 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -14,11 +14,3 @@
revert-7f2a65d896bf.diff
revert-d61b1fdad6a.diff
revert-a64c1eb9b110.diff
-CVE-2013-1872.patch
-CVE-2013-1993.patch
-
-# Add missing haswell pci ids
-add-vlv-ids.diff
-fix-hsw-gt3-names.diff
-fix-missing-gt3-id.diff
-add-more-reserved-hsw-ids.diff
commit e64febb4b71475b35765f0dc168df22655444a7f
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Mon Jul 1 14:05:00 2013 -0700
docs: 9.1.4 release notes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/docs/relnotes-9.1.4.html b/docs/relnotes-9.1.4.html
new file mode 100644
index 0000000..48e421b
--- /dev/null
+++ b/docs/relnotes-9.1.4.html
@@ -0,0 +1,319 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.4 Release Notes / July 1st, 2013</h1>
+
+<p>
+Mesa 9.1.4 is a bug fix release which fixes bugs found since the 9.1.3 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1. OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+TBD
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=37871";>Bug 37871</a> - [bisected i965] Bus error (core dumped) on oglc texdecaltile</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=42182";>Bug 42182</a> - egl/opengles1/tri_x11 renders wrong</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44958";>Bug 44958</a> - [SNB IVB HSW] mesa demo test texleak bus error</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=53494";>Bug 53494</a> - [snb] crash in texsubimage to a large atlas in clutter</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60518";>Bug 60518</a> - glDrawElements segfault when compiled into display list</li>
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