libdrm: Changes to 'debian-unstable'
ChangeLog | 159 +++++++++++++++++++++++++++++++++++++++
configure.ac | 2
debian/changelog | 5 -
debian/control | 2
debian/libdrm-intel1.symbols | 1
debian/libdrm2.symbols | 1
debian/rules | 6 -
freedreno/freedreno_bo.c | 67 +++++++++++++++-
freedreno/freedreno_device.c | 61 ++++++++++++++
freedreno/freedreno_drmif.h | 1
freedreno/freedreno_priv.h | 13 +++
freedreno/freedreno_ringbuffer.c | 7 +
include/drm/drm.h | 1
include/drm/drm_mode.h | 13 +++
intel/intel_aub.h | 76 +++++++++++++-----
intel/intel_bufmgr.h | 3
intel/intel_bufmgr_gem.c | 27 ++++++
intel/intel_chipset.h | 101 ++++++++++++++++++------
radeon/r600_pci_ids.h | 26 ++++++
radeon/radeon_bo_gem.c | 4
radeon/radeon_surface.c | 3
tests/modetest/buffers.c | 26 +++++-
xf86drmMode.c | 15 +++
xf86drmMode.h | 1
24 files changed, 552 insertions(+), 69 deletions(-)
New commits:
commit 7c957cd1c7baef6136bd81eedefb3c8503cf0dbf
Author: Sven Joachim <svenjoac@gmx.de>
Date: Tue Jul 2 17:16:20 2013 +0200
Use Package-Type rather than XC-Package-Type for the udeb
As recommended by lintian.
diff --git a/debian/control b/debian/control
index 873ce22..6729001 100644
--- a/debian/control
+++ b/debian/control
@@ -59,7 +59,7 @@ Description: Userspace interface to kernel DRM services -- runtime
This package provides the runtime environment for libdrm.
Package: libdrm2-udeb
-XC-Package-Type: udeb
+Package-Type: udeb
Section: debian-installer
Architecture: any
Depends:
commit 3b6be4f49acd7114358bd459b0d0eebd3f47c5eb
Author: Sven Joachim <svenjoac@gmx.de>
Date: Tue Jul 2 17:13:49 2013 +0200
Disable silent rules
diff --git a/debian/changelog b/debian/changelog
index 4020e37..7e8a0c9 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -3,6 +3,7 @@ libdrm (2.4.46-1) UNRELEASED; urgency=low
* New upstream release.
* Bump libdrm2's and libdrm-intel1's symbols and shlibs.
* Build libdrm-intel1 on x32 (Closes: #712515).
+ * Disable silent rules.
-- Sven Joachim <svenjoac@gmx.de> Sun, 16 Jun 2013 20:40:09 +0200
diff --git a/debian/rules b/debian/rules
index b331970..d57b013 100755
--- a/debian/rules
+++ b/debian/rules
@@ -56,7 +56,7 @@ endif
###
override_dh_auto_configure:
- dh_auto_configure -- --enable-static=yes $(confflags)
+ dh_auto_configure -- --disable-silent-rules --enable-static=yes $(confflags)
override_dh_auto_test:
dh_auto_test || echo "Test suite failure, but keeping on anyway"
commit e85b238c0825f72dd79cffb8f24531b5ec9fa099
Author: Sven Joachim <svenjoac@gmx.de>
Date: Tue Jul 2 17:04:59 2013 +0200
Bump libdrm2's and libdrm-intel1's symbols and shlibs
diff --git a/debian/changelog b/debian/changelog
index 46c8fb0..4020e37 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,7 @@
libdrm (2.4.46-1) UNRELEASED; urgency=low
* New upstream release.
+ * Bump libdrm2's and libdrm-intel1's symbols and shlibs.
* Build libdrm-intel1 on x32 (Closes: #712515).
-- Sven Joachim <svenjoac@gmx.de> Sun, 16 Jun 2013 20:40:09 +0200
diff --git a/debian/libdrm-intel1.symbols b/debian/libdrm-intel1.symbols
index 8f5b9fe..a0b9440 100644
--- a/debian/libdrm-intel1.symbols
+++ b/debian/libdrm-intel1.symbols
@@ -41,6 +41,7 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
drm_intel_bufmgr_gem_get_devid@Base 2.4.32
drm_intel_bufmgr_gem_init@Base 2.4.1
drm_intel_bufmgr_gem_set_aub_dump@Base 2.4.32
+ drm_intel_bufmgr_gem_set_aub_filename@Base 2.4.46
drm_intel_bufmgr_gem_set_aub_annotations@Base 2.4.34
drm_intel_bufmgr_gem_set_vma_cache_size@Base 2.4.29
drm_intel_bufmgr_set_debug@Base 2.4.1
diff --git a/debian/libdrm2.symbols b/debian/libdrm2.symbols
index c4047c4..563184f 100644
--- a/debian/libdrm2.symbols
+++ b/debian/libdrm2.symbols
@@ -110,6 +110,7 @@ libdrm.so.2 libdrm2 #MINVER#
drmModePageFlip@Base 2.4.17
drmModeRmFB@Base 2.4.3
drmModeSetCrtc@Base 2.4.3
+ drmModeSetCursor2@Base 2.4.46
drmModeSetCursor@Base 2.4.3
drmModeSetPlane@Base 2.4.30
drmMsg@Base 2.4.1
diff --git a/debian/rules b/debian/rules
index 78ea6f7..b331970 100755
--- a/debian/rules
+++ b/debian/rules
@@ -88,9 +88,9 @@ endif
dh_strip -s --remaining-packages
override_dh_makeshlibs:
- dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.38)' --add-udeb=libdrm2-udeb -- -c4
+ dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.46)' --add-udeb=libdrm2-udeb -- -c4
ifeq ($(INTEL), yes)
- dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.38)' -- -c4
+ dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.46)' -- -c4
endif
ifeq ($(NOUVEAU), yes)
dh_makeshlibs -plibdrm-nouveau2 -V'libdrm-nouveau2 (>= 2.4.38)' -- -c4
commit 7eb5558d584ae7010f1dd8e54992f9c58fea819c
Author: Sven Joachim <svenjoac@gmx.de>
Date: Tue Jul 2 16:51:29 2013 +0200
New upstream release
diff --git a/ChangeLog b/ChangeLog
index 51c7a9b..2ea6916 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,162 @@
+commit c6d73cfeeaff9596c735d0a10b248f94b2e1e347
+Author: Dave Airlie <airlied@redhat.com>
+Date: Tue Jul 2 09:24:53 2013 +0100
+
+ libdrm: bump to 2.4.46
+
+commit 2e0ab6237697c9754d92689f77c1792c11be881b
+Author: Dave Airlie <airlied@redhat.com>
+Date: Tue Jul 2 09:21:06 2013 +0100
+
+ drm: add hotspot cursor interface support.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 378bb47a784a3808c9b256fe7a52e10a4fcabf92
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Jan 24 18:01:59 2013 -0500
+
+ radeon: add kabini pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 96c04c23fca6656483f66ecb0da0679df02eb9c0
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri Jun 7 13:46:37 2013 -0400
+
+ radeon: add Bonaire pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 0ff7f2760d052503d5cf65ded34a66fe20ccec28
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri Jun 7 13:45:30 2013 -0400
+
+ radeon: add CIK chip families
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit fbd106ad76b0ee33814f6a5b94efaa0b067ec2af
+Author: Damien Lespiau <damien.lespiau@intel.com>
+Date: Wed Feb 20 12:11:49 2013 +0000
+
+ intel/aub: Implement a way to specify the output .aub filename
+
+ Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
+ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 1e4f63bbc8e9a23c90745e10027e2772bab15038
+Author: Damien Lespiau <damien.lespiau@intel.com>
+Date: Wed Feb 20 12:11:50 2013 +0000
+
+ intel/aub: Return early if we disable aub dumps
+
+ No need to prepare the .aub header and dump in that case, it'll be
+ done with the next call with true.
+
+ Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
+ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 59257580666cf5f5916bf989d94bace774030bd5
+Author: Damien Lespiau <damien.lespiau@intel.com>
+Date: Wed Feb 20 12:11:48 2013 +0000
+
+ intel/aub: Sync the AUB defines with mesa's
+
+ Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
+ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit a0178c00c70f4b47e09ed7564fc2ccde611231a0
+Author: Mark Kettenis <kettenis@openbsd.org>
+Date: Wed Jun 5 13:04:30 2013 +1000
+
+ radeon: correct RADEON_GEM_WAIT_IDLE use
+
+ RADEON_GEM_WAIT_IDLE is declared DRM_IOW but libdrm
+ uses it with drmCommandWriteRead instead of drmCommandWrite
+ which leads to the ioctl being unmatched and returning an
+ error on at least OpenBSD.
+
+ Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
+ Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
+
+commit 1669a67d063e82a58dae4d906015172d471e9a2a
+Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Date: Mon May 13 17:48:40 2013 -0300
+
+ intel: Adding more reserved PCI IDs for Haswell.
+
+ At DDX commit Chris mentioned the tendency we have of finding out more
+ PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
+
+ Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+ Acked-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 150c3555e7ba53f6ad2d3970cca8e4d5970410aa
+Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Date: Mon May 13 17:48:39 2013 -0300
+
+ intel: Fix Haswell GT3 names.
+
+ When publishing first HSW ids we weren't allowed to use "GT3" codname.
+ But this is the correct codname and Mesa is using it already.
+ So to avoid people getting confused why in Mesa it is called GT3 and here
+ it is called GT2_PLUS let's fix this name in a standard and correct way.
+
+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+ Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
+ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 8a88e349975a64676f143183e835e6d296f29627
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Thu Apr 18 17:26:52 2013 +0300
+
+ modetest: Make RGB565 pwetty too
+
+ Render the crosshairs for 565 and x888/a888 formats.
+
+ v2: Use the drm format to determine cairo format
+
+ Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 3586337f3703ce4833a375f66b08df064a1cec28
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Fri May 17 16:13:02 2013 -0400
+
+ freedreno: also remove from name table on bo delete
+
+ When adding the name tracking, I missed removing from the name table
+ when the bo was deleted, leaving a dangling pointer.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit acfbf394a9176ea97f114ca6c0eb8249a2220e82
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Wed May 15 13:21:24 2013 -0400
+
+ freedreno: add some asserts
+
+ Things are worse if we issueibcmds with bogus gpu ptrs, so it is better
+ to just make userspace crash when things go pear shaped.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit 0b89e2730c41466e8d9c04c469679ba23d052ec9
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Wed May 15 13:18:02 2013 -0400
+
+ freedreno: add handle and name tracking
+
+ Due to the evil userspace buffer tracking we have to do, and hacks for
+ creating GEM buffer from fbdev/scanout, "evil-twin" fd_bo objects are
+ problematic. So introduce hashtable tracking of bo's and dev's, to
+ avoid getting duplicate fd_bo ptrs for the same underlying gem object,
+ in particular when importing via flink name.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed May 15 19:32:05 2013 +0200
diff --git a/debian/changelog b/debian/changelog
index 3b2fa20..46c8fb0 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,6 @@
-libdrm (2.4.45-4) UNRELEASED; urgency=low
+libdrm (2.4.46-1) UNRELEASED; urgency=low
+ * New upstream release.
* Build libdrm-intel1 on x32 (Closes: #712515).
-- Sven Joachim <svenjoac@gmx.de> Sun, 16 Jun 2013 20:40:09 +0200
commit c6d73cfeeaff9596c735d0a10b248f94b2e1e347
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Jul 2 09:24:53 2013 +0100
libdrm: bump to 2.4.46
diff --git a/configure.ac b/configure.ac
index 21f8d3f..d2e232b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.45],
+ [2.4.46],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 2e0ab6237697c9754d92689f77c1792c11be881b
Author: Dave Airlie <airlied@redhat.com>
Date: Tue Jul 2 09:21:06 2013 +0100
drm: add hotspot cursor interface support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/include/drm/drm.h b/include/drm/drm.h
index a847689..616824b 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -733,6 +733,7 @@ struct drm_prime_handle {
#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
+#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
/**
* Device specific ioctls should only be in their respective headers
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 62ba997..d41d76b 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -390,6 +390,19 @@ struct drm_mode_cursor {
__u32 handle;
};
+struct drm_mode_cursor2 {
+ __u32 flags;
+ __u32 crtc_id;
+ __s32 x;
+ __s32 y;
+ __u32 width;
+ __u32 height;
+ /* driver specific handle */
+ __u32 handle;
+ __s32 hot_x;
+ __s32 hot_y;
+};
+
struct drm_mode_crtc_lut {
__u32 crtc_id;
__u32 gamma_size;
diff --git a/xf86drmMode.c b/xf86drmMode.c
index f603ceb..6b60c35 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -400,6 +400,21 @@ int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width
return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg);
}
+int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height, int32_t hot_x, int32_t hot_y)
+{
+ struct drm_mode_cursor2 arg;
+
+ arg.flags = DRM_MODE_CURSOR_BO;
+ arg.crtc_id = crtcId;
+ arg.width = width;
+ arg.height = height;
+ arg.handle = bo_handle;
+ arg.hot_x = hot_x;
+ arg.hot_y = hot_y;
+
+ return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR2, &arg);
+}
+
int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y)
{
struct drm_mode_cursor arg;
diff --git a/xf86drmMode.h b/xf86drmMode.h
index 8e40034..f8a817c 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -378,6 +378,7 @@ int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
*/
int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height);
+int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height, int32_t hot_x, int32_t hot_y);
/**
* Move the cursor on crtc
*/
commit 378bb47a784a3808c9b256fe7a52e10a4fcabf92
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Thu Jan 24 18:01:59 2013 -0500
radeon: add kabini pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 545019e..fbadb82 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -407,3 +407,20 @@ CHIPSET(0x6651, BONAIRE_6651, BONAIRE)
CHIPSET(0x6658, BONAIRE_6658, BONAIRE)
CHIPSET(0x665C, BONAIRE_665C, BONAIRE)
CHIPSET(0x665D, BONAIRE_665D, BONAIRE)
+
+CHIPSET(0x9830, KABINI_9830, KABINI)
+CHIPSET(0x9831, KABINI_9831, KABINI)
+CHIPSET(0x9832, KABINI_9832, KABINI)
+CHIPSET(0x9833, KABINI_9833, KABINI)
+CHIPSET(0x9834, KABINI_9834, KABINI)
+CHIPSET(0x9835, KABINI_9835, KABINI)
+CHIPSET(0x9836, KABINI_9836, KABINI)
+CHIPSET(0x9837, KABINI_9837, KABINI)
+CHIPSET(0x9838, KABINI_9838, KABINI)
+CHIPSET(0x9839, KABINI_9839, KABINI)
+CHIPSET(0x983A, KABINI_983A, KABINI)
+CHIPSET(0x983B, KABINI_983B, KABINI)
+CHIPSET(0x983C, KABINI_983C, KABINI)
+CHIPSET(0x983D, KABINI_983D, KABINI)
+CHIPSET(0x983E, KABINI_983E, KABINI)
+CHIPSET(0x983F, KABINI_983F, KABINI)
commit 96c04c23fca6656483f66ecb0da0679df02eb9c0
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Jun 7 13:46:37 2013 -0400
radeon: add Bonaire pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 01c900f..545019e 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -398,3 +398,12 @@ CHIPSET(0x6664, HAINAN_6664, HAINAN)
CHIPSET(0x6665, HAINAN_6665, HAINAN)
CHIPSET(0x6667, HAINAN_6667, HAINAN)
CHIPSET(0x666F, HAINAN_666F, HAINAN)
+
+CHIPSET(0x6640, BONAIRE_6640, BONAIRE)
+CHIPSET(0x6641, BONAIRE_6641, BONAIRE)
+CHIPSET(0x6649, BONAIRE_6649, BONAIRE)
+CHIPSET(0x6650, BONAIRE_6650, BONAIRE)
+CHIPSET(0x6651, BONAIRE_6651, BONAIRE)
+CHIPSET(0x6658, BONAIRE_6658, BONAIRE)
+CHIPSET(0x665C, BONAIRE_665C, BONAIRE)
+CHIPSET(0x665D, BONAIRE_665D, BONAIRE)
commit 0ff7f2760d052503d5cf65ded34a66fe20ccec28
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Jun 7 13:45:30 2013 -0400
radeon: add CIK chip families
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index a74064c..818e26a 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -74,6 +74,9 @@ enum radeon_family {
CHIP_VERDE,
CHIP_OLAND,
CHIP_HAINAN,
+ CHIP_BONAIRE,
+ CHIP_KAVERI,
+ CHIP_KABINI,
CHIP_LAST,
};
commit fbd106ad76b0ee33814f6a5b94efaa0b067ec2af
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Wed Feb 20 12:11:49 2013 +0000
intel/aub: Implement a way to specify the output .aub filename
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 8d7f239..15f818e 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -171,6 +171,9 @@ int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
+void
+drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
+ const char *filename);
void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
int x1, int y1, int width, int height,
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 7b1ecf1..a51e3f3 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -128,6 +128,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int has_vebox : 1;
bool fenced_relocs;
+ char *aub_filename;
FILE *aub_file;
uint32_t aub_offset;
} drm_intel_bufmgr_gem;
@@ -1574,6 +1575,7 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
free(bufmgr_gem->exec2_objects);
free(bufmgr_gem->exec_objects);
free(bufmgr_gem->exec_bos);
+ free(bufmgr_gem->aub_filename);
pthread_mutex_destroy(&bufmgr_gem->lock);
@@ -2865,6 +2867,23 @@ drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
}
/**
+ * Sets the AUB filename.
+ *
+ * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
+ * for it to have any effect.
+ */
+void
+drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
+ const char *filename)
+{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
+
+ free(bufmgr_gem->aub_filename);
+ if (filename)
+ bufmgr_gem->aub_filename = strdup(filename);
+}
+
+/**
* Sets up AUB dumping.
*
* This is a trace file format that can be used with the simulator.
@@ -2879,6 +2898,7 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
int entry = 0x200003;
int i;
int gtt_size = 0x10000;
+ const char *filename;
if (!enable) {
if (bufmgr_gem->aub_file) {
@@ -2891,7 +2911,11 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
if (geteuid() != getuid())
return;
- bufmgr_gem->aub_file = fopen("intel.aub", "w+");
+ if (bufmgr_gem->aub_filename)
+ filename = bufmgr_gem->aub_filename;
+ else
+ filename = "intel.aub";
+ bufmgr_gem->aub_file = fopen(filename, "w+");
if (!bufmgr_gem->aub_file)
return;
commit 1e4f63bbc8e9a23c90745e10027e2772bab15038
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Wed Feb 20 12:11:50 2013 +0000
intel/aub: Return early if we disable aub dumps
No need to prepare the .aub header and dump in that case, it'll be
done with the next call with true.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 3c73068..7b1ecf1 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2885,6 +2885,7 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
fclose(bufmgr_gem->aub_file);
bufmgr_gem->aub_file = NULL;
}
+ return;
}
if (geteuid() != getuid())
commit 59257580666cf5f5916bf989d94bace774030bd5
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Wed Feb 20 12:11:48 2013 +0000
intel/aub: Sync the AUB defines with mesa's
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
diff --git a/intel/intel_aub.h b/intel/intel_aub.h
index a36fd53..5f0aba8 100644
--- a/intel/intel_aub.h
+++ b/intel/intel_aub.h
@@ -93,29 +93,59 @@
#define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16)
/* DW2 */
-// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_GENERAL_STATE
-#define AUB_TRACE_GENERAL_STATE_MASK 0x000000ff
-
-#define AUB_TRACE_VS_STATE 0x00000001
-#define AUB_TRACE_GS_STATE 0x00000002
-#define AUB_TRACE_CL_STATE 0x00000003
-#define AUB_TRACE_SF_STATE 0x00000004
-#define AUB_TRACE_WM_STATE 0x00000005
-#define AUB_TRACE_CC_STATE 0x00000006
-#define AUB_TRACE_CL_VP 0x00000007
-#define AUB_TRACE_SF_VP 0x00000008
-#define AUB_TRACE_CC_VP 0x00000009
-#define AUB_TRACE_SAMPLER_STATE 0x0000000a
-#define AUB_TRACE_KERNEL 0x0000000b
-#define AUB_TRACE_SCRATCH 0x0000000c
-#define AUB_TRACE_SDC 0x0000000d
-#define AUB_TRACE_BLEND_STATE 0x00000016
-#define AUB_TRACE_DEPTH_STENCIL_STATE 0x00000017
-
-// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_SURFACE_STATE
-#define AUB_TRACE_SURFACE_STATE_MASK 0x00000ff00
-#define AUB_TRACE_BINDING_TABLE 0x000000100
-#define AUB_TRACE_SURFACE_STATE 0x000000200
+
+/**
+ * aub_state_struct_type enum values are encoded with the top 16 bits
+ * representing the type to be delivered to the .aub file, and the bottom 16
+ * bits representing the subtype. This macro performs the encoding.
+ */
+#define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
+
+enum aub_state_struct_type {
+ AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1),
+ AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2),
+ AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3),
+ AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4),
+ AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5),
+ AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6),
+ AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7),
+ AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8),
+ AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9),
+ AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa),
+ AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb),
+ AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc),
+ AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd),
+
+ AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15),
+ AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16),
+ AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17),
+
+ AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0),
+ AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100),
+ AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200),
+ AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0),
+ AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1),
+};
+
+#undef ENCODE_SS_TYPE
+
+/**
+ * Decode a aub_state_struct_type value to determine the type that should be
+ * stored in the .aub file.
+ */
+static inline uint32_t AUB_TRACE_TYPE(enum aub_state_struct_type ss_type)
+{
+ return (ss_type & 0xFFFF0000) >> 16;
+}
+
+/**
+ * Decode a state_struct_type value to determine the subtype that should be
+ * stored in the .aub file.
+ */
+static inline uint32_t AUB_TRACE_SUBTYPE(enum aub_state_struct_type ss_type)
+{
+ return ss_type & 0xFFFF;
+}
/* DW3: address */
/* DW4: len */
commit a0178c00c70f4b47e09ed7564fc2ccde611231a0
Author: Mark Kettenis <kettenis@openbsd.org>
Date: Wed Jun 5 13:04:30 2013 +1000
radeon: correct RADEON_GEM_WAIT_IDLE use
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but libdrm
uses it with drmCommandWriteRead instead of drmCommandWrite
which leads to the ioctl being unmatched and returning an
error on at least OpenBSD.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c
index fca0aaf..4ea405f 100644
--- a/radeon/radeon_bo_gem.c
+++ b/radeon/radeon_bo_gem.c
@@ -211,8 +211,8 @@ static int bo_wait(struct radeon_bo_int *boi)
memset(&args, 0, sizeof(args));
args.handle = boi->handle;
do {
- ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
- &args, sizeof(args));
+ ret = drmCommandWrite(boi->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
+ &args, sizeof(args));
} while (ret == -EBUSY);
return ret;
}
commit 1669a67d063e82a58dae4d906015172d471e9a2a
Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Date: Mon May 13 17:48:40 2013 -0300
intel: Adding more reserved PCI IDs for Haswell.
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 3350def..aeb439e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -97,6 +97,12 @@
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041A
#define PCI_CHIP_HASWELL_S_GT3 0x042A
+#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
+#define PCI_CHIP_HASWELL_B_GT2 0x041B
+#define PCI_CHIP_HASWELL_B_GT3 0x042B
+#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
+#define PCI_CHIP_HASWELL_E_GT2 0x041E
+#define PCI_CHIP_HASWELL_E_GT3 0x042E
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
@@ -106,6 +112,12 @@
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
+#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
+#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
+#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
+#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
@@ -115,6 +127,12 @@
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
+#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
+#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
+#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
+#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
@@ -124,6 +142,12 @@
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
+#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
+#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
+#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
+#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
@@ -210,39 +234,63 @@
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_E_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
(devid) == PCI_CHIP_HASWELL_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_E_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
(devid) == PCI_CHIP_HASWELL_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_E_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
(devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid) || \
commit 150c3555e7ba53f6ad2d3970cca8e4d5970410aa
Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Date: Mon May 13 17:48:39 2013 -0300
intel: Fix Haswell GT3 names.
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 5aea3f2..3350def 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -90,40 +90,40 @@
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_GT3 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_M_GT3 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_S_GT3 0x042A
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
@@ -230,22 +230,23 @@
(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
+#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid))
+ IS_HSW_GT2(devid) || \
+ IS_HSW_GT3(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
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