libdrm: Changes to 'ubuntu'
.gitignore | 1
ChangeLog | 116 +++++++++++++++++++
configure.ac | 2
debian/changelog | 30 ++++-
debian/control | 2
debian/patches/add-more-reserved-hsw-ids.diff | 136 +++++++++++++++++++++++
debian/patches/fix-hsw-gt3-names.diff | 110 ++++++++++++++++++
debian/patches/series | 2
freedreno/freedreno_bo.c | 68 +++++++++++
freedreno/freedreno_drmif.h | 1
freedreno/freedreno_pipe.c | 26 ++++
freedreno/freedreno_priv.h | 10 +
freedreno/freedreno_ringbuffer.c | 4
include/drm/Makefile.am | 4
include/drm/i915_drm.h | 2
include/drm/qxl_drm.h | 152 ++++++++++++++++++++++++++
intel/intel_bufmgr_gem.c | 9 +
radeon/r600_pci_ids.h | 12 ++
radeon/radeon_surface.c | 10 +
radeon/radeon_surface.h | 1
20 files changed, 682 insertions(+), 16 deletions(-)
New commits:
commit 03d6c82578112b7ee436b332d1cdbaa9c8abcc30
Author: Timo Aaltonen <tjaalton@ubuntu.com>
Date: Thu Jun 6 14:12:14 2013 +0300
release to saucy
diff --git a/debian/changelog b/debian/changelog
index c8ec82a..22121be 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,9 +1,9 @@
-libdrm (2.4.45-2ubuntu1) UNRELEASED; urgency=low
+libdrm (2.4.45-2ubuntu1) saucy; urgency=low
* Merge from debian experimental.
* Added patches to add/fix Haswell pci-id's (LP: #1175533)
- -- Timo Aaltonen <tjaalton@ubuntu.com> Thu, 06 Jun 2013 14:08:52 +0300
+ -- Timo Aaltonen <tjaalton@ubuntu.com> Thu, 06 Jun 2013 14:10:48 +0300
libdrm (2.4.45-2) experimental; urgency=low
commit ef3e0628bf05f9a182c0614a8b14d5bce820acbd
Author: Timo Aaltonen <tjaalton@ubuntu.com>
Date: Thu Jun 6 14:10:45 2013 +0300
Added patches to add/fix Haswell pci-id's (LP: #1175533)
diff --git a/debian/changelog b/debian/changelog
index 028f434..c8ec82a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+libdrm (2.4.45-2ubuntu1) UNRELEASED; urgency=low
+
+ * Merge from debian experimental.
+ * Added patches to add/fix Haswell pci-id's (LP: #1175533)
+
+ -- Timo Aaltonen <tjaalton@ubuntu.com> Thu, 06 Jun 2013 14:08:52 +0300
+
libdrm (2.4.45-2) experimental; urgency=low
[ Sven Joachim ]
diff --git a/debian/patches/add-more-reserved-hsw-ids.diff b/debian/patches/add-more-reserved-hsw-ids.diff
new file mode 100644
index 0000000..5586818
--- /dev/null
+++ b/debian/patches/add-more-reserved-hsw-ids.diff
@@ -0,0 +1,136 @@
+commit 1669a67d063e82a58dae4d906015172d471e9a2a
+Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Date: Mon May 13 17:48:40 2013 -0300
+
+ intel: Adding more reserved PCI IDs for Haswell.
+
+ At DDX commit Chris mentioned the tendency we have of finding out more
+ PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
+
+ Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+ Acked-by: Kenneth Graunke <kenneth@whitecape.org>
+
+diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
+index 3350def..aeb439e 100644
+--- a/intel/intel_chipset.h
++++ b/intel/intel_chipset.h
+@@ -97,6 +97,12 @@
+ #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+ #define PCI_CHIP_HASWELL_S_GT2 0x041A
+ #define PCI_CHIP_HASWELL_S_GT3 0x042A
++#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
++#define PCI_CHIP_HASWELL_B_GT2 0x041B
++#define PCI_CHIP_HASWELL_B_GT3 0x042B
++#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
++#define PCI_CHIP_HASWELL_E_GT2 0x041E
++#define PCI_CHIP_HASWELL_E_GT3 0x042E
+ #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+ #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+ #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
+@@ -106,6 +112,12 @@
+ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+ #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
++#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
++#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
++#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
++#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
++#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
++#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
+ #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+ #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
+@@ -115,6 +127,12 @@
+ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+ #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
++#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
++#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
++#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
++#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
++#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
++#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
+ #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
+ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
+ #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
+@@ -124,6 +142,12 @@
+ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
+ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+ #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
++#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
++#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
++#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
++#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
++#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
++#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
+
+ #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
+ #define PCI_CHIP_VALLEYVIEW_1 0x0f31
+@@ -210,39 +234,63 @@
+ #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
+ #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
+ #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
+
+ #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
+ IS_HSW_GT2(devid) || \
diff --git a/debian/patches/fix-hsw-gt3-names.diff b/debian/patches/fix-hsw-gt3-names.diff
new file mode 100644
index 0000000..fc59e02
--- /dev/null
+++ b/debian/patches/fix-hsw-gt3-names.diff
@@ -0,0 +1,110 @@
+commit 150c3555e7ba53f6ad2d3970cca8e4d5970410aa
+Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Date: Mon May 13 17:48:39 2013 -0300
+
+ intel: Fix Haswell GT3 names.
+
+ When publishing first HSW ids we weren't allowed to use "GT3" codname.
+ But this is the correct codname and Mesa is using it already.
+ So to avoid people getting confused why in Mesa it is called GT3 and here
+ it is called GT2_PLUS let's fix this name in a standard and correct way.
+
+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+ Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
+ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+
+diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
+index 5aea3f2..3350def 100644
+--- a/intel/intel_chipset.h
++++ b/intel/intel_chipset.h
+@@ -90,40 +90,40 @@
+
+ #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
+ #define PCI_CHIP_HASWELL_GT2 0x0412
+-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
++#define PCI_CHIP_HASWELL_GT3 0x0422
+ #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
+ #define PCI_CHIP_HASWELL_M_GT2 0x0416
+-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
++#define PCI_CHIP_HASWELL_M_GT3 0x0426
+ #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+ #define PCI_CHIP_HASWELL_S_GT2 0x041A
+-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
++#define PCI_CHIP_HASWELL_S_GT3 0x042A
+ #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+ #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
++#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
+ #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
+ #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
++#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
+ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
++#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
+ #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
++#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
+ #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
+ #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
++#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
+ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
++#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
+ #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
+ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
+-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
++#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
+ #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
+ #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
+-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
++#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
+ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
+ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
++#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
+
+ #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
+ #define PCI_CHIP_VALLEYVIEW_1 0x0f31
+@@ -230,22 +230,23 @@
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+- (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
++#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
+
+ #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
+- IS_HSW_GT2(devid))
++ IS_HSW_GT2(devid) || \
++ IS_HSW_GT3(devid))
+
+ #define IS_9XX(dev) (IS_GEN3(dev) || \
+ IS_GEN4(dev) || \
diff --git a/debian/patches/series b/debian/patches/series
index 2e425c0..f28456c 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1,2 +1,4 @@
01_default_perms.diff
03_build_against_librt.diff
+fix-hsw-gt3-names.diff
+add-more-reserved-hsw-ids.diff
commit 687b4feafcf2696727eb62c0d781ec0de42c723e
Author: Julien Cristau <jcristau@debian.org>
Date: Thu May 30 10:03:45 2013 +0200
Upload to experimental
diff --git a/debian/changelog b/debian/changelog
index 04a89c4..c0c519a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,9 +1,10 @@
-libdrm (2.4.45-2) UNRELEASED; urgency=low
+libdrm (2.4.45-2) experimental; urgency=low
+ [ Sven Joachim ]
* Only build-depend on valgrind on architectures where
valgrind is actually available.
- -- Sven Joachim <svenjoac@gmx.de> Fri, 17 May 2013 17:56:43 +0200
+ -- Julien Cristau <jcristau@debian.org> Thu, 30 May 2013 10:03:37 +0200
libdrm (2.4.45-1) experimental; urgency=low
commit c3b713090840df937677c0827aa76ca798ea9ff3
Author: Sven Joachim <svenjoac@gmx.de>
Date: Fri May 17 18:00:06 2013 +0200
Make valgrind build-dependency archictecture specific
diff --git a/debian/changelog b/debian/changelog
index fdc788c..04a89c4 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+libdrm (2.4.45-2) UNRELEASED; urgency=low
+
+ * Only build-depend on valgrind on architectures where
+ valgrind is actually available.
+
+ -- Sven Joachim <svenjoac@gmx.de> Fri, 17 May 2013 17:56:43 +0200
+
libdrm (2.4.45-1) experimental; urgency=low
* Team upload.
diff --git a/debian/control b/debian/control
index 8175dfc..ec12408 100644
--- a/debian/control
+++ b/debian/control
@@ -13,7 +13,7 @@ Build-Depends:
libpthread-stubs0-dev,
libudev-dev [linux-any],
libpciaccess-dev,
- valgrind,
+ valgrind [amd64 armel armhf i386 mips mipsel powerpc s390x],
Standards-Version: 3.9.4
Section: libs
Vcs-Git: git://git.debian.org/git/pkg-xorg/lib/libdrm
commit 157efcb996b5e5e366947ebd3cdd69f96a7c129f
Author: Emilio Pozuelo Monfort <pochu@debian.org>
Date: Thu May 16 00:17:04 2013 +0200
Upload 2.4.45 to experimental
diff --git a/debian/changelog b/debian/changelog
index 99ca0fc..fdc788c 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,6 @@
-libdrm (2.4.45-1) UNRELEASED; urgency=low
+libdrm (2.4.45-1) experimental; urgency=low
+
+ * Team upload.
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
@@ -11,7 +13,10 @@ libdrm (2.4.45-1) UNRELEASED; urgency=low
[ Timo Aaltonen ]
* control: Bump policy to 3.9.4, no changes.
- -- Julien Cristau <jcristau@debian.org> Tue, 25 Dec 2012 13:17:28 +0100
+ [ Emilio Pozuelo Monfort ]
+ * Upload to experimental.
+
+ -- Emilio Pozuelo Monfort <pochu@debian.org> Thu, 16 May 2013 00:09:59 +0200
libdrm (2.4.40-1) experimental; urgency=low
commit ef470fa9bd9a65897788519f67d4b8fa20750c60
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Wed May 15 21:57:50 2013 +0200
bump changelogs
diff --git a/ChangeLog b/ChangeLog
index 74b1902..51c7a9b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,119 @@
+commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed May 15 19:32:05 2013 +0200
+
+ configure.ac: bump version to 2.4.45 for release
+
+commit e5e51c2110ebf6e1edaa14b7567c5d6a79008a90
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed Apr 24 20:39:45 2013 +0200
+
+ radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
+
+ Signed-off-by: Marek Olšák <maraeo@gmail.com>
+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 96e90aabc4c0238de2f2d245899f991a3b996587
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon May 13 16:14:28 2013 -0400
+
+ radeon: add HAINAN pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit c56729cc1564bb4204ca30a18499a78a39f48892
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon May 13 16:15:17 2013 -0400
+
+ radeon: add HAINAN family
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 040f6b015ef7d9c1bda09f78a8873f6da45d5e95
+Author: Dave Airlie <airlied@redhat.com>
+Date: Thu May 9 12:55:42 2013 +1000
+
+ drm: add qxl drm header file
+
+ Now that this driver is merged add the header file.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 011999927f76a7e9ba8f047fae4b4e084da6c2c3
+Author: Xiang, Haihao <haihao.xiang@intel.com>
+Date: Wed Nov 14 12:46:39 2012 +0800
+
+ intel: Add support for VEBOX ring (v2)
+
+ v2: Fix the test for has_vebox
+
+ Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
+ Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
+
+commit b3a3a77823ada2eb37233678b5a49efaec9b75cb
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Thu Apr 25 16:36:15 2013 -0400
+
+ freedreno: add synchronization between mesa and ddx
+
+ Super-cheezy way to synchronization between mesa and ddx.. the
+ SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
+ GET_BUFINFO gives us a way to retrieve it. We use this to stash
+ the timestamp of the last ISSUEIBCMDS on the buffer.
+
+ To avoid an obscene amount of syscalls, we:
+ 1) Only set the timestamp for buffers w/ an flink name, ie.
+ only buffers shared across processes. This is enough to
+ catch the DRI2 buffers.
+ 2) Only set the timestamp for buffers submitted to the 3d ring
+ and only check the timestamps on buffers submitted to the
+ 2d ring. This should be enough to handle synchronizing of
+ presentation blit. We could do synchronization in the other
+ direction too, but that would be problematic if we are using
+ the 3d ring from DDX, since client side wouldn't know this.
+
+ The waiting on timestamp happens before flush, and setting of
+ timestamp happens after flush. It is transparent to the user
+ of libdrm_freedreno as all the tracking of buffers happens via
+ _emit_reloc()..
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit ec3c257eb6958da493aee6f010f51a07d7ba4160
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Apr 25 14:13:52 2013 -0400
+
+ radeon: add new richland pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 439d7d74320a148a2d53aec1ca28eba672ad9353
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Apr 25 14:12:50 2013 -0400
+
+ radeon: add new SI pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 12464a70ed502d9f401931156005afd717a9992f
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Mon Apr 22 14:50:57 2013 -0400
+
+ Add exynos_fimg2d_test to .gitignore
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit 86709ba5373730a438602459e104bf0a9a49559d
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Mon Apr 22 14:49:28 2013 -0400
+
+ freedreno: add gpu-id property
+
+ Gallium driver will need to query this to figure out whether to load the
+ a2xx or a3xx driver.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
commit 9768af201e9aba2093c80a8da3632fe9e4c044fe
Author: Jerome Glisse <jglisse@redhat.com>
Date: Thu Apr 18 15:01:19 2013 -0400
diff --git a/debian/changelog b/debian/changelog
index 51073b4..99ca0fc 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.44-1) UNRELEASED; urgency=low
+libdrm (2.4.45-1) UNRELEASED; urgency=low
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed May 15 19:32:05 2013 +0200
configure.ac: bump version to 2.4.45 for release
diff --git a/configure.ac b/configure.ac
index 803d99d..21f8d3f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.44],
+ [2.4.45],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit e5e51c2110ebf6e1edaa14b7567c5d6a79008a90
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed Apr 24 20:39:45 2013 +0200
radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index d1fdc4b..a74064c 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -159,7 +159,8 @@ static void surf_minify(struct radeon_surface *surf,
surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
@@ -565,7 +566,8 @@ static void eg_surf_minify(struct radeon_surface *surf,
surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
@@ -1459,7 +1461,8 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
}
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index 2babfd7..bbed56f 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -56,6 +56,7 @@
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
+#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
commit 96e90aabc4c0238de2f2d245899f991a3b996587
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon May 13 16:14:28 2013 -0400
radeon: add HAINAN pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 1530394..01c900f 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -391,3 +391,10 @@ CHIPSET(0x6620, OLAND_6620, OLAND)
CHIPSET(0x6621, OLAND_6621, OLAND)
CHIPSET(0x6623, OLAND_6623, OLAND)
CHIPSET(0x6631, OLAND_6631, OLAND)
+
+CHIPSET(0x6660, HAINAN_6660, HAINAN)
+CHIPSET(0x6663, HAINAN_6663, HAINAN)
+CHIPSET(0x6664, HAINAN_6664, HAINAN)
+CHIPSET(0x6665, HAINAN_6665, HAINAN)
+CHIPSET(0x6667, HAINAN_6667, HAINAN)
+CHIPSET(0x666F, HAINAN_666F, HAINAN)
commit c56729cc1564bb4204ca30a18499a78a39f48892
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon May 13 16:15:17 2013 -0400
radeon: add HAINAN family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 288b5e2..d1fdc4b 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -73,6 +73,7 @@ enum radeon_family {
CHIP_PITCAIRN,
CHIP_VERDE,
CHIP_OLAND,
+ CHIP_HAINAN,
CHIP_LAST,
};
commit 040f6b015ef7d9c1bda09f78a8873f6da45d5e95
Author: Dave Airlie <airlied@redhat.com>
Date: Thu May 9 12:55:42 2013 +1000
drm: add qxl drm header file
Now that this driver is merged add the header file.
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/include/drm/Makefile.am b/include/drm/Makefile.am
index 2923ab4..2bc34d2 100644
--- a/include/drm/Makefile.am
+++ b/include/drm/Makefile.am
@@ -36,8 +36,8 @@ klibdrminclude_HEADERS = \
savage_drm.h \
sis_drm.h \
via_drm.h \
- mach64_drm.h
-
+ mach64_drm.h \
+ qxl_drm.h
if HAVE_VMWGFX
klibdrminclude_HEADERS += vmwgfx_drm.h
diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h
new file mode 100644
index 0000000..5d7de70
--- /dev/null
+++ b/include/drm/qxl_drm.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2013 Red Hat
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef QXL_DRM_H
+#define QXL_DRM_H
+
+#include <stddef.h>
+#include "drm/drm.h"
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ *
+ * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
+ * compatibility Keep fields aligned to their size
+ */
+
+#define QXL_GEM_DOMAIN_CPU 0
+#define QXL_GEM_DOMAIN_VRAM 1
+#define QXL_GEM_DOMAIN_SURFACE 2
+
+#define DRM_QXL_ALLOC 0x00
+#define DRM_QXL_MAP 0x01
+#define DRM_QXL_EXECBUFFER 0x02
+#define DRM_QXL_UPDATE_AREA 0x03
+#define DRM_QXL_GETPARAM 0x04
+#define DRM_QXL_CLIENTCAP 0x05
+
+#define DRM_QXL_ALLOC_SURF 0x06
+
+struct drm_qxl_alloc {
+ uint32_t size;
+ uint32_t handle; /* 0 is an invalid handle */
+};
+
+struct drm_qxl_map {
+ uint64_t offset; /* use for mmap system call */
+ uint32_t handle;
+ uint32_t pad;
+};
+
+/*
+ * dest is the bo we are writing the relocation into
+ * src is bo we are relocating.
+ * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
+ * src_offset)
+ */
+#define QXL_RELOC_TYPE_BO 1
+#define QXL_RELOC_TYPE_SURF 2
+
+struct drm_qxl_reloc {
+ uint64_t src_offset; /* offset into src_handle or src buffer */
+ uint64_t dst_offset; /* offset in dest handle */
+ uint32_t src_handle; /* dest handle to compute address from */
+ uint32_t dst_handle; /* 0 if to command buffer */
+ uint32_t reloc_type;
+ uint32_t pad;
+};
+
+struct drm_qxl_command {
+ uint64_t command; /* void* */
+ uint64_t relocs; /* struct drm_qxl_reloc* */
+ uint32_t type;
+ uint32_t command_size;
+ uint32_t relocs_num;
+ uint32_t pad;
+};
+
+/* XXX: call it drm_qxl_commands? */
+struct drm_qxl_execbuffer {
+ uint32_t flags; /* for future use */
+ uint32_t commands_num;
+ uint64_t commands; /* struct drm_qxl_command* */
+};
+
+struct drm_qxl_update_area {
+ uint32_t handle;
+ uint32_t top;
+ uint32_t left;
+ uint32_t bottom;
+ uint32_t right;
+ uint32_t pad;
+};
+
+#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
+#define QXL_PARAM_MAX_RELOCS 2
+struct drm_qxl_getparam {
+ uint64_t param;
+ uint64_t value;
+};
+
+/* these are one bit values */
+struct drm_qxl_clientcap {
+ uint32_t index;
+ uint32_t pad;
+};
+
+struct drm_qxl_alloc_surf {
+ uint32_t format;
+ uint32_t width;
+ uint32_t height;
+ int32_t stride;
+ uint32_t handle;
+ uint32_t pad;
+};
+
+#define DRM_IOCTL_QXL_ALLOC \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
+
+#define DRM_IOCTL_QXL_MAP \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
+
+#define DRM_IOCTL_QXL_EXECBUFFER \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
+ struct drm_qxl_execbuffer)
+
+#define DRM_IOCTL_QXL_UPDATE_AREA \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
+ struct drm_qxl_update_area)
+
+#define DRM_IOCTL_QXL_GETPARAM \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
+ struct drm_qxl_getparam)
+
+#define DRM_IOCTL_QXL_CLIENTCAP \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
+ struct drm_qxl_clientcap)
+
+#define DRM_IOCTL_QXL_ALLOC_SURF \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
+ struct drm_qxl_alloc_surf)
+
+#endif
commit 011999927f76a7e9ba8f047fae4b4e084da6c2c3
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed Nov 14 12:46:39 2012 +0800
intel: Add support for VEBOX ring (v2)
v2: Fix the test for has_vebox
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7e9e9bd..aa983f3 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -303,6 +303,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_LLC 17
#define I915_PARAM_HAS_ALIASING_PPGTT 18
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
+#define I915_PARAM_HAS_VEBOX 22
typedef struct drm_i915_getparam {
int param;
@@ -649,6 +650,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_VEBOX (4<<0)
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
* Gen6+ only supports relative addressing to dynamic state (default) and
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index d21547e..3c73068 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -125,6 +125,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int has_wait_timeout : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
+ unsigned int has_vebox : 1;
bool fenced_relocs;
FILE *aub_file;
@@ -2213,6 +2214,10 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
if (!bufmgr_gem->has_bsd)
return -EINVAL;
break;
+ case I915_EXEC_VEBOX:
+ if (!bufmgr_gem->has_vebox)
+ return -EINVAL;
+ break;
case I915_EXEC_RENDER:
case I915_EXEC_DEFAULT:
break;
@@ -3126,6 +3131,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
} else
bufmgr_gem->has_llc = *gp.value;
+ gp.param = I915_PARAM_HAS_VEBOX;
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
+
if (bufmgr_gem->gen < 4) {
gp.param = I915_PARAM_NUM_FENCES_AVAIL;
gp.value = &bufmgr_gem->available_fences;
commit b3a3a77823ada2eb37233678b5a49efaec9b75cb
Author: Rob Clark <robclark@freedesktop.org>
Date: Thu Apr 25 16:36:15 2013 -0400
freedreno: add synchronization between mesa and ddx
Super-cheezy way to synchronization between mesa and ddx.. the
SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
GET_BUFINFO gives us a way to retrieve it. We use this to stash
the timestamp of the last ISSUEIBCMDS on the buffer.
To avoid an obscene amount of syscalls, we:
1) Only set the timestamp for buffers w/ an flink name, ie.
only buffers shared across processes. This is enough to
catch the DRI2 buffers.
2) Only set the timestamp for buffers submitted to the 3d ring
and only check the timestamps on buffers submitted to the
2d ring. This should be enough to handle synchronizing of
presentation blit. We could do synchronization in the other
direction too, but that would be problematic if we are using
the 3d ring from DDX, since client side wouldn't know this.
The waiting on timestamp happens before flush, and setting of
timestamp happens after flush. It is transparent to the user
of libdrm_freedreno as all the tracking of buffers happens via
_emit_reloc()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c
index 4f566e1..be386b4 100644
--- a/freedreno/freedreno_bo.c
+++ b/freedreno/freedreno_bo.c
@@ -165,12 +165,17 @@ struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
struct drm_gem_open req = {
.name = name,
};
+ struct fd_bo *bo;
if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) {
return NULL;
}
- return bo_from_handle(dev, req.size, req.handle);
+ bo = bo_from_handle(dev, req.size, req.handle);
+ if (bo)
+ bo->name = name;
+
+ return bo;
}
struct fd_bo * fd_bo_ref(struct fd_bo *bo)
@@ -272,3 +277,64 @@ uint32_t fd_bo_gpuaddr(struct fd_bo *bo, uint32_t offset)
}
return bo->gpuaddr + offset;
}
+
+/*
+ * Super-cheezy way to synchronization between mesa and ddx.. the
+ * SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
+ * GET_BUFINFO gives us a way to retrieve it. We use this to stash
+ * the timestamp of the last ISSUEIBCMDS on the buffer.
+ *
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