mesa: Changes to 'upstream-experimental'
Makefile.am | 2
bin/.cherry-ignore | 6
bin/bugzilla_mesa.sh | 52 +
bin/get-pick-list.sh | 6
bin/shortlog_mesa.sh | 6
configure.ac | 2
docs/relnotes-9.1.2.html | 4
docs/relnotes-9.1.3.html | 228 +++++
include/pci_ids/r600_pci_ids.h | 2
include/pci_ids/radeonsi_pci_ids.h | 3
src/egl/drivers/dri2/egl_dri2.c | 6
src/egl/drivers/dri2/platform_x11.c | 21
src/gallium/auxiliary/gallivm/lp_bld_sample.c | 2
src/gallium/auxiliary/util/u_blitter.c | 113 ++
src/gallium/auxiliary/util/u_blitter.h | 18
src/gallium/drivers/nvc0/nvc0_video.c | 4
src/gallium/drivers/r600/r600_blit.c | 31
src/gallium/drivers/r600/r600_pipe.c | 39
src/gallium/drivers/r600/r600_pipe.h | 7
src/gallium/drivers/r600/r600_shader.c | 51 -
src/gallium/drivers/r600/r600_texture.c | 10
src/gallium/drivers/radeonsi/r600_blit.c | 18
src/gallium/include/state_tracker/st_api.h | 1
src/gallium/state_trackers/dri/common/dri_context.c | 2
src/gallium/state_trackers/dri/common/dri_screen.c | 3
src/gallium/winsys/sw/xlib/xlib_sw_winsys.c | 6
src/glsl/ast_to_hir.cpp | 15
src/glsl/ir_constant_expression.cpp | 2
src/glsl/link_varyings.cpp | 36
src/glsl/lower_jumps.cpp | 4
src/glsl/lower_packed_varyings.cpp | 8
src/glsl/ralloc.c | 2
src/glx/glxcmds.c | 4
src/mesa/drivers/dri/i965/brw_context.h | 26
src/mesa/drivers/dri/i965/brw_fs.cpp | 49 -
src/mesa/drivers/dri/i965/brw_fs.h | 3
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 43 -
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 1
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14
src/mesa/drivers/dri/i965/brw_lower_texture_gradients.cpp | 27
src/mesa/drivers/dri/i965/brw_misc_state.c | 195 ++--
src/mesa/drivers/dri/i965/brw_shader.cpp | 3
src/mesa/drivers/dri/i965/brw_state.h | 5
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 4
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 7
src/mesa/drivers/dri/i965/brw_vtbl.c | 2
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 35
src/mesa/drivers/dri/i965/gen6_sol.c | 11
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 103 ++
src/mesa/drivers/dri/i965/gen7_misc_state.c | 93 --
src/mesa/drivers/dri/i965/gen7_sol_state.c | 18
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 8
src/mesa/drivers/dri/intel/intel_context.h | 18
src/mesa/drivers/dri/intel/intel_fbo.c | 4
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 6
src/mesa/drivers/dri/intel/intel_tex.c | 4
src/mesa/main/context.c | 2
src/mesa/main/extensions.c | 4
src/mesa/main/format_unpack.c | 597 +++++++++++++-
src/mesa/main/get.c | 19
src/mesa/main/get_hash_params.py | 14
src/mesa/main/hash.c | 4
src/mesa/main/imports.h | 6
src/mesa/main/mtypes.h | 1
src/mesa/main/shaderapi.c | 6
src/mesa/main/stencil.c | 5
src/mesa/main/version.h | 4
src/mesa/program/prog_cache.c | 11
src/mesa/state_tracker/st_atom_constbuf.c | 1
src/mesa/state_tracker/st_atom_depth.c | 2
src/mesa/state_tracker/st_extensions.c | 3
src/mesa/swrast/s_blit.c | 49 -
74 files changed, 1790 insertions(+), 359 deletions(-)
New commits:
commit f32ec82a8cfcabc5b7596796f36afe7986651f02
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Tue May 21 12:59:17 2013 -0700
docs: 9.1.3 release notes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/docs/relnotes-9.1.3.html b/docs/relnotes-9.1.3.html
new file mode 100644
index 0000000..cff9370
--- /dev/null
+++ b/docs/relnotes-9.1.3.html
@@ -0,0 +1,228 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.3 Release Notes / May 21st, 2013</h1>
+
+<p>
+Mesa 9.1.3 is a bug fix release which fixes bugs found since the 9.1.1 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1. OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+TBD
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=39251";>Bug 39251</a> - Second Life viewers from release 2.7.4.235167 to the last 3.4.0.264911 crash on start.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=47478";>Bug 47478</a> - [wine] GLX_DONT_CARE does not work for GLX_DRAWABLE_TYPE or GLX_RENDER_TYPE</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=56416";>Bug 56416</a> - [SNB bisected] SNB hang with rc6 and hiz on glxgears (and other GL apps) immediately after xinit.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=57436";>Bug 57436</a> - [GLSL1.40 IVB/HSW]Piglit spec/glsl-1.40/compiler_built-in-functions/inverse-mat2.frag fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61554";>Bug 61554</a> - [ivb] Mesa 9.1 performance regression on KWin's Lanczos shader</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61773";>Bug 61773</a> - abort is an incredibly not-smart way to handle IR validation</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62868";>Bug 62868</a> - solaris build broken with missing ffsll</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=62999";>Bug 62999</a> - glXChooseFBConfig with GLX_DRAWABLE_TYPE, GLX_DONT_CARE fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63078";>Bug 63078</a> - EGL X11 Regression: Maximum swap interval is 0 (worked with 9.0)</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=63447";>Bug 63447</a> - [i965 Bisected]Ogles1conform/Ogles2conform/Ogles3conform cases segfault</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=64662";>Bug 64662</a> - [SNB 9.1 Bisected]Ogles2conform GL2ExtensionTests/depth_texture_cube_map/depth_texture_cube_map.test fail</li>
+
+</ul>
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+ git log mesa-9.1.2..mesa-9.1.3
+</pre>
+
+<p>Alex Deucher (2):</p>
+<ul>
+ <li>r600g: add new richland pci ids</li>
+ <li>radeonsi: add new SI pci ids</li>
+</ul>
+
+<p>Alexander Monakov (1):</p>
+<ul>
+ <li>Honor GLX_DONT_CARE in MATCH_MASK</li>
+</ul>
+
+<p>Andreas Boll (2):</p>
+<ul>
+ <li>mesa: Add a script to generate the list of fixed bugs</li>
+ <li>mesa: add usage examples to get-pick-list and shortlog scripts</li>
+</ul>
+
+<p>Aras Pranckevicius (1):</p>
+<ul>
+ <li>GLSL: fix lower_jumps to report progress properly</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+ <li>mesa: remove platform checks around __builtin_ffs, __builtin_ffsll</li>
+ <li>gallium/u_blitter: fix is_blit_generic_supported() stencil checking</li>
+ <li>mesa: enable GL_ARB_texture_float if TEXTURE_FLOAT_ENABLED is defined</li>
+</ul>
+
+<p>Chad Versace (2):</p>
+<ul>
+ <li>egl/dri2: Fix min/max swap interval of configs</li>
+ <li>intel: Allocate hiz in intel_renderbuffer_move_to_temp()</li>
+</ul>
+
+<p>Chris Forbes (2):</p>
+<ul>
+ <li>i965/fs: Don't try to use bogus interpolation modes pre-Gen6.</li>
+ <li>mesa: don't memcmp() off the end of a cache key.</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+ <li>st/mesa: fix UBO offsets.</li>
+ <li>ralloc: don't write to memory in case of alloc fail.</li>
+</ul>
+
+<p>Eric Anholt (11):</p>
+<ul>
+ <li>i965/fs: Remove creation of a MOV instruction that's never used.</li>
+ <li>i965/fs: Move varying uniform offset compuation into the helper func.</li>
+ <li>i965: Make the constant surface interface take a normal byte size.</li>
+ <li>i965/fs: Avoid inappropriate optimization with regs_written > 1.</li>
+ <li>i965/fs: Do CSE on gen7's varying-index pull constant loads.</li>
+ <li>i965/fs: Clean up the setup of gen4 simd16 message destinations.</li>
+ <li>i965/gen7: Skip resetting SOL offsets at batch start with HW contexts.</li>
+ <li>i965/gen6: Reduce updates of transform feedback offsets with HW contexts.</li>
+ <li>i965: Fix SNB GPU hangs when a blorp batch is the first thing to execute.</li>
+ <li>i965: Fix hangs on HSW since the gen6 blorp fix.</li>
+ <li>i965: Disable write masking when setting up texturing m0.</li>
+</ul>
+
+<p>Haixia Shi (1):</p>
+<ul>
+ <li>ACTIVE_UNIFORM_MAX_LENGTH should include 3 extra characters for arrays.</li>
+</ul>
+
+<p>Ian Romanick (11):</p>
+<ul>
+ <li>docs: Add 9.1.2 release md5sums</li>
+ <li>mesa: Note that patch 0967c36 shouldn't actually get picked to the 9.1 branch</li>
+ <li>mesa: NULL check the pointer before trying to dereference it</li>
+ <li>egl/dri2: NULL check value returned by dri2_create_surface</li>
+ <li>mesa: Don't leak shared state when context initialization fails</li>
+ <li>mesa: Don't leak gl_context::BeginEnd at context destruction</li>
+ <li>mesa/swrast: Refactor no-memory error checking in blit_linear</li>
+ <li>mesa/swrast: Move free calls outside the attachment loop</li>
+ <li>intel: Don't dereference a NULL pointer of calloc fails</li>
+ <li>mesa: Note that a824692 is already back ported</li>
+ <li>mesa: Bump version to 9.1.3</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+ <li>winsys/sw/xlib: Prevent shared memory segment leakage.</li>
+</ul>
+
+<p>Kenneth Graunke (9):</p>
+<ul>
+ <li>mesa: Add new ctx->Stencil._WriteEnabled derived state flag.</li>
+ <li>i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.</li>
+ <li>mesa: Fix unpack function for ETC2_SRGB8_PUNCHTHROUGH_ALPHA1.</li>
+ <li>mesa: Add an unpack function for ARGB2101010_UINT.</li>
+ <li>mesa: Add unpack functions for R/RG/RGB [U]INT8/16/32 formats.</li>
+ <li>mesa: Add unpack functions for A/I/L/LA [U]INT8/16/32 formats.</li>
+ <li>glsl: Ignore redundant prototypes after a function's been defined.</li>
+ <li>i965: Lower textureGrad() for samplerCubeShadow.</li>
+ <li>i965/vs: Fix textureGrad() with shadow samplers on Haswell.</li>
+</ul>
+
+<p>Maarten Lankhorst (1):</p>
+<ul>
+ <li>nvc0: Fix fd leak in nvc0_create_decoder</li>
+</ul>
+
+<p>Marek Olšák (5):</p>
+<ul>
+ <li>radeonsi: add more cases for copying unsupported formats to resource_copy_region</li>
+ <li>mesa: fix glGet queries depending on derived framebuffer state (v2)</li>
+ <li>gallium/u_blitter: implement buffer clearing</li>
+ <li>r600g: initialize CMASK and HTILE with the GPU using streamout</li>
+ <li>st/mesa: depth-stencil-alpha state also depends on _NEW_BUFFERS</li>
+</ul>
+
+<p>Martin Andersson (1):</p>
+<ul>
+ <li>r600g: Fix UMAD on Cayman</li>
+</ul>
+
+<p>Michel Dänzer (1):</p>
+<ul>
+ <li>radeonsi: Handle arbitrary 2-byte formats in resource_copy_region</li>
+</ul>
+
+<p>Paul Berry (7):</p>
+<ul>
+ <li>glsl: Fix array indexing when constant folding built-in functions.</li>
+ <li>i965: Reduce code duplication in handling of depth, stencil, and HiZ.</li>
+ <li>glsl/linker: fix varying packing for non-flat integer varyings.</li>
+ <li>glsl: Document lower_packed_varyings' "flat" requirement with an assert.</li>
+ <li>glsl/linker: Adapt flat varying handling in preparation for geometry shaders.</li>
+ <li>glsl/linker: Reduce scope of non-flat integer varying fix.</li>
+ <li>intel: Do a depth resolve before copying images between miptrees.</li>
+</ul>
+
+<p>Ralf Jung (1):</p>
+<ul>
+ <li>egl/x11: Fix initialisation of swap_interval</li>
+</ul>
+
+<p>Roland Scheidegger (1):</p>
+<ul>
+ <li>gallivm: fix small but severe bug in handling multiple lod level strides</li>
+</ul>
+
+<p>Vadim Girlin (1):</p>
+<ul>
+ <li>gallium: handle drirc disable_glsl_line_continuations option</li>
+</ul>
+
+</div>
+</body>
+</html>
commit e9be1f7ce5d7f24e68ed63136cdfd8b3c1899065
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Tue May 21 12:49:28 2013 -0700
mesa: Bump version to 9.1.3
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/Makefile.am b/Makefile.am
index 558b965..0c398cb 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -36,7 +36,7 @@ check-local:
# Rules for making release tarballs
-PACKAGE_VERSION=9.1.2
+PACKAGE_VERSION=9.1.3
PACKAGE_DIR = Mesa-$(PACKAGE_VERSION)
PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)
diff --git a/configure.ac b/configure.ac
index b9fcb0b..36065f1 100644
--- a/configure.ac
+++ b/configure.ac
@@ -6,7 +6,7 @@ dnl Tell the user about autoconf.html in the --help output
m4_divert_once([HELP_END], [
See docs/autoconf.html for more details on the options for Mesa.])
-AC_INIT([Mesa], [9.1.2],
+AC_INIT([Mesa], [9.1.3],
[https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa])
AC_CONFIG_AUX_DIR([bin])
AC_CONFIG_MACRO_DIR([m4])
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index c22f2c8..12e7409 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -34,8 +34,8 @@ struct gl_context;
/* Mesa version */
#define MESA_MAJOR 9
#define MESA_MINOR 1
-#define MESA_PATCH 2
-#define MESA_VERSION_STRING "9.1.2"
+#define MESA_PATCH 3
+#define MESA_VERSION_STRING "9.1.3"
/* To make version comparison easy */
#define MESA_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
commit caeab4d170229ec85cf5d3e79ce7f7e2c9cabf44
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Tue May 21 12:47:32 2013 -0700
mesa: Note that a824692 is already back ported
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 32393f3..2a5fae2 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -11,3 +11,6 @@ dbf94d105a48b7aafb2c8cf64d8b4392d87efea1 glsl: Replace constant-index vector arr
# This patch is superceded by 34a4fc5
0967c362bf378b7415c30ca6d9523d3b2a3a7f5d i965: Fix an inconsistency inb the VUE map with gl_ClipVertex on gen4/5.
+
+# This patch was backported as c3eb301
+a8246927e35a49097f70cffb7fa8dd05ec1365e1 r600g: Fix UMAD on Cayman
commit cbe0e50247c909a7d34f71d9a1a4852b6c3af472
Author: Paul Berry <stereotype441@gmail.com>
Date: Thu May 16 14:12:15 2013 -0700
intel: Do a depth resolve before copying images between miptrees.
When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage()
to reassemble a depth miptree that has been broken apart into pieces
(to deal with misalignment of levels/layers within the miptree), it
just copies the depth data, not the HiZ data. This is reasonable,
since the alignment restrictions of HiZ are a large part of the reason
why the miptree had to be broken apart in the first place. However,
in order for the depth copy to be sufficient, we need to do a depth
resolve first, to make sure any deferred depth writes that are in the
HiZ buffer get performed.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and
https://bugs.freedesktop.org/show_bug.cgi?id=64659.
NOTE: This is a candidate for stable release branches.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
(cherry picked from commit 46ea8041074df79561f9771e2ecf198f2cbd088f)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index a063f87..43f3779 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -725,6 +725,12 @@ intel_miptree_copy_slice(struct intel_context *intel,
dst_mt, dst_x, dst_y, dst_mt->region->pitch,
width, height);
+ /* Since we are about to copy depth data using either the blitter or swrast
+ * (neither of which respect HiZ), we need to do a depth resolve first.
+ */
+ intel_miptree_slice_resolve_depth(intel, src_mt, level, slice);
+ intel_miptree_slice_resolve_depth(intel, dst_mt, level, slice);
+
if (!intelEmitCopyBlit(intel,
dst_mt->region->cpp,
src_mt->region->pitch, src_mt->region->bo,
commit c3eb301a3a09f4b1b471afdbd16a4f986702f194
Author: Martin Andersson <g02maran@gmail.com>
Date: Tue Apr 2 22:43:33 2013 +0200
r600g: Fix UMAD on Cayman
The multiplication part of tgsi_umad did not work on Cayman, because it did
not populate the correct vector slots.
This fixed hardlocks in the EXT_transform_feedback/order tests.
NOTE: This is a candidate for the stable branches.
(might not be easy to cherry-pick though)
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Stable backport:
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index e8992ba..e0fb18b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -5760,7 +5760,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
- int i, j, r;
+ int i, j, k, r;
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
/* src0 * src1 */
@@ -5768,21 +5768,40 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
continue;
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-
- alu.dst.chan = i;
- alu.dst.sel = ctx->temp_reg;
- alu.dst.write = 1;
-
- alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
- for (j = 0; j < 2; j++) {
- r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
- }
-
- alu.last = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
+ if (ctx->bc->chip_class == CAYMAN) {
+ for (j = 0; j < 4; j++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.dst.chan = j;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.write = (j == i);
+
+ if (j == 3)
+ alu.last = 1;
+ alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+ for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
+ r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
+ }
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ } else {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+
+ alu.dst.chan = i;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.write = 1;
+
+ alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
+ for (j = 0; j < 2; j++) {
+ r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
+ }
+
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
}
commit 496996010561463bf0f2e2a7632978c548065b98
Author: Chad Versace <chad.versace@linux.intel.com>
Date: Fri Apr 5 15:18:00 2013 -0700
intel: Allocate hiz in intel_renderbuffer_move_to_temp()
When moving the renderbuffer to a new miptree, we neglected to allocate
the hiz buffer for the new miptree. Oops.
Fixes all Piglit depthstencil-render-miplevels tests from crash to pass on
Sandybridge.
Note: This is a candidate for the 9.1 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
(cherry picked from commit aa391976dfa12479185d9eeed1f2a0b4dce6c49b)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 37ecbd1..41412ee 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -999,6 +999,10 @@ intel_renderbuffer_move_to_temp(struct intel_context *intel,
irb->mt->num_samples,
false /* force_y_tiling */);
+ if (intel->vtbl.is_hiz_depth_format(intel, new_mt->format)) {
+ intel_miptree_alloc_hiz(intel, new_mt, irb->mt->num_samples);
+ }
+
intel_miptree_copy_teximage(intel, intel_image, new_mt);
intel_miptree_reference(&irb->mt, intel_image->mt);
intel_renderbuffer_set_draw_offset(irb);
commit 22f7bcd44f92b93fad40b5a78fe476dc3715b640
Author: Eric Anholt <eric@anholt.net>
Date: Thu Aug 30 11:07:52 2012 -0700
i965: Disable write masking when setting up texturing m0.
v2/Kayden: Also disable write masking in the vec4 backend.
Fixes 78 oglconform glsl-bif-tex-* subcases.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com> [v1]
Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
(cherry picked from commit 86536a321d9d26137587affe687a07da71f0b526)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 365a2ec..aa3a616 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -469,6 +469,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
*/
if (inst->texture_offset) {
brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
/* Explicitly set up the message header by copying g0 to the MRF. */
brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index e395ada..863ff7c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -335,6 +335,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
*/
if (inst->texture_offset) {
/* Explicitly set up the message header by copying g0 to the MRF. */
+ brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
@@ -344,7 +346,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
BRW_REGISTER_TYPE_UD),
brw_imm_uw(inst->texture_offset));
- brw_set_access_mode(p, BRW_ALIGN_16);
+ brw_pop_insn_state(p);
} else if (inst->header_present) {
/* Set up an implied move from g0 to the MRF. */
src = brw_vec8_grf(0, 0);
commit 3933e653289d31d38d233cd0ddfebe6bd2d4eb04
Author: Chad Versace <chad.versace@linux.intel.com>
Date: Tue Apr 23 04:17:48 2013 +0200
egl/dri2: Fix min/max swap interval of configs
The commit below exposed a bug in dri2_add_config.
commit 3998f8c6b5da1a223926249755e54d8f701f81ab
Author: Ralf Jung <post@ralfj.de>
Date: Tue Apr 9 14:09:50 2013 +0200
egl/x11: Fix initialisation of swap_interval
This little code snippet near the bottom of dri2_add_config,
if (double_buffer) {
...
conf->base.MinSwapInterval = dri2_dpy->min_swap_interval;
conf->base.MaxSwapInterval = dri2_dpy->max_swap_interval;
}
it never did what it claimed to do. The assignment never changed the value
of conf->base.MaxSwapInterval, because dri2_dpy->max_swap_interval was,
until the above exposing commit, unitialized here. That is,
conf->base.MaxSwapInterval was 0 before and after assignment. Ditto for
the min swap interval.
Above the troublesome code snippet, the call to _eglFilterArray rejects
the config as unmatching if its swap interval bounds differ from the base
config's. Before the exposing commit, at the call to _eglFilterArray, the
swap interval bounds were always [0,0], and hence no config was rejected
due to swap interval.
After the exposing commit, _eglFilterArray incorrectly rejected some
configs, which prevented dri2_egl_config::dri_double_config from getting
set for the rejected config, which resulted in a NULL pointer getting
passed into dri2CreateNewDrawable, and then segfault.
The solution: set the swap interval bounds before _eglFilterArray.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63447
Tested-by: Lu Hua <huax.lu@intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
(cherry picked from commit d3dfce32768dd698d12948987f93680ce02d465a)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index e17d5be..0f4e948 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -221,6 +221,9 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id,
base.RenderableType = disp->ClientAPIs;
base.Conformant = disp->ClientAPIs;
+ base.MinSwapInterval = dri2_dpy->min_swap_interval;
+ base.MaxSwapInterval = dri2_dpy->max_swap_interval;
+
if (!_eglValidateConfig(&base, EGL_FALSE)) {
_eglLog(_EGL_DEBUG, "DRI2: failed to validate config %d", id);
return NULL;
@@ -268,9 +271,6 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id,
if (double_buffer) {
surface_type &= ~EGL_PIXMAP_BIT;
-
- conf->base.MinSwapInterval = dri2_dpy->min_swap_interval;
- conf->base.MaxSwapInterval = dri2_dpy->max_swap_interval;
}
conf->base.SurfaceType |= surface_type;
commit 1e043ebe034b6e33b4c5228770db397b22fd26e0
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Thu Apr 18 09:32:39 2013 +0200
mesa: add usage examples to get-pick-list and shortlog scripts
NOTE: This is a candidate for the stable branches.
(cherry picked from commit b8e41db053a7cceba81650b4a94fff65c06ef86e)
diff --git a/bin/get-pick-list.sh b/bin/get-pick-list.sh
index d3ac511..d2b76e7 100755
--- a/bin/get-pick-list.sh
+++ b/bin/get-pick-list.sh
@@ -1,6 +1,12 @@
#!/bin/sh
# Script for generating a list of candidates for cherry-picking to a stable branch
+#
+# Usage examples:
+#
+# $ bin/get-pick-list.sh
+# $ bin/get-pick-list.sh > picklist
+# $ bin/get-pick-list.sh | tee picklist
# Grep for commits with "cherry picked from commit" in the commit message.
git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\
diff --git a/bin/shortlog_mesa.sh b/bin/shortlog_mesa.sh
index b20c52f..2ba0815 100755
--- a/bin/shortlog_mesa.sh
+++ b/bin/shortlog_mesa.sh
@@ -2,6 +2,12 @@
# This script is used to generate the list of changes that
# appears in the release notes files, with HTML formatting.
+#
+# Usage examples:
+#
+# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3
+# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3 > changes
+# $ bin/shortlog_mesa.sh mesa-9.0.2..mesa-9.0.3 | tee changes
typeset -i in_log=0
commit 8487315e6e551c5ae78b8e0970b583ff32dbcdf5
Author: Andreas Boll <andreas.boll.dev@gmail.com>
Date: Wed Apr 17 18:14:44 2013 +0200
mesa: Add a script to generate the list of fixed bugs
This list appears in the fixed bugs section of the release notes.
v2: Add usage examples
NOTE: This is a candidate for the stable branches.
(cherry picked from commit ca79b72c00f035e2b48d554b42361829523f38ff)
diff --git a/bin/bugzilla_mesa.sh b/bin/bugzilla_mesa.sh
new file mode 100755
index 0000000..491ca0e
--- /dev/null
+++ b/bin/bugzilla_mesa.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+
+# This script is used to generate the list of fixed bugs that
+# appears in the release notes files, with HTML formatting.
+#
+# Note: This script could take a while until all details have
+# been fetched from bugzilla.
+#
+# Usage examples:
+#
+# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3
+# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 > bugfixes
+# $ bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 | tee bugfixes
+# $ DRYRUN=yes bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3
+# $ DRYRUN=yes bin/bugzilla_mesa.sh mesa-9.0.2..mesa-9.0.3 | wc -l
+
+
+# regex pattern: trim before url
+trim_before='s/.*\(http\)/\1/'
+
+# regex pattern: trim after url
+trim_after='s/\(show_bug.cgi?id=[0-9]*\).*/\1/'
+
+# regex pattern: always use https
+use_https='s/http:/https:/'
+
+# extract fdo urls from commit log
+urls=$(git log $* | grep 'bugs.freedesktop.org/show_bug' | sed -e $trim_before -e $trim_after -e $use_https | sort | uniq)
+
+# if DRYRUN is set to "yes", simply print the URLs and don't fetch the
+# details from fdo bugzilla.
+#DRYRUN=yes
+
+if [ "x$DRYRUN" = xyes ]; then
+ for i in $urls
+ do
+ echo $i
+ done
+else
+ echo "<ul>"
+ echo ""
+
+ for i in $urls
+ do
+ id=$(echo $i | cut -d'=' -f2)
+ summary=$(wget --quiet -O - $i | grep -e '<title>.*</title>' | sed -e 's/ *<title>Bug [0-9]\+ – \(.*\)<\/title>/\1/')
+ echo "<li><a href=\"$i\">Bug $id</a> - $summary</li>"
+ echo ""
+ done
+
+ echo "</ul>"
+fi
commit 7881aae604aa6f6dbb431a850641214115bfcd3a
Author: Eric Anholt <eric@anholt.net>
Date: Mon May 6 20:44:21 2013 -0700
i965: Fix hangs on HSW since the gen6 blorp fix.
The constant packets for gen6 are too small for gen7, and while IVB seems
happy with them HSW blows up. Fix it by emitting the correct packets on
gen7, for all stages.
v2: Include the packets instead of just skipping them.
NOTE: This is a candidate for the stable branches.
Reviewed-and-tested-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 5d06c9ea0f1aa2f312660413acd1bd6a1dafe1a6)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 21caa0a..6452169 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -276,6 +276,37 @@ gen7_blorp_emit_sampler_state(struct brw_context *brw,
}
+/* 3DSTATE_VS
+ *
+ * Disable vertex shader.
+ */
+static void
+gen7_blorp_emit_vs_disable(struct brw_context *brw,
+ const brw_blorp_params *params)
+{
+ struct intel_context *intel = &brw->intel;
+
+ BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
+ BEGIN_BATCH(6);
+ OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
+
+
/* 3DSTATE_HS
*
* Disable the hull shader.
@@ -287,6 +318,16 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw,
struct intel_context *intel = &brw->intel;
BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
+ BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -327,6 +368,16 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
{
struct intel_context *intel = &brw->intel;
+ BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
OUT_BATCH(0);
@@ -337,6 +388,36 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
ADVANCE_BATCH();
}
+/* 3DSTATE_GS
+ *
+ * Disable the geometry shader.
+ */
+static void
+gen7_blorp_emit_gs_disable(struct brw_context *brw,
+ const brw_blorp_params *params)
+{
+ struct intel_context *intel = &brw->intel;
+
+ BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
+ BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
/* 3DSTATE_STREAMOUT
*
@@ -573,6 +654,22 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
ADVANCE_BATCH();
}
+static void
+gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
+ const brw_blorp_params *params)
+{
+ struct intel_context *intel = &brw->intel;
+
+ BEGIN_BATCH(7);
+ OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
static void
gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
@@ -777,11 +874,11 @@ gen7_blorp_exec(struct intel_context *intel,
wm_surf_offset_texture);
sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
}
- gen6_blorp_emit_vs_disable(brw, params);
+ gen7_blorp_emit_vs_disable(brw, params);
gen7_blorp_emit_hs_disable(brw, params);
gen7_blorp_emit_te_disable(brw, params);
gen7_blorp_emit_ds_disable(brw, params);
- gen6_blorp_emit_gs_disable(brw, params);
+ gen7_blorp_emit_gs_disable(brw, params);
gen7_blorp_emit_streamout_disable(brw, params);
gen6_blorp_emit_clip_disable(brw, params);
gen7_blorp_emit_sf_config(brw, params);
@@ -791,6 +888,8 @@ gen7_blorp_exec(struct intel_context *intel,
wm_bind_bo_offset);
gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
+ } else {
+ gen7_blorp_emit_constant_ps_disable(brw, params);
}
gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
gen7_blorp_emit_cc_viewport(brw, params);
commit 23fb93a9186caf7d9520495f29a37db37deabf83
Author: Eric Anholt <eric@anholt.net>
Date: Wed May 1 16:08:12 2013 -0700
i965: Fix SNB GPU hangs when a blorp batch is the first thing to execute.
The GPU apparently goes looking for constants even though there are no
shader stages enabled, and gets stuck because we haven't told it there are
no constants to collect. If any other user of the 3D pipeline had run
(even the Render accel of the X server!) since power on, then the in-GPU
constant buffers would have been set up with some contents we didn't use,
and we would succeed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56416
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Dave Airlie <airlied@redhat.com>
NOTE: This is a candidate for the stable branches.
(cherry picked from commit 1dfea559c3f188a7a82a4abc09765ba09e939522)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 3834ae2..4fbcea4 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -594,6 +594,15 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
intel_emit_post_sync_nonzero_flush(intel);
}
+ /* Disable the push constant buffers. */
+ BEGIN_BATCH(5);
+ OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
Reply to: