libdrm: Changes to 'debian-experimental'
.gitignore | 1
ChangeLog | 116 +++++++++++++++++++++++++++++
configure.ac | 2
debian/changelog | 2
freedreno/freedreno_bo.c | 68 +++++++++++++++++
freedreno/freedreno_drmif.h | 1
freedreno/freedreno_pipe.c | 26 ++++++
freedreno/freedreno_priv.h | 10 ++
freedreno/freedreno_ringbuffer.c | 4 -
include/drm/Makefile.am | 4 -
include/drm/i915_drm.h | 2
include/drm/qxl_drm.h | 152 +++++++++++++++++++++++++++++++++++++++
intel/intel_bufmgr_gem.c | 9 ++
radeon/r600_pci_ids.h | 12 +++
radeon/radeon_surface.c | 10 +-
radeon/radeon_surface.h | 1
16 files changed, 409 insertions(+), 11 deletions(-)
New commits:
commit ef470fa9bd9a65897788519f67d4b8fa20750c60
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Wed May 15 21:57:50 2013 +0200
bump changelogs
diff --git a/ChangeLog b/ChangeLog
index 74b1902..51c7a9b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,119 @@
+commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed May 15 19:32:05 2013 +0200
+
+ configure.ac: bump version to 2.4.45 for release
+
+commit e5e51c2110ebf6e1edaa14b7567c5d6a79008a90
+Author: Marek Olšák <maraeo@gmail.com>
+Date: Wed Apr 24 20:39:45 2013 +0200
+
+ radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
+
+ Signed-off-by: Marek Olšák <maraeo@gmail.com>
+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 96e90aabc4c0238de2f2d245899f991a3b996587
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon May 13 16:14:28 2013 -0400
+
+ radeon: add HAINAN pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit c56729cc1564bb4204ca30a18499a78a39f48892
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon May 13 16:15:17 2013 -0400
+
+ radeon: add HAINAN family
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 040f6b015ef7d9c1bda09f78a8873f6da45d5e95
+Author: Dave Airlie <airlied@redhat.com>
+Date: Thu May 9 12:55:42 2013 +1000
+
+ drm: add qxl drm header file
+
+ Now that this driver is merged add the header file.
+
+ Signed-off-by: Dave Airlie <airlied@redhat.com>
+
+commit 011999927f76a7e9ba8f047fae4b4e084da6c2c3
+Author: Xiang, Haihao <haihao.xiang@intel.com>
+Date: Wed Nov 14 12:46:39 2012 +0800
+
+ intel: Add support for VEBOX ring (v2)
+
+ v2: Fix the test for has_vebox
+
+ Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
+ Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
+
+commit b3a3a77823ada2eb37233678b5a49efaec9b75cb
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Thu Apr 25 16:36:15 2013 -0400
+
+ freedreno: add synchronization between mesa and ddx
+
+ Super-cheezy way to synchronization between mesa and ddx.. the
+ SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
+ GET_BUFINFO gives us a way to retrieve it. We use this to stash
+ the timestamp of the last ISSUEIBCMDS on the buffer.
+
+ To avoid an obscene amount of syscalls, we:
+ 1) Only set the timestamp for buffers w/ an flink name, ie.
+ only buffers shared across processes. This is enough to
+ catch the DRI2 buffers.
+ 2) Only set the timestamp for buffers submitted to the 3d ring
+ and only check the timestamps on buffers submitted to the
+ 2d ring. This should be enough to handle synchronizing of
+ presentation blit. We could do synchronization in the other
+ direction too, but that would be problematic if we are using
+ the 3d ring from DDX, since client side wouldn't know this.
+
+ The waiting on timestamp happens before flush, and setting of
+ timestamp happens after flush. It is transparent to the user
+ of libdrm_freedreno as all the tracking of buffers happens via
+ _emit_reloc()..
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit ec3c257eb6958da493aee6f010f51a07d7ba4160
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Apr 25 14:13:52 2013 -0400
+
+ radeon: add new richland pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 439d7d74320a148a2d53aec1ca28eba672ad9353
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu Apr 25 14:12:50 2013 -0400
+
+ radeon: add new SI pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit 12464a70ed502d9f401931156005afd717a9992f
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Mon Apr 22 14:50:57 2013 -0400
+
+ Add exynos_fimg2d_test to .gitignore
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit 86709ba5373730a438602459e104bf0a9a49559d
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Mon Apr 22 14:49:28 2013 -0400
+
+ freedreno: add gpu-id property
+
+ Gallium driver will need to query this to figure out whether to load the
+ a2xx or a3xx driver.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
commit 9768af201e9aba2093c80a8da3632fe9e4c044fe
Author: Jerome Glisse <jglisse@redhat.com>
Date: Thu Apr 18 15:01:19 2013 -0400
diff --git a/debian/changelog b/debian/changelog
index 51073b4..99ca0fc 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.44-1) UNRELEASED; urgency=low
+libdrm (2.4.45-1) UNRELEASED; urgency=low
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
commit 63aeae123848d0bfbc0a35102cb9717cf496eab6
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed May 15 19:32:05 2013 +0200
configure.ac: bump version to 2.4.45 for release
diff --git a/configure.ac b/configure.ac
index 803d99d..21f8d3f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.44],
+ [2.4.45],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit e5e51c2110ebf6e1edaa14b7567c5d6a79008a90
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed Apr 24 20:39:45 2013 +0200
radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index d1fdc4b..a74064c 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -159,7 +159,8 @@ static void surf_minify(struct radeon_surface *surf,
surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
@@ -565,7 +566,8 @@ static void eg_surf_minify(struct radeon_surface *surf,
surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
@@ -1459,7 +1461,8 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
}
- if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & RADEON_SURF_FMASK)) {
if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
surflevel->mode = RADEON_SURF_MODE_1D;
return;
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index 2babfd7..bbed56f 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -56,6 +56,7 @@
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
+#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
commit 96e90aabc4c0238de2f2d245899f991a3b996587
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon May 13 16:14:28 2013 -0400
radeon: add HAINAN pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 1530394..01c900f 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -391,3 +391,10 @@ CHIPSET(0x6620, OLAND_6620, OLAND)
CHIPSET(0x6621, OLAND_6621, OLAND)
CHIPSET(0x6623, OLAND_6623, OLAND)
CHIPSET(0x6631, OLAND_6631, OLAND)
+
+CHIPSET(0x6660, HAINAN_6660, HAINAN)
+CHIPSET(0x6663, HAINAN_6663, HAINAN)
+CHIPSET(0x6664, HAINAN_6664, HAINAN)
+CHIPSET(0x6665, HAINAN_6665, HAINAN)
+CHIPSET(0x6667, HAINAN_6667, HAINAN)
+CHIPSET(0x666F, HAINAN_666F, HAINAN)
commit c56729cc1564bb4204ca30a18499a78a39f48892
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Mon May 13 16:15:17 2013 -0400
radeon: add HAINAN family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 288b5e2..d1fdc4b 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -73,6 +73,7 @@ enum radeon_family {
CHIP_PITCAIRN,
CHIP_VERDE,
CHIP_OLAND,
+ CHIP_HAINAN,
CHIP_LAST,
};
commit 040f6b015ef7d9c1bda09f78a8873f6da45d5e95
Author: Dave Airlie <airlied@redhat.com>
Date: Thu May 9 12:55:42 2013 +1000
drm: add qxl drm header file
Now that this driver is merged add the header file.
Signed-off-by: Dave Airlie <airlied@redhat.com>
diff --git a/include/drm/Makefile.am b/include/drm/Makefile.am
index 2923ab4..2bc34d2 100644
--- a/include/drm/Makefile.am
+++ b/include/drm/Makefile.am
@@ -36,8 +36,8 @@ klibdrminclude_HEADERS = \
savage_drm.h \
sis_drm.h \
via_drm.h \
- mach64_drm.h
-
+ mach64_drm.h \
+ qxl_drm.h
if HAVE_VMWGFX
klibdrminclude_HEADERS += vmwgfx_drm.h
diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h
new file mode 100644
index 0000000..5d7de70
--- /dev/null
+++ b/include/drm/qxl_drm.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2013 Red Hat
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef QXL_DRM_H
+#define QXL_DRM_H
+
+#include <stddef.h>
+#include "drm/drm.h"
+
+/* Please note that modifications to all structs defined here are
+ * subject to backwards-compatibility constraints.
+ *
+ * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
+ * compatibility Keep fields aligned to their size
+ */
+
+#define QXL_GEM_DOMAIN_CPU 0
+#define QXL_GEM_DOMAIN_VRAM 1
+#define QXL_GEM_DOMAIN_SURFACE 2
+
+#define DRM_QXL_ALLOC 0x00
+#define DRM_QXL_MAP 0x01
+#define DRM_QXL_EXECBUFFER 0x02
+#define DRM_QXL_UPDATE_AREA 0x03
+#define DRM_QXL_GETPARAM 0x04
+#define DRM_QXL_CLIENTCAP 0x05
+
+#define DRM_QXL_ALLOC_SURF 0x06
+
+struct drm_qxl_alloc {
+ uint32_t size;
+ uint32_t handle; /* 0 is an invalid handle */
+};
+
+struct drm_qxl_map {
+ uint64_t offset; /* use for mmap system call */
+ uint32_t handle;
+ uint32_t pad;
+};
+
+/*
+ * dest is the bo we are writing the relocation into
+ * src is bo we are relocating.
+ * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
+ * src_offset)
+ */
+#define QXL_RELOC_TYPE_BO 1
+#define QXL_RELOC_TYPE_SURF 2
+
+struct drm_qxl_reloc {
+ uint64_t src_offset; /* offset into src_handle or src buffer */
+ uint64_t dst_offset; /* offset in dest handle */
+ uint32_t src_handle; /* dest handle to compute address from */
+ uint32_t dst_handle; /* 0 if to command buffer */
+ uint32_t reloc_type;
+ uint32_t pad;
+};
+
+struct drm_qxl_command {
+ uint64_t command; /* void* */
+ uint64_t relocs; /* struct drm_qxl_reloc* */
+ uint32_t type;
+ uint32_t command_size;
+ uint32_t relocs_num;
+ uint32_t pad;
+};
+
+/* XXX: call it drm_qxl_commands? */
+struct drm_qxl_execbuffer {
+ uint32_t flags; /* for future use */
+ uint32_t commands_num;
+ uint64_t commands; /* struct drm_qxl_command* */
+};
+
+struct drm_qxl_update_area {
+ uint32_t handle;
+ uint32_t top;
+ uint32_t left;
+ uint32_t bottom;
+ uint32_t right;
+ uint32_t pad;
+};
+
+#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
+#define QXL_PARAM_MAX_RELOCS 2
+struct drm_qxl_getparam {
+ uint64_t param;
+ uint64_t value;
+};
+
+/* these are one bit values */
+struct drm_qxl_clientcap {
+ uint32_t index;
+ uint32_t pad;
+};
+
+struct drm_qxl_alloc_surf {
+ uint32_t format;
+ uint32_t width;
+ uint32_t height;
+ int32_t stride;
+ uint32_t handle;
+ uint32_t pad;
+};
+
+#define DRM_IOCTL_QXL_ALLOC \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
+
+#define DRM_IOCTL_QXL_MAP \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
+
+#define DRM_IOCTL_QXL_EXECBUFFER \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
+ struct drm_qxl_execbuffer)
+
+#define DRM_IOCTL_QXL_UPDATE_AREA \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
+ struct drm_qxl_update_area)
+
+#define DRM_IOCTL_QXL_GETPARAM \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
+ struct drm_qxl_getparam)
+
+#define DRM_IOCTL_QXL_CLIENTCAP \
+ DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
+ struct drm_qxl_clientcap)
+
+#define DRM_IOCTL_QXL_ALLOC_SURF \
+ DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
+ struct drm_qxl_alloc_surf)
+
+#endif
commit 011999927f76a7e9ba8f047fae4b4e084da6c2c3
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed Nov 14 12:46:39 2012 +0800
intel: Add support for VEBOX ring (v2)
v2: Fix the test for has_vebox
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7e9e9bd..aa983f3 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -303,6 +303,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_LLC 17
#define I915_PARAM_HAS_ALIASING_PPGTT 18
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
+#define I915_PARAM_HAS_VEBOX 22
typedef struct drm_i915_getparam {
int param;
@@ -649,6 +650,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_VEBOX (4<<0)
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
* Gen6+ only supports relative addressing to dynamic state (default) and
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index d21547e..3c73068 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -125,6 +125,7 @@ typedef struct _drm_intel_bufmgr_gem {
unsigned int has_wait_timeout : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
+ unsigned int has_vebox : 1;
bool fenced_relocs;
FILE *aub_file;
@@ -2213,6 +2214,10 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
if (!bufmgr_gem->has_bsd)
return -EINVAL;
break;
+ case I915_EXEC_VEBOX:
+ if (!bufmgr_gem->has_vebox)
+ return -EINVAL;
+ break;
case I915_EXEC_RENDER:
case I915_EXEC_DEFAULT:
break;
@@ -3126,6 +3131,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
} else
bufmgr_gem->has_llc = *gp.value;
+ gp.param = I915_PARAM_HAS_VEBOX;
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
+
if (bufmgr_gem->gen < 4) {
gp.param = I915_PARAM_NUM_FENCES_AVAIL;
gp.value = &bufmgr_gem->available_fences;
commit b3a3a77823ada2eb37233678b5a49efaec9b75cb
Author: Rob Clark <robclark@freedesktop.org>
Date: Thu Apr 25 16:36:15 2013 -0400
freedreno: add synchronization between mesa and ddx
Super-cheezy way to synchronization between mesa and ddx.. the
SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
GET_BUFINFO gives us a way to retrieve it. We use this to stash
the timestamp of the last ISSUEIBCMDS on the buffer.
To avoid an obscene amount of syscalls, we:
1) Only set the timestamp for buffers w/ an flink name, ie.
only buffers shared across processes. This is enough to
catch the DRI2 buffers.
2) Only set the timestamp for buffers submitted to the 3d ring
and only check the timestamps on buffers submitted to the
2d ring. This should be enough to handle synchronizing of
presentation blit. We could do synchronization in the other
direction too, but that would be problematic if we are using
the 3d ring from DDX, since client side wouldn't know this.
The waiting on timestamp happens before flush, and setting of
timestamp happens after flush. It is transparent to the user
of libdrm_freedreno as all the tracking of buffers happens via
_emit_reloc()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c
index 4f566e1..be386b4 100644
--- a/freedreno/freedreno_bo.c
+++ b/freedreno/freedreno_bo.c
@@ -165,12 +165,17 @@ struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
struct drm_gem_open req = {
.name = name,
};
+ struct fd_bo *bo;
if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) {
return NULL;
}
- return bo_from_handle(dev, req.size, req.handle);
+ bo = bo_from_handle(dev, req.size, req.handle);
+ if (bo)
+ bo->name = name;
+
+ return bo;
}
struct fd_bo * fd_bo_ref(struct fd_bo *bo)
@@ -272,3 +277,64 @@ uint32_t fd_bo_gpuaddr(struct fd_bo *bo, uint32_t offset)
}
return bo->gpuaddr + offset;
}
+
+/*
+ * Super-cheezy way to synchronization between mesa and ddx.. the
+ * SET_ACTIVE ioctl gives us a way to stash a 32b # w/ a GEM bo, and
+ * GET_BUFINFO gives us a way to retrieve it. We use this to stash
+ * the timestamp of the last ISSUEIBCMDS on the buffer.
+ *
+ * To avoid an obscene amount of syscalls, we:
+ * 1) Only set the timestamp for buffers w/ an flink name, ie.
+ * only buffers shared across processes. This is enough to
+ * catch the DRI2 buffers.
+ * 2) Only set the timestamp for buffers submitted to the 3d ring
+ * and only check the timestamps on buffers submitted to the
+ * 2d ring. This should be enough to handle synchronizing of
+ * presentation blit. We could do synchronization in the other
+ * direction too, but that would be problematic if we are using
+ * the 3d ring from DDX, since client side wouldn't know this.
+ *
+ * The waiting on timestamp happens before flush, and setting of
+ * timestamp happens after flush. It is transparent to the user
+ * of libdrm_freedreno as all the tracking of buffers happens via
+ * _emit_reloc()..
+ */
+
+void fb_bo_set_timestamp(struct fd_bo *bo, uint32_t timestamp)
+{
+ if (bo->name) {
+ struct drm_kgsl_gem_active req = {
+ .handle = bo->handle,
+ .active = timestamp,
+ };
+ int ret;
+
+ ret = drmCommandWrite(bo->dev->fd, DRM_KGSL_GEM_SET_ACTIVE,
+ &req, sizeof(req));
+ if (ret) {
+ ERROR_MSG("set active failed: %s", strerror(errno));
+ }
+ }
+}
+
+uint32_t fd_bo_get_timestamp(struct fd_bo *bo)
+{
+ uint32_t timestamp = 0;
+ if (bo->name) {
+ struct drm_kgsl_gem_bufinfo req = {
+ .handle = bo->handle,
+ };
+ int ret;
+
+ ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
+ &req, sizeof(req));
+ if (ret) {
+ ERROR_MSG("get bufinfo failed: %s", strerror(errno));
+ return 0;
+ }
+
+ timestamp = req.active;
+ }
+ return timestamp;
+}
diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c
index 1698c46..9f9f1c6 100644
--- a/freedreno/freedreno_pipe.c
+++ b/freedreno/freedreno_pipe.c
@@ -199,8 +199,26 @@ void fd_pipe_add_submit(struct fd_pipe *pipe, struct fd_bo *bo)
list_addtail(list, &pipe->submit_list);
}
+/* prepare buffers on submit list before flush: */
+void fd_pipe_pre_submit(struct fd_pipe *pipe)
+{
+ struct fd_bo *bo;
+
+ if (pipe->id == FD_PIPE_3D)
+ return;
+
+ if (!pipe->p3d)
+ pipe->p3d = fd_pipe_new(pipe->dev, FD_PIPE_3D);
+
+ LIST_FOR_EACH_ENTRY(bo, &pipe->submit_list, list[pipe->id]) {
+ uint32_t timestamp = fd_bo_get_timestamp(bo);
+ if (timestamp)
+ fd_pipe_wait(pipe->p3d, timestamp);
+ }
+}
+
/* process buffers on submit list after flush: */
-void fd_pipe_process_submit(struct fd_pipe *pipe, uint32_t timestamp)
+void fd_pipe_post_submit(struct fd_pipe *pipe, uint32_t timestamp)
{
struct fd_bo *bo, *tmp;
@@ -209,6 +227,9 @@ void fd_pipe_process_submit(struct fd_pipe *pipe, uint32_t timestamp)
list_del(list);
bo->timestamp[pipe->id] = timestamp;
list_addtail(list, &pipe->pending_list);
+
+ if (pipe->id == FD_PIPE_3D)
+ fb_bo_set_timestamp(bo, timestamp);
}
if (!fd_pipe_timestamp(pipe, ×tamp))
diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h
index aa71b56..0edca1d 100644
--- a/freedreno/freedreno_priv.h
+++ b/freedreno/freedreno_priv.h
@@ -70,10 +70,16 @@ struct fd_pipe {
* not passed yet (so still ref'd in active cmdstream)
*/
struct list_head pending_list;
+
+ /* if we are the 2d pipe, and want to wait on a timestamp
+ * from 3d, we need to also internally open the 3d pipe:
+ */
+ struct fd_pipe *p3d;
};
void fd_pipe_add_submit(struct fd_pipe *pipe, struct fd_bo *bo);
-void fd_pipe_process_submit(struct fd_pipe *pipe, uint32_t timestamp);
+void fd_pipe_pre_submit(struct fd_pipe *pipe);
+void fd_pipe_post_submit(struct fd_pipe *pipe, uint32_t timestamp);
void fd_pipe_process_pending(struct fd_pipe *pipe, uint32_t timestamp);
struct fd_bo {
@@ -95,6 +101,8 @@ struct fd_bo {
* a proper kernel driver
*/
uint32_t fd_bo_gpuaddr(struct fd_bo *bo, uint32_t offset);
+void fb_bo_set_timestamp(struct fd_bo *bo, uint32_t timestamp);
+uint32_t fd_bo_get_timestamp(struct fd_bo *bo);
#define ALIGN(v,a) (((v) + (a) - 1) & ~((a) - 1))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
diff --git a/freedreno/freedreno_ringbuffer.c b/freedreno/freedreno_ringbuffer.c
index f187996..d20a7f5 100644
--- a/freedreno/freedreno_ringbuffer.c
+++ b/freedreno/freedreno_ringbuffer.c
@@ -159,6 +159,8 @@ static int flush_impl(struct fd_ringbuffer *ring, uint32_t *last_start)
};
int ret;
+ fd_pipe_pre_submit(ring->pipe);
+
/* z180_cmdstream_issueibcmds() is made of fail: */
if (ring->pipe->id == FD_PIPE_2D) {
/* fix up size field in last cmd packet */
@@ -180,7 +182,7 @@ static int flush_impl(struct fd_ringbuffer *ring, uint32_t *last_start)
ring->last_timestamp = req.timestamp;
ring->last_start = ring->cur;
- fd_pipe_process_submit(ring->pipe, req.timestamp);
+ fd_pipe_post_submit(ring->pipe, req.timestamp);
return ret;
}
commit ec3c257eb6958da493aee6f010f51a07d7ba4160
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Thu Apr 25 14:13:52 2013 -0400
radeon: add new richland pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 9a62d83..1530394 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -320,6 +320,8 @@ CHIPSET(0x9998, ARUBA_9998, ARUBA)
CHIPSET(0x9999, ARUBA_9999, ARUBA)
CHIPSET(0x999A, ARUBA_999A, ARUBA)
CHIPSET(0x999B, ARUBA_999B, ARUBA)
+CHIPSET(0x999C, ARUBA_999C, ARUBA)
+CHIPSET(0x999D, ARUBA_999D, ARUBA)
CHIPSET(0x99A0, ARUBA_99A0, ARUBA)
CHIPSET(0x99A2, ARUBA_99A2, ARUBA)
CHIPSET(0x99A4, ARUBA_99A4, ARUBA)
commit 439d7d74320a148a2d53aec1ca28eba672ad9353
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Thu Apr 25 14:12:50 2013 -0400
radeon: add new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 4ff8753..9a62d83 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -354,6 +354,7 @@ CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN)
CHIPSET(0x6820, VERDE_6820, VERDE)
CHIPSET(0x6821, VERDE_6821, VERDE)
+CHIPSET(0x6822, VERDE_6822, VERDE)
CHIPSET(0x6823, VERDE_6823, VERDE)
CHIPSET(0x6824, VERDE_6824, VERDE)
CHIPSET(0x6825, VERDE_6825, VERDE)
@@ -361,11 +362,13 @@ CHIPSET(0x6826, VERDE_6826, VERDE)
CHIPSET(0x6827, VERDE_6827, VERDE)
CHIPSET(0x6828, VERDE_6828, VERDE)
CHIPSET(0x6829, VERDE_6829, VERDE)
+CHIPSET(0x682A, VERDE_682A, VERDE)
CHIPSET(0x682B, VERDE_682B, VERDE)
CHIPSET(0x682D, VERDE_682D, VERDE)
CHIPSET(0x682F, VERDE_682F, VERDE)
CHIPSET(0x6830, VERDE_6830, VERDE)
CHIPSET(0x6831, VERDE_6831, VERDE)
+CHIPSET(0x6835, VERDE_6835, VERDE)
CHIPSET(0x6837, VERDE_6837, VERDE)
CHIPSET(0x6838, VERDE_6838, VERDE)
CHIPSET(0x6839, VERDE_6839, VERDE)
commit 12464a70ed502d9f401931156005afd717a9992f
Author: Rob Clark <robclark@freedesktop.org>
Date: Mon Apr 22 14:50:57 2013 -0400
Add exynos_fimg2d_test to .gitignore
Signed-off-by: Rob Clark <robclark@freedesktop.org>
diff --git a/.gitignore b/.gitignore
index 9f8eabb..5447f5c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -85,4 +85,5 @@ tests/modetest/modetest
tests/kmstest/kmstest
tests/vbltest/vbltest
tests/radeon/radeon_ttm
+tests/exynos/exynos_fimg2d_test
man/*.3
commit 86709ba5373730a438602459e104bf0a9a49559d
Author: Rob Clark <robclark@freedesktop.org>
Date: Mon Apr 22 14:49:28 2013 -0400
freedreno: add gpu-id property
Gallium driver will need to query this to figure out whether to load the
a2xx or a3xx driver.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h
index 775d699..ba99afd 100644
--- a/freedreno/freedreno_drmif.h
+++ b/freedreno/freedreno_drmif.h
@@ -48,6 +48,7 @@ enum fd_pipe_id {
enum fd_param_id {
FD_DEVICE_ID,
FD_GMEM_SIZE,
+ FD_GPU_ID,
};
/* bo flags: */
diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c
index 49949ec..1698c46 100644
--- a/freedreno/freedreno_pipe.c
+++ b/freedreno/freedreno_pipe.c
@@ -142,6 +142,9 @@ int fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param,
case FD_DEVICE_ID:
*value = pipe->devinfo.device_id;
return 0;
+ case FD_GPU_ID:
+ *value = pipe->devinfo.gpu_id;
+ return 0;
case FD_GMEM_SIZE:
*value = pipe->devinfo.gmem_sizebytes;
return 0;
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