libdrm: Changes to 'debian-experimental'
.gitignore | 1
ChangeLog | 209 +++++++++++
Makefile.am | 6
configure.ac | 28 +
debian/changelog | 2
exynos/Makefile.am | 2
exynos/exynos_drm.h | 52 ++
exynos/exynos_fimg2d.c | 630 ++++++++++++++++++++++++++++++++++
exynos/fimg2d.h | 325 +++++++++++++++++
exynos/fimg2d_reg.h | 114 ++++++
freedreno/Makefile.am | 19 +
freedreno/README | 16
freedreno/freedreno_bo.c | 274 ++++++++++++++
freedreno/freedreno_device.c | 45 ++
freedreno/freedreno_drmif.h | 99 +++++
freedreno/freedreno_pipe.c | 227 ++++++++++++
freedreno/freedreno_priv.h | 117 ++++++
freedreno/freedreno_ringbuffer.c | 249 +++++++++++++
freedreno/freedreno_ringbuffer.h | 87 ++++
freedreno/kgsl_drm.h | 192 ++++++++++
freedreno/libdrm_freedreno.pc.in | 11
freedreno/list.h | 137 +++++++
freedreno/msm_kgsl.h | 519 ++++++++++++++++++++++++++++
intel/intel_bufmgr_gem.c | 2
intel/intel_chipset.h | 378 +++++++++++---------
intel/intel_decode.c | 2
nouveau/nouveau.c | 18
nouveau/private.h | 1
nouveau/pushbuf.c | 8
radeon/r600_pci_ids.h | 11
radeon/radeon_surface.c | 8
tests/Makefile.am | 4
tests/exynos/Makefile.am | 19 +
tests/exynos/exynos_fimg2d_test.c | 695 ++++++++++++++++++++++++++++++++++++++
tests/kmstest/Makefile.am | 5
tests/modeprint/Makefile.am | 5
tests/modetest/Makefile.am | 5
tests/vbltest/Makefile.am | 6
38 files changed, 4339 insertions(+), 189 deletions(-)
New commits:
commit 2f54887cd7a0fcb6f8f913c9e828e842960d4e5d
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Wed Mar 27 11:08:01 2013 +0100
bump changelogs
diff --git a/ChangeLog b/ChangeLog
index 275a4de..4f07fdb 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,212 @@
+commit c005f043dcb4df5ed8a36b9f4b70fcf9e92d52a5
+Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
+Date: Wed Mar 27 10:42:20 2013 +0100
+
+ configure.ac: bump version to 2.4.43 for release
+
+ Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
+
+commit 93d12593e5f1b251a09b112d7beaf5cfca026896
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Mon Feb 18 20:50:01 2013 +0200
+
+ intel_chipset: Fix up VLV confusion
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 6e55fd7dee48dabcd46939df1aa8729eba426298
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date: Mon Feb 18 20:22:21 2013 +0200
+
+ intel_chipset: Use parens around macro arguments
+
+ Protect the macro argument evaluations with parens.
+
+ This is already touching most lines, so while at it, fix up all white
+ space to uniform style throughout the file.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit f92d7969bf6ba636d193423cf2388956badde3ff
+Author: Marcin Slusarz <marcin.slusarz@gmail.com>
+Date: Sun Mar 3 22:34:38 2013 +0100
+
+ nouveau: add a way to override single pushbuffer memory limits
+
+ Currently single pushbuffer can take up to 80% of VRAM and 80% of GART.
+ As this value seems to be arbitrary (and user may need to set it differently)
+ this patch adds support for 2 environment variables:
+ NOUVEAU_LIBDRM_VRAM_LIMIT_PERCENT (default 80)
+ NOUVEAU_LIBDRM_GART_LIMIT_PERCENT (default 80)
+ which will let users override pushbuffer VRAM/GART limits.
+
+ Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
+
+commit 284421a56921337aaabcec7ad2790034249c7b31
+Author: Marcin Slusarz <marcin.slusarz@gmail.com>
+Date: Sun Mar 3 22:13:38 2013 +0100
+
+ nouveau: return error from pushbuf_validate
+
+ Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
+
+commit 9b0c7f23a261d9bfa857a7e0efd2c5f97d404485
+Author: Benjamin Gaignard <benjamin.gaignard@st.com>
+Date: Tue Mar 26 11:11:41 2013 +0100
+
+ tests: allow tests programs to be installed (cumulative patch)
+
+ fix error in previous patch
+
+ Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.com>
+ Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
+
+commit 62d8866021f04bc8afc8e63d366c71d11c817bc9
+Author: Benjamin Gaignard <benjamin.gaignard@stericsson.com>
+Date: Wed Jan 30 14:34:00 2013 +0100
+
+ tests: allow tests programs to be installed
+
+ Install test programs is useful in cross compilation case. By default
+ the behavior is the same and test programs aren't installed in $bindir.
+ If --enable-install-test-programs is set then test programs are
+ installed in $bindir.
+
+ Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
+ Signed-off-by: Rob Clark <robdclark@gmail.com>
+
+commit 36a2daad2416ad55a859c483b0d7ed93a5eff6e0
+Author: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri Mar 8 14:12:32 2013 -0500
+
+ radeon: add pci ids for Richland APUs
+
+ Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+
+commit bbf6e3dea3c79ea8e0c3e1dd8f80014201e003fc
+Author: Inki Dae <inki.dae@samsung.com>
+Date: Mon Feb 18 21:51:00 2013 +0900
+
+ libdrm/exynos: add test application for 2d gpu.
+
+ This patch adds library and test application for g2d gpu(fimg2d).
+
+ The fimg2d hardware is a 2D graphics accelerator(G2D) that
+ supports Bit Block Transfer(BitBLT).
+
+ The library includes the following primitive drawing operations:
+ .solid fill - This operation fills the given buffer with
+ the given color data.
+ .copy - This operation copies contents in source buffer to
+ destination buffer.
+ .copy_with_scale - This operation copies contents in source buffer
+ to destination buffer scaling up or down properly.
+ .blend - This operation blends contents in source buffer with
+ the ones in destination buffer.
+
+ And the above operations uses gem handle or user space address
+ allocated by malloc() as source or destination buffer.
+
+ And the test application includes just simple primitive drawing
+ tests with the above library.
+ And the guide to test is as the following,
+ "#exynos_fimg2d_test -s connector_id@crtc_id:mode"
+
+ With this above simple command, four primitive drawing operations
+ would be called step by step and also rendered on the output device
+ to the given connector and crtc id.
+
+ Signed-off-by: Inki Dae <inki.dae@samsung.com>
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+ Signed-off-by: Rob Clark <robdclark@gmail.com>
+
+commit ade2ad2d66ac341a12eca37bcb30d40199eb4e02
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Thu Mar 7 09:49:53 2013 -0500
+
+ radeonsi: make sure tile_split field are not garbage
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 41fc2cc8a98a8d02ea7d3635d3103f7dd371de10
+Author: Rob Clark <robclark@freedesktop.org>
+Date: Sun Oct 7 18:57:31 2012 -0500
+
+ freedreno: add freedreno DRM
+
+ The libdrm_freedreno helper layer for use by xf86-video-freedreno,
+ fdre (freedreno r/e library and tests for driving gpu), and eventual
+ gallium driver for the Adreno GPU. This uses the msm gpu driver
+ from QCOM's android kernel tree.
+
+ Note that current msm kernel driver is a bit strange. It provides a
+ DRM interface for GEM, which is basically sufficient to have DRI2
+ working. But it does not provide KMS. And interface to 2d and 3d
+ cores is via different other devices (/dev/kgsl-*). This is not
+ quite how I'd write a DRM driver, but at this stage it is useful for
+ xf86-video-freedreno and fdre (and eventual gallium driver) to be
+ able to work on existing kernel driver from QCOM, to allow to
+ capture cmdstream dumps from the binary blob drivers without having
+ to reboot. So libdrm_freedreno attempts to hide most of the crazy.
+ The intention is that when there is a proper kernel driver, it will
+ be mostly just changes in libdrm_freedreno to adapt the gallium
+ driver and xf86-video-freedreno (ignoring the fbdev->KMS changes).
+
+ So don't look at freedreno as an example of how to write a libdrm
+ module or a DRM driver.. it is just an attempt to paper over a non-
+ standard kernel driver architecture.
+
+ v1: original
+ v2: hold ref's to pending bo's (because qcom's kernel driver doesn't),
+ various bug fixes, add ringbuffer markers so we can emit IB's to
+ portion of ringbuffer (so that gallium driver can use a single
+ ringbuffer for both tile cmds and draw cmds.
+
+ Signed-off-by: Rob Clark <robclark@freedesktop.org>
+
+commit 36d18211b196cad4761ac70c4fd08aba323f5b0d
+Author: Ben Widawsky <ben@bwidawsk.net>
+Date: Mon Dec 3 17:43:29 2012 -0800
+
+ intel_chipset: Merge intel-gpu-tools chipsets
+
+ Intel GPU Tools is newer and arguably better. This change doesn't
+ completely merge the files because it's a bit simpler if we move the
+ I9XX macro over to Intel GPU Tools, and don't move over a few macros
+ from IGT that libdrm doesn't care about.
+
+ It has been discussed, and would seem even easier if Intel GPU Tools
+ simply used the libdrm header files. Whether or not we move to that,
+ this should help that effort.
+
+ Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
+ Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
+
+commit 20c5607b57da113ca1a29caaa5a52eaf83808dff
+Author: Chris Forbes <chrisf@ijw.co.nz>
+Date: Mon Jan 28 08:01:18 2013 +0000
+
+ intel: fix length mask for Gen5/Gen6 3DSTATE_CLEAR_PARAMS
+
+ On Gen6, bit 15 is now `Depth Clear Value Valid`. This was being treated
+ as part of the length, and failing the rest of the batchbuffer decode.
+
+ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+ Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
+
+commit 3b5cc135424f3b8d6b79fb409fe9b4ffc4855333
+Author: Kenneth Graunke <kenneth@whitecape.org>
+Date: Sat Jan 12 16:54:59 2013 -0800
+
+ intel/aub: Actually run BLT batches on the blit ring.
+
+ We didn't set the ring flag for BLT batches, so they got run on the
+ render ring. Shenanigans ensued, especially when we sent commands that
+ were only valid on the BLT ring.
+
+ Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
+ Reviewed-by: Eric Anholt <eric@anholt.net>
+
commit 183b5f20b59c83f57967b41d1e3a90c073e8df76
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Tue Feb 5 14:08:41 2013 +0100
diff --git a/debian/changelog b/debian/changelog
index 0050d34..8f03c70 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.42-1) UNRELEASED; urgency=low
+libdrm (2.4.43-1) UNRELEASED; urgency=low
[ Julien Cristau ]
* Bump libdrm2 shlibs to 2.4.38.
commit c005f043dcb4df5ed8a36b9f4b70fcf9e92d52a5
Author: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Date: Wed Mar 27 10:42:20 2013 +0100
configure.ac: bump version to 2.4.43 for release
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
diff --git a/configure.ac b/configure.ac
index 59e8a34..2786c87 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.42],
+ [2.4.43],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 93d12593e5f1b251a09b112d7beaf5cfca026896
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Mon Feb 18 20:50:01 2013 +0200
intel_chipset: Fix up VLV confusion
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 8af5acf..2760dc8 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -192,15 +192,15 @@
(devid) == PCI_CHIP_SANDYBRIDGE_S)
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid))
+ IS_HASWELL(devid) || \
+ IS_VALLEYVIEW(devid))
#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
(devid) == PCI_CHIP_IVYBRIDGE_S || \
- (devid) == PCI_CHIP_IVYBRIDGE_S_GT2 || \
- (devid) == PCI_CHIP_VALLEYVIEW_PO)
+ (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
(devid) == PCI_CHIP_VALLEYVIEW_1 || \
commit 6e55fd7dee48dabcd46939df1aa8729eba426298
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Mon Feb 18 20:22:21 2013 +0200
intel_chipset: Use parens around macro arguments
Protect the macro argument evaluations with parens.
This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 3123a90..8af5acf 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -52,26 +52,26 @@
#define PCI_CHIP_IGD_GM 0xA011
#define PCI_CHIP_IGD_G 0xA001
-#define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
+#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
+#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
+#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I946_GZ 0x2972
-#define PCI_CHIP_I965_GM 0x2A02
-#define PCI_CHIP_I965_GME 0x2A12
+#define PCI_CHIP_I965_GM 0x2A02
+#define PCI_CHIP_I965_GME 0x2A12
-#define PCI_CHIP_GM45_GM 0x2A42
+#define PCI_CHIP_GM45_GM 0x2A42
-#define PCI_CHIP_IGD_E_G 0x2E02
-#define PCI_CHIP_Q45_G 0x2E12
-#define PCI_CHIP_G45_G 0x2E22
-#define PCI_CHIP_G41_G 0x2E32
+#define PCI_CHIP_IGD_E_G 0x2E02
+#define PCI_CHIP_Q45_G 0x2E12
+#define PCI_CHIP_G45_G 0x2E22
+#define PCI_CHIP_G41_G 0x2E32
-#define PCI_CHIP_ILD_G 0x0042
-#define PCI_CHIP_ILM_G 0x0046
+#define PCI_CHIP_ILD_G 0x0042
+#define PCI_CHIP_ILM_G 0x0046
#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
@@ -88,169 +88,169 @@
#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
-#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
-#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
-#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
-#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
-#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
-#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
-#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
-#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
-#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
-#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
-#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
-#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
-#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
-#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
-#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
-#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
-#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
-#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2 0x0412
+#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2 0x0416
+#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
+#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
#define PCI_CHIP_VALLEYVIEW_2 0x0f32
#define PCI_CHIP_VALLEYVIEW_3 0x0f33
-#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
- devid == PCI_CHIP_I915_GM || \
- devid == PCI_CHIP_I945_GM || \
- devid == PCI_CHIP_I945_GME || \
- devid == PCI_CHIP_I965_GM || \
- devid == PCI_CHIP_I965_GME || \
- devid == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
- devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- devid == PCI_CHIP_IVYBRIDGE_M_GT2)
-
-#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
- devid == PCI_CHIP_Q45_G || \
- devid == PCI_CHIP_G45_G || \
- devid == PCI_CHIP_G41_G)
-#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
+#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
+ (devid) == PCI_CHIP_I915_GM || \
+ (devid) == PCI_CHIP_I945_GM || \
+ (devid) == PCI_CHIP_I945_GME || \
+ (devid) == PCI_CHIP_I965_GM || \
+ (devid) == PCI_CHIP_I965_GME || \
+ (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
+
+#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
+ (devid) == PCI_CHIP_Q45_G || \
+ (devid) == PCI_CHIP_G45_G || \
+ (devid) == PCI_CHIP_G41_G)
+#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
-#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
-#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
+#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
+#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
-#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
- devid == PCI_CHIP_E7221_G || \
- devid == PCI_CHIP_I915_GM)
+#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
+ (devid) == PCI_CHIP_E7221_G || \
+ (devid) == PCI_CHIP_I915_GM)
-#define IS_945GM(devid) (devid == PCI_CHIP_I945_GM || \
- devid == PCI_CHIP_I945_GME)
+#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
+ (devid) == PCI_CHIP_I945_GME)
-#define IS_945(devid) (devid == PCI_CHIP_I945_G || \
- devid == PCI_CHIP_I945_GM || \
- devid == PCI_CHIP_I945_GME || \
+#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
+ (devid) == PCI_CHIP_I945_GM || \
+ (devid) == PCI_CHIP_I945_GME || \
IS_G33(devid))
-#define IS_G33(devid) (devid == PCI_CHIP_G33_G || \
- devid == PCI_CHIP_Q33_G || \
- devid == PCI_CHIP_Q35_G || IS_IGD(devid))
+#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
+ (devid) == PCI_CHIP_Q33_G || \
+ (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-#define IS_GEN2(devid) (devid == PCI_CHIP_I830_M || \
- devid == PCI_CHIP_845_G || \
- devid == PCI_CHIP_I855_GM || \
- devid == PCI_CHIP_I865_G)
+#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
+ (devid) == PCI_CHIP_845_G || \
+ (devid) == PCI_CHIP_I855_GM || \
+ (devid) == PCI_CHIP_I865_G)
#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
-#define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \
- devid == PCI_CHIP_I965_Q || \
- devid == PCI_CHIP_I965_G_1 || \
- devid == PCI_CHIP_I965_GM || \
- devid == PCI_CHIP_I965_GME || \
- devid == PCI_CHIP_I946_GZ || \
+#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
+ (devid) == PCI_CHIP_I965_Q || \
+ (devid) == PCI_CHIP_I965_G_1 || \
+ (devid) == PCI_CHIP_I965_GM || \
+ (devid) == PCI_CHIP_I965_GME || \
+ (devid) == PCI_CHIP_I946_GZ || \
IS_G4X(devid))
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
-#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
- devid == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid))
-
-#define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
- dev == PCI_CHIP_IVYBRIDGE_GT2 || \
- dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
- dev == PCI_CHIP_IVYBRIDGE_S || \
- dev == PCI_CHIP_IVYBRIDGE_S_GT2 || \
- dev == PCI_CHIP_VALLEYVIEW_PO)
-
-#define IS_VALLEYVIEW(dev) (((dev) == PCI_CHIP_VALLEYVIEW_PO) || \
- ((dev) == PCI_CHIP_VALLEYVIEW_1) || \
- ((dev) == PCI_CHIP_VALLEYVIEW_2) || \
- ((dev) == PCI_CHIP_VALLEYVIEW_3))
-
-#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
- devid == PCI_CHIP_HASWELL_M_GT1 || \
- devid == PCI_CHIP_HASWELL_S_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT1)
-#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
- devid == PCI_CHIP_HASWELL_M_GT2 || \
- devid == PCI_CHIP_HASWELL_S_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
- devid == PCI_CHIP_HASWELL_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
-
-#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid))
-
-#define IS_9XX(dev) (IS_GEN3(dev) || \
- IS_GEN4(dev) || \
- IS_GEN5(dev) || \
- IS_GEN6(dev) || \
- IS_GEN7(dev))
+#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
+ (devid) == PCI_CHIP_SANDYBRIDGE_S)
+
+#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
+ IS_HASWELL(devid))
+
+#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
+ (devid) == PCI_CHIP_IVYBRIDGE_S || \
+ (devid) == PCI_CHIP_IVYBRIDGE_S_GT2 || \
+ (devid) == PCI_CHIP_VALLEYVIEW_PO)
+
+#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
+ (devid) == PCI_CHIP_VALLEYVIEW_1 || \
+ (devid) == PCI_CHIP_VALLEYVIEW_2 || \
+ (devid) == PCI_CHIP_VALLEYVIEW_3)
+
+#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
+#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+
+#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
+ IS_HSW_GT2(devid))
+
+#define IS_9XX(dev) (IS_GEN3(dev) || \
+ IS_GEN4(dev) || \
+ IS_GEN5(dev) || \
+ IS_GEN6(dev) || \
+ IS_GEN7(dev))
#endif /* _INTEL_CHIPSET_H */
commit f92d7969bf6ba636d193423cf2388956badde3ff
Author: Marcin Slusarz <marcin.slusarz@gmail.com>
Date: Sun Mar 3 22:34:38 2013 +0100
nouveau: add a way to override single pushbuffer memory limits
Currently single pushbuffer can take up to 80% of VRAM and 80% of GART.
As this value seems to be arbitrary (and user may need to set it differently)
this patch adds support for 2 environment variables:
NOUVEAU_LIBDRM_VRAM_LIMIT_PERCENT (default 80)
NOUVEAU_LIBDRM_GART_LIMIT_PERCENT (default 80)
which will let users override pushbuffer VRAM/GART limits.
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
diff --git a/nouveau/nouveau.c b/nouveau/nouveau.c
index 9b32e31..ee7893b 100644
--- a/nouveau/nouveau.c
+++ b/nouveau/nouveau.c
@@ -77,6 +77,7 @@ nouveau_device_wrap(int fd, int close, struct nouveau_device **pdev)
uint64_t chipset, vram, gart, bousage;
drmVersionPtr ver;
int ret;
+ char *tmp;
#ifdef DEBUG
debug_init(getenv("NOUVEAU_LIBDRM_DEBUG"));
@@ -114,14 +115,27 @@ nouveau_device_wrap(int fd, int close, struct nouveau_device **pdev)
nvdev->have_bo_usage = (bousage != 0);
nvdev->close = close;
+
+ tmp = getenv("NOUVEAU_LIBDRM_VRAM_LIMIT_PERCENT");
+ if (tmp)
+ nvdev->vram_limit_percent = atoi(tmp);
+ else
+ nvdev->vram_limit_percent = 80;
+ tmp = getenv("NOUVEAU_LIBDRM_GART_LIMIT_PERCENT");
+ if (tmp)
+ nvdev->gart_limit_percent = atoi(tmp);
+ else
+ nvdev->gart_limit_percent = 80;
DRMINITLISTHEAD(&nvdev->bo_list);
nvdev->base.object.oclass = NOUVEAU_DEVICE_CLASS;
nvdev->base.lib_version = 0x01000000;
nvdev->base.chipset = chipset;
nvdev->base.vram_size = vram;
nvdev->base.gart_size = gart;
- nvdev->base.vram_limit = (nvdev->base.vram_size * 80) / 100;
- nvdev->base.gart_limit = (nvdev->base.gart_size * 80) / 100;
+ nvdev->base.vram_limit =
+ (nvdev->base.vram_size * nvdev->vram_limit_percent) / 100;
+ nvdev->base.gart_limit =
+ (nvdev->base.gart_size * nvdev->gart_limit_percent) / 100;
*pdev = &nvdev->base;
return 0;
diff --git a/nouveau/private.h b/nouveau/private.h
index 8a5cb26..60714b8 100644
--- a/nouveau/private.h
+++ b/nouveau/private.h
@@ -99,6 +99,7 @@ struct nouveau_device_priv {
uint32_t *client;
int nr_client;
bool have_bo_usage;
+ int gart_limit_percent, vram_limit_percent;
};
static inline struct nouveau_device_priv *
diff --git a/nouveau/pushbuf.c b/nouveau/pushbuf.c
index e720a08..0fd0c47 100644
--- a/nouveau/pushbuf.c
+++ b/nouveau/pushbuf.c
@@ -347,8 +347,10 @@ pushbuf_submit(struct nouveau_pushbuf *push, struct nouveau_object *chan)
&req, sizeof(req));
nvpb->suffix0 = req.suffix0;
nvpb->suffix1 = req.suffix1;
- dev->vram_limit = (req.vram_available * 80) / 100;
- dev->gart_limit = (req.gart_available * 80) / 100;
+ dev->vram_limit = (req.vram_available *
+ nouveau_device(dev)->vram_limit_percent) / 100;
+ dev->gart_limit = (req.gart_available *
+ nouveau_device(dev)->gart_limit_percent) / 100;
#else
if (dbg_on(31))
ret = -EINVAL;
commit 284421a56921337aaabcec7ad2790034249c7b31
Author: Marcin Slusarz <marcin.slusarz@gmail.com>
Date: Sun Mar 3 22:13:38 2013 +0100
nouveau: return error from pushbuf_validate
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
diff --git a/nouveau/pushbuf.c b/nouveau/pushbuf.c
index ff8e125..e720a08 100644
--- a/nouveau/pushbuf.c
+++ b/nouveau/pushbuf.c
@@ -524,7 +524,7 @@ pushbuf_validate(struct nouveau_pushbuf *push, bool retry)
}
}
- return 0;
+ return ret;
}
int
commit 9b0c7f23a261d9bfa857a7e0efd2c5f97d404485
Author: Benjamin Gaignard <benjamin.gaignard@st.com>
Date: Tue Mar 26 11:11:41 2013 +0100
tests: allow tests programs to be installed (cumulative patch)
fix error in previous patch
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
diff --git a/tests/vbltest/Makefile.am b/tests/vbltest/Makefile.am
index f99b6a2..34a35e7 100644
--- a/tests/vbltest/Makefile.am
+++ b/tests/vbltest/Makefile.am
@@ -2,7 +2,7 @@ AM_CFLAGS = \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)
if HAVE_INSTALL_TESTS
-noinst_PROGRAMS = \
+bin_PROGRAMS = \
vbltest
else
noinst_PROGRAMS = \
commit 62d8866021f04bc8afc8e63d366c71d11c817bc9
Author: Benjamin Gaignard <benjamin.gaignard@stericsson.com>
Date: Wed Jan 30 14:34:00 2013 +0100
tests: allow tests programs to be installed
Install test programs is useful in cross compilation case. By default
the behavior is the same and test programs aren't installed in $bindir.
If --enable-install-test-programs is set then test programs are
installed in $bindir.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
diff --git a/configure.ac b/configure.ac
index ee4ac72..59e8a34 100644
--- a/configure.ac
+++ b/configure.ac
@@ -98,6 +98,11 @@ AC_ARG_ENABLE(freedreno-experimental-api,
[Enable support for freedreno's experimental API (default: disabled)]),
[FREEDRENO=$enableval], [FREEDRENO=no])
+AC_ARG_ENABLE(install-test-programs,
+ AS_HELP_STRING([--enable-install-test-programs],
+ [Install test programs (default: no)]),
+ [INSTALL_TESTS=$enableval], [INSTALL_TESTS=no])
+
dnl ===========================================================================
dnl check compiler flags
AC_DEFUN([LIBDRM_CC_TRY_FLAG], [
@@ -211,6 +216,11 @@ if test "x$FREEDRENO" = xyes; then
AC_DEFINE(HAVE_FREEDRENO, 1, [Have freedreno support])
fi
+AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes])
+if test "x$INSTALL_TESTS" = xyes; then
+ AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs])
+fi
+
AC_ARG_ENABLE([cairo-tests],
[AS_HELP_STRING([--enable-cairo-tests],
[Enable support for Cairo rendering in tests (default: auto)])],
diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am
index ae562a1..7903a26 100644
--- a/tests/kmstest/Makefile.am
+++ b/tests/kmstest/Makefile.am
@@ -3,8 +3,13 @@ AM_CFLAGS = \
-I$(top_srcdir)/libkms/ \
-I$(top_srcdir)
+if HAVE_INSTALL_TESTS
+bin_PROGRAMS = \
+ kmstest
+else
noinst_PROGRAMS = \
kmstest
+endif
kmstest_SOURCES = \
main.c
diff --git a/tests/modeprint/Makefile.am b/tests/modeprint/Makefile.am
index c4862ac..6420ef3 100644
--- a/tests/modeprint/Makefile.am
+++ b/tests/modeprint/Makefile.am
@@ -2,8 +2,13 @@ AM_CFLAGS = \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)
+if HAVE_INSTALL_TESTS
+bin_PROGRAMS = \
+ modeprint
+else
noinst_PROGRAMS = \
modeprint
+endif
modeprint_SOURCES = \
modeprint.c
diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am
index 065ae13..410c632 100644
--- a/tests/modetest/Makefile.am
+++ b/tests/modetest/Makefile.am
@@ -3,8 +3,13 @@ AM_CFLAGS = \
-I$(top_srcdir)/libkms/ \
-I$(top_srcdir)
+if HAVE_INSTALL_TESTS
+bin_PROGRAMS = \
+ modetest
+else
noinst_PROGRAMS = \
modetest
+endif
modetest_SOURCES = \
buffers.c modetest.c buffers.h
diff --git a/tests/vbltest/Makefile.am b/tests/vbltest/Makefile.am
index 77f9037..f99b6a2 100644
--- a/tests/vbltest/Makefile.am
+++ b/tests/vbltest/Makefile.am
@@ -1,9 +1,13 @@
AM_CFLAGS = \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)
-
+if HAVE_INSTALL_TESTS
+noinst_PROGRAMS = \
+ vbltest
+else
noinst_PROGRAMS = \
vbltest
+endif
vbltest_SOURCES = \
vbltest.c
commit 36a2daad2416ad55a859c483b0d7ed93a5eff6e0
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Mar 8 14:12:32 2013 -0500
radeon: add pci ids for Richland APUs
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index ccc3ea5..4ff8753 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -298,6 +298,10 @@ CHIPSET(0x9907, ARUBA_9907, ARUBA)
CHIPSET(0x9908, ARUBA_9908, ARUBA)
CHIPSET(0x9909, ARUBA_9909, ARUBA)
CHIPSET(0x990A, ARUBA_990A, ARUBA)
+CHIPSET(0x990B, ARUBA_990B, ARUBA)
+CHIPSET(0x990C, ARUBA_990C, ARUBA)
+CHIPSET(0x990D, ARUBA_990D, ARUBA)
+CHIPSET(0x990E, ARUBA_990E, ARUBA)
CHIPSET(0x990F, ARUBA_990F, ARUBA)
CHIPSET(0x9910, ARUBA_9910, ARUBA)
CHIPSET(0x9913, ARUBA_9913, ARUBA)
@@ -309,6 +313,13 @@ CHIPSET(0x9991, ARUBA_9991, ARUBA)
CHIPSET(0x9992, ARUBA_9992, ARUBA)
CHIPSET(0x9993, ARUBA_9993, ARUBA)
CHIPSET(0x9994, ARUBA_9994, ARUBA)
+CHIPSET(0x9995, ARUBA_9995, ARUBA)
+CHIPSET(0x9996, ARUBA_9996, ARUBA)
+CHIPSET(0x9997, ARUBA_9997, ARUBA)
+CHIPSET(0x9998, ARUBA_9998, ARUBA)
+CHIPSET(0x9999, ARUBA_9999, ARUBA)
+CHIPSET(0x999A, ARUBA_999A, ARUBA)
+CHIPSET(0x999B, ARUBA_999B, ARUBA)
CHIPSET(0x99A0, ARUBA_99A0, ARUBA)
CHIPSET(0x99A2, ARUBA_99A2, ARUBA)
CHIPSET(0x99A4, ARUBA_99A4, ARUBA)
commit bbf6e3dea3c79ea8e0c3e1dd8f80014201e003fc
Author: Inki Dae <inki.dae@samsung.com>
Date: Mon Feb 18 21:51:00 2013 +0900
libdrm/exynos: add test application for 2d gpu.
This patch adds library and test application for g2d gpu(fimg2d).
The fimg2d hardware is a 2D graphics accelerator(G2D) that
supports Bit Block Transfer(BitBLT).
The library includes the following primitive drawing operations:
.solid fill - This operation fills the given buffer with
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