mesa: Changes to 'debian-experimental'
Makefile.am | 2
bin/.cherry-ignore | 1
bin/get-pick-list.sh | 2
common.py | 2
configure.ac | 5
debian/changelog | 44 ++
debian/libgl1-mesa-dri.install.in | 1
docs/index.html | 17 +
docs/relnotes-9.1.1.html | 232 ++++++++++++++
docs/relnotes-9.1.html | 6
docs/relnotes.html | 1
include/pci_ids/i965_pci_ids.h | 18 -
include/pci_ids/r600_pci_ids.h | 11
scons/gallium.py | 3
scons/llvm.py | 14
src/egl/drivers/dri2/egl_dri2.c | 9
src/gallium/auxiliary/draw/draw_pipe_clip.c | 11
src/gallium/auxiliary/draw/draw_pipe_offset.c | 40 ++
src/gallium/auxiliary/util/u_range.h | 89 +++++
src/gallium/drivers/llvmpipe/lp_state_rasterizer.c | 6
src/gallium/drivers/llvmpipe/lp_texture.c | 4
src/gallium/drivers/r600/evergreen_hw_context.c | 3
src/gallium/drivers/r600/evergreen_state.c | 43 ++
src/gallium/drivers/r600/r600.h | 12
src/gallium/drivers/r600/r600_asm.c | 11
src/gallium/drivers/r600/r600_buffer.c | 19 +
src/gallium/drivers/r600/r600_hw_context.c | 14
src/gallium/drivers/r600/r600_hw_context_priv.h | 2
src/gallium/drivers/r600/r600_llvm.c | 6
src/gallium/drivers/r600/r600_pipe.c | 16
src/gallium/drivers/r600/r600_pipe.h | 4
src/gallium/drivers/r600/r600_state.c | 6
src/gallium/drivers/r600/r600_state_common.c | 14
src/gallium/drivers/r600/r600d.h | 1
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 17 +
src/gallium/drivers/radeonsi/radeonsi_shader.c | 11
src/gallium/drivers/radeonsi/radeonsi_shader.h | 1
src/gallium/drivers/radeonsi/si_state.c | 5
src/gallium/drivers/radeonsi/si_state_draw.c | 20 -
src/gallium/state_trackers/glx/xlib/xm_api.c | 3
src/gallium/targets/dri-vmwgfx/Makefile.am | 6
src/gallium/targets/vdpau-softpipe/Makefile.am | 2
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 8
src/gbm/backends/dri/gbm_dri.c | 2
src/mesa/drivers/common/meta.c | 17 -
src/mesa/drivers/dri/i965/Makefile.am | 1
src/mesa/drivers/dri/i965/brw_fs.cpp | 290 +++++++++++++++++-
src/mesa/drivers/dri/i965/brw_fs.h | 5
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 3
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 3
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 42 --
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 28 -
src/mesa/drivers/dri/i965/brw_vs_constval.c | 19 +
src/mesa/drivers/dri/intel/intel_chipset.h | 18 -
src/mesa/drivers/dri/nouveau/nouveau_driver.c | 3
src/mesa/main/attrib.c | 12
src/mesa/main/context.c | 1
src/mesa/main/glformats.c | 2
src/mesa/main/points.c | 3
src/mesa/main/teximage.c | 8
src/mesa/main/texparam.c | 6
src/mesa/main/version.h | 4
src/mesa/state_tracker/st_atom_rasterizer.c | 10
src/mesa/state_tracker/st_cb_bitmap.c | 13
src/mesa/state_tracker/st_draw.c | 2
src/mesa/state_tracker/st_program.c | 2
66 files changed, 1046 insertions(+), 190 deletions(-)
New commits:
commit e3293777d2fca0474b9be880a36ccf024460c204
Author: Sven Joachim <svenjoac@gmx.de>
Date: Wed Mar 20 17:42:58 2013 +0100
Remove duplicate entry from debian/changelog
The switch to xz compression has also been done in version 8.0.4-2.
diff --git a/debian/changelog b/debian/changelog
index e26458e..8f9bf32 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -3,9 +3,6 @@ mesa (9.1.1-1) UNRELEASED; urgency=low
* New upstream release.
- Set close on exec flag when opening dri devices (Closes: #651370).
- [ Julien Cristau ]
- * Use xz for all binary packages not just *-dbg.
-
[ Timo Aaltonen ]
* Refresh patches
- disable 05_kfreebsd-egl-x11.diff for now.
commit 3cc52c9693c98ea39b63e48653302ed3ff45e4d8
Author: Sven Joachim <svenjoac@gmx.de>
Date: Wed Mar 20 17:26:36 2013 +0100
New upstream release
diff --git a/debian/changelog b/debian/changelog
index 7cbcba7..440bbbd 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (9.1-1) UNRELEASED; urgency=low
+mesa (9.1.1-1) UNRELEASED; urgency=low
* New upstream release.
- Set close on exec flag when opening dri devices (Closes: #651370).
commit 1e5e805fd089f644f254b2b16d49ba3e27c1a53c
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Tue Mar 19 17:14:38 2013 -0700
mesa: Bump version to 9.1.1
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/Makefile.am b/Makefile.am
index a1f7bce..c7e2f6c 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -36,7 +36,7 @@ check-local:
# Rules for making release tarballs
-PACKAGE_VERSION=9.1
+PACKAGE_VERSION=9.1.1
PACKAGE_DIR = Mesa-$(PACKAGE_VERSION)
PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)
diff --git a/configure.ac b/configure.ac
index d75cf65..4a98996 100644
--- a/configure.ac
+++ b/configure.ac
@@ -6,7 +6,7 @@ dnl Tell the user about autoconf.html in the --help output
m4_divert_once([HELP_END], [
See docs/autoconf.html for more details on the options for Mesa.])
-AC_INIT([Mesa], [9.1.0],
+AC_INIT([Mesa], [9.1.1],
[https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa])
AC_CONFIG_AUX_DIR([bin])
AC_CONFIG_MACRO_DIR([m4])
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index a98aadf..cd0b0a5 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -34,8 +34,8 @@ struct gl_context;
/* Mesa version */
#define MESA_MAJOR 9
#define MESA_MINOR 1
-#define MESA_PATCH 0
-#define MESA_VERSION_STRING "9.1"
+#define MESA_PATCH 1
+#define MESA_VERSION_STRING "9.1.1"
/* To make version comparison easy */
#define MESA_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
commit 9e36e41034a9dce3fe3f03650f4f54f06dcbf10f
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Tue Mar 19 17:11:41 2013 -0700
docs: 9.1.1 release notes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/docs/relnotes-9.1.1.html b/docs/relnotes-9.1.1.html
new file mode 100644
index 0000000..8921c8f
--- /dev/null
+++ b/docs/relnotes-9.1.1.html
@@ -0,0 +1,232 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 9.1.1 Release Notes / March 19th, 2013</h1>
+
+<p>
+Mesa 9.1.1 is a bug fix release which fixes bugs found since the 9.1 release.
+</p>
+<p>
+Mesa 9.1 implements the OpenGL 3.1 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.1. OpenGL
+3.1 is <strong>only</strong> available if requested at context creation
+because GL_ARB_compatibility is not supported.
+</p>
+
+<h2>MD5 checksums</h2>
+<pre>
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=30232";>Bug 30232</a> - [GM45] mesa demos spriteblast render incorrectly</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=32429";>Bug 32429</a> - [gles2] Ironlake: gl_PointCoord takes no effect for point sprites</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=38086";>Bug 38086</a> - Mesa 7.11-devel implementation error: Unexpected program target in destroy_program_variants_cb()</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=57121";>Bug 57121</a> - [snb] corrupted GLSL built-in function results when using Uniform Buffer contents as arguments</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58042";>Bug 58042</a> - [bisected] Garbled UI in Team Fortress 2 and Counter-Strike: Source</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=58960";>Bug 58960</a> - Texture flicker with fragment shader</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59495";>Bug 59495</a> - [i965 Bisected]Oglc fbblit(advanced.blitFb-3d-cube.mirror.both) fails</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=59783";>Bug 59783</a> - [IVB bisected] 3DMMES2.0 Taiji performance reduced by ~13% with gnome-session enable compositing</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60121";>Bug 60121</a> - build - libvdpau_softpipe fails at runtime.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60143";>Bug 60143</a> - gbm_dri_bo_create fails to initialize bo->base.base.format</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60802";>Bug 60802</a> - Corruption with DMA ring on cayman</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60848";>Bug 60848</a> - [bisected] r600g: add htile support cause gpu lockup in Dishonored wine.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=60938";>Bug 60938</a> - [softpipe] piglit interpolation-noperspective-gl_BackColor-flat-fixed regression</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61012";>Bug 61012</a> - alloc_layout_array tx * ty assertion failure when making pbuffer current</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=61026";>Bug 61026</a> - Segfault in glBitmap when called with PBO source</li>
+
+<!-- <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=";>Bug </a> - </li> -->
+</ul>
+
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+ git log mesa-9.1..mesa-9.1.1
+</pre>
+
+
+<p>Adam Sampson (1):</p>
+<ul>
+ <li>autotools: oprofilejit should be included in the list of LLVM components required</li>
+</ul>
+
+<p>Alex Deucher (2):</p>
+<ul>
+ <li>r600g: add Richland APU pci ids</li>
+ <li>r600g: Use blitter rather than DMA for 128bpp on cayman (v3)</li>
+</ul>
+
+<p>Andreas Boll (2):</p>
+<ul>
+ <li>docs: Add 9.1 release md5sums</li>
+ <li>docs: add news item for 9.1 release</li>
+</ul>
+
+<p>Anuj Phogat (1):</p>
+<ul>
+ <li>meta: Allocate texture before initializing texture coordinates</li>
+</ul>
+
+<p>Brian Paul (11):</p>
+<ul>
+ <li>docs: remove stray 'date' text</li>
+ <li>docs: insert links to the 9.0.3 release</li>
+ <li>draw: fix non-perspective interpolation in interp()</li>
+ <li>st/mesa: implement glBitmap unpacking from a PBO, for the cache path</li>
+ <li>st/xlib: initialize the drawable size in create_xmesa_buffer()</li>
+ <li>st/mesa: fix trimming of GL_QUAD_STRIP</li>
+ <li>st/mesa: check for dummy programs in destroy_program_variants()</li>
+ <li>st/mesa: fix polygon offset state translation logic</li>
+ <li>draw: fix broken polygon offset stage</li>
+ <li>llvmpipe: add missing checks for polygon offset point/line modes</li>
+ <li>svga: always link with C++</li>
+</ul>
+
+<p>Daniel van Vugt (1):</p>
+<ul>
+ <li>gbm: Remember to init format on gbm_dri_bo_create.</li>
+</ul>
+
+<p>Eric Anholt (7):</p>
+<ul>
+ <li>i965/fs: Do a general SEND dependency workaround for the original 965.</li>
+ <li>i965/fs: Fix copy propagation with smearing.</li>
+ <li>i965/fs: Delay setup of uniform loads until after pre-regalloc scheduling.</li>
+ <li>i965/fs: Only do CSE when the dst types match.</li>
+ <li>i965/fs: Fix broken math on values loaded from uniform buffers on gen6.</li>
+ <li>mesa: Fix setup of ctx->Point.PointSprite for GLES2.</li>
+ <li>i965: Fix the W value of deprecated pointcoords on pre-gen6.</li>
+</ul>
+
+<p>Frank Henigman (1):</p>
+<ul>
+ <li>i965: Link i965_dri.so with C++ linker.</li>
+</ul>
+
+<p>Ian Romanick (3):</p>
+<ul>
+ <li>mesa: Add previously picked commit to .cherry-ignore</li>
+ <li>mesa: Modify candidate search string</li>
+ <li>egl: Allow 24-bit visuals for 32-bit RGBA8888 configs</li>
+</ul>
+
+<p>Jakub Bogusz (1):</p>
+<ul>
+ <li>vdpau-softpipe: Build correct source file - vl_winsys_xsp.c</li>
+</ul>
+
+<p>Jerome Glisse (1):</p>
+<ul>
+ <li>r600g: workaround hyperz lockup on evergreen</li>
+</ul>
+
+<p>John Kåre Alsaker (1):</p>
+<ul>
+ <li>llvmpipe: Fix creation of shared and scanout textures.</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+ <li>attrib: push/pop FRAGMENT_PROGRAM_ARB state</li>
+</ul>
+
+<p>José Fonseca (3):</p>
+<ul>
+ <li>scons: Allows choosing VS 10 or 11.</li>
+ <li>scons: Define _ALLOW_KEYWORD_MACROS on MSVC builds.</li>
+ <li>scons: Warn when using MSVS versions prior to 2012.</li>
+</ul>
+
+<p>Keith Kriewall (1):</p>
+<ul>
+ <li>scons: Fix Windows build with LLVM 3.2</li>
+</ul>
+
+<p>Kenneth Graunke (1):</p>
+<ul>
+ <li>i965: Fix Crystal Well PCI IDs.</li>
+</ul>
+
+<p>Marek Olšák (5):</p>
+<ul>
+ <li>r600g: use async DMA with a non-zero src offset</li>
+ <li>r600g: flush and invalidate htile cache when appropriate</li>
+ <li>gallium/util: add helper code for 1D integer range</li>
+ <li>r600g: always map uninitialized buffer range as unsynchronized</li>
+ <li>r600g: pad the DMA CS to a multiple of 8 dwords</li>
+</ul>
+
+<p>Martin Andersson (1):</p>
+<ul>
+ <li>winsys/radeon: Only add bo to hash table when creating flink</li>
+</ul>
+
+<p>Matt Turner (1):</p>
+<ul>
+ <li>mesa: Allow ETC2/EAC formats with ARB_ES3_compatibility.</li>
+</ul>
+
+<p>Michel Dänzer (3):</p>
+<ul>
+ <li>radeonsi: Fix up and enable flat shading.</li>
+ <li>r600g/Cayman: Fix blending using destination alpha factor but non-alpha dest</li>
+ <li>radeonsi: Fix off-by-one for maximum vertex element index in some cases</li>
+</ul>
+
+<p>Tapani Pälli (2):</p>
+<ul>
+ <li>mesa: add missing case in _mesa_GetTexParameterfv()</li>
+ <li>mesa/es: NULL check in EGLImageTargetTexture2DOES</li>
+</ul>
+
+<p>Vadim Girlin (1):</p>
+<ul>
+ <li>r600g: fix check_and_set_bank_swizzle for cayman</li>
+</ul>
+
+<p>Vincent Lejeune (2):</p>
+<ul>
+ <li>r600g/llvm: Add support for UBO</li>
+ <li>r600g: Check comp_mask before merging export instructions</li>
+</ul>
+
+</div>
+</body>
+</html>
commit d0ccb5b91191251c2a76ef43819c0a7704cecaba
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Mar 15 14:29:24 2013 -0400
r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
On cayman, 128bpp surfaces require non_disp ordering for hw
access to both linear and tiled surfaces. When we use the 3D
engine we can set the non_disp ordering on both the tiled and
linear sides (via CB or texture), but when we use the DMA
engine, we can only set the non_disp ordering on the tiled
side, so after a L2T operation with the DMA engine, the data
ends up in the wrong order on the tiled side.
v2: cayman/TN only
v3: fix comments
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802
Note: this is a candidate for the 9.1 branch.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 4409758a046a47b09cdd339f97afd22107c68f0c)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 33f306c..804c037 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3676,6 +3676,17 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
return FALSE;
}
+ /* 128 bpp surfaces require non_disp_tiling for both
+ * tiled and linear buffers on cayman. However, async
+ * DMA only supports it on the tiled side. As such
+ * the tile order is backwards after a L2T/T2L packet.
+ */
+ if ((rctx->chip_class == CAYMAN) &&
+ (src_mode != dst_mode) &&
+ (util_format_get_blocksize(src->format) >= 16)) {
+ return FALSE;
+ }
+
if (src_mode == dst_mode) {
uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
commit 61e7c043ea4b787e0ec47e827fb57f7091a3b61a
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Mar 8 13:52:37 2013 -0500
r600g: add Richland APU pci ids
Note: this is a candidate for the stable branches.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 03eef7f8ef98f1008a8687bbd7ee0141b433887a)
diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h
index 7ceb820..9c9bab2 100644
--- a/include/pci_ids/r600_pci_ids.h
+++ b/include/pci_ids/r600_pci_ids.h
@@ -298,6 +298,10 @@ CHIPSET(0x9907, ARUBA_9907, ARUBA)
CHIPSET(0x9908, ARUBA_9908, ARUBA)
CHIPSET(0x9909, ARUBA_9909, ARUBA)
CHIPSET(0x990A, ARUBA_990A, ARUBA)
+CHIPSET(0x990B, ARUBA_990B, ARUBA)
+CHIPSET(0x990C, ARUBA_990C, ARUBA)
+CHIPSET(0x990D, ARUBA_990D, ARUBA)
+CHIPSET(0x990E, ARUBA_990E, ARUBA)
CHIPSET(0x990F, ARUBA_990F, ARUBA)
CHIPSET(0x9910, ARUBA_9910, ARUBA)
CHIPSET(0x9913, ARUBA_9913, ARUBA)
@@ -309,6 +313,13 @@ CHIPSET(0x9991, ARUBA_9991, ARUBA)
CHIPSET(0x9992, ARUBA_9992, ARUBA)
CHIPSET(0x9993, ARUBA_9993, ARUBA)
CHIPSET(0x9994, ARUBA_9994, ARUBA)
+CHIPSET(0x9995, ARUBA_9995, ARUBA)
+CHIPSET(0x9996, ARUBA_9996, ARUBA)
+CHIPSET(0x9997, ARUBA_9997, ARUBA)
+CHIPSET(0x9998, ARUBA_9998, ARUBA)
+CHIPSET(0x9999, ARUBA_9999, ARUBA)
+CHIPSET(0x999A, ARUBA_999A, ARUBA)
+CHIPSET(0x999B, ARUBA_999B, ARUBA)
CHIPSET(0x99A0, ARUBA_99A0, ARUBA)
CHIPSET(0x99A2, ARUBA_99A2, ARUBA)
CHIPSET(0x99A4, ARUBA_99A4, ARUBA)
commit 231247df02d1c7e91c743a248ef3b2c9a574a090
Author: José Fonseca <jfonseca@vmware.com>
Date: Fri Mar 15 15:23:54 2013 +0000
scons: Warn when using MSVS versions prior to 2012.
Reviewed-by: Brian Paul <brianp@vmware.com>
diff --git a/scons/gallium.py b/scons/gallium.py
index 4d3de82..b28be5d 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -402,6 +402,8 @@ def generate(env):
'/Oi', # enable intrinsic functions
]
else:
+ if distutils.version.LooseVersion(env['MSVC_VERSION']) < distutils.version.LooseVersion('11.0'):
+ print 'scons: warning: Visual Studio versions prior to 2012 are known to produce incorrect code when optimizations are enabled ( https://bugs.freedesktop.org/show_bug.cgi?id=58718 )'
ccflags += [
'/O2', # optimize for speed
]
commit 5d66947d66c4f80d4a26ad19029ecb6697a19e61
Author: José Fonseca <jfonseca@vmware.com>
Date: Thu Mar 14 17:40:14 2013 +0000
scons: Define _ALLOW_KEYWORD_MACROS on MSVC builds.
scons/llvm.py defines inline globally to workaround issues with LLVM C
binding headers, so the only way to is to avoid
aggravating xkeycheck.h errors is to set _ALLOW_KEYWORD_MACROS.
This fixes MSVC 2012 build with LLVM.
Reviewed-by: Brian Paul <brianp@vmware.com>
diff --git a/scons/gallium.py b/scons/gallium.py
index 4b51b6e..4d3de82 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -289,6 +289,7 @@ def generate(env):
'_CRT_SECURE_NO_DEPRECATE',
'_SCL_SECURE_NO_WARNINGS',
'_SCL_SECURE_NO_DEPRECATE',
+ '_ALLOW_KEYWORD_MACROS',
]
if env['build'] in ('debug', 'checked'):
cppdefines += ['_DEBUG']
commit 0acc79322b2505e7d2e3e0ad98b2df98b9ed5bf7
Author: José Fonseca <jfonseca@vmware.com>
Date: Tue Mar 12 20:33:38 2013 +0000
scons: Allows choosing VS 10 or 11.
NOTE: Candidate for the stable branches.
Reviewed-by: Brian Paul <brianp@vmware.com>
diff --git a/common.py b/common.py
index 6ff9608..1d618e6 100644
--- a/common.py
+++ b/common.py
@@ -100,4 +100,4 @@ def AddOptions(opts):
opts.Add(BoolOption('quiet', 'DEPRECATED: profile build', 'yes'))
opts.Add(BoolOption('texture_float', 'enable floating-point textures and renderbuffers', 'no'))
if host_platform == 'windows':
- opts.Add(EnumOption('MSVS_VERSION', 'MS Visual C++ version', None, allowed_values=('7.1', '8.0', '9.0')))
+ opts.Add(EnumOption('MSVC_VERSION', 'MS Visual C++ version', None, allowed_values=('7.1', '8.0', '9.0', '10.0', '11.0')))
commit 5ccaa67204faaa41ecc4ec2daf3a607f24bbeaaa
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Tue Mar 12 12:34:37 2013 +0100
radeonsi: Fix off-by-one for maximum vertex element index in some cases
In cases where the vertex element size is smaller than the vertex buffer
stride, the previous calculation could end up 1 too low. This would result
in the GPU using index 0 instead of the maximum index for those elements,
which would be visible as intermittent distorted triangles.
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 4dca602521c51a4cb03855bda9c22b5ccc4829c7)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 61dea74..8c35625 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -445,8 +445,14 @@ static void si_vertex_buffer_update(struct r600_context *rctx)
si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vb->stride)));
- si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) /
- MAX2(vb->stride, 1));
+ if (vb->stride)
+ /* Round up by rounding down and adding 1 */
+ si_pm4_sh_data_add(pm4,
+ (vb->buffer->width0 - offset -
+ util_format_get_blocksize(ve->src_format)) /
+ vb->stride + 1);
+ else
+ si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
if (!bound[ve->vertex_buffer_index]) {
commit d72f8e21245c6374da680a8276060d5a68381487
Author: Cyril Brulebois <kibi@debian.org>
Date: Wed Mar 13 22:05:42 2013 +0100
Upload to unstable.
diff --git a/debian/changelog b/debian/changelog
index 7ed256d..2bff87c 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (8.0.5-4) UNRELEASED; urgency=low
+mesa (8.0.5-4) unstable; urgency=low
* Cherry-pick commit 17f1cb1d99 (dri/nouveau: fix crash in
nouveau_flush) from upstream master branch.
commit b79b607dbdc23ec0524ace3719f061f66a5ae305
Author: Sven Joachim <svenjoac@gmx.de>
Date: Wed Mar 13 17:52:36 2013 +0100
Document the cherry-pick in debian/changelog
diff --git a/debian/changelog b/debian/changelog
index e5aba72..7ed256d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+mesa (8.0.5-4) UNRELEASED; urgency=low
+
+ * Cherry-pick commit 17f1cb1d99 (dri/nouveau: fix crash in
+ nouveau_flush) from upstream master branch.
+
+ -- Sven Joachim <svenjoac@gmx.de> Wed, 13 Mar 2013 17:52:18 +0100
+
mesa (8.0.5-3) unstable; urgency=high
* mesa: add bounds checking for uniform array access (CVE-2012-5129).
commit 82b40f3729cbe4e100d10d2ef99db84ca919a9b9
Author: Jan de Groot <jan@jgc.homeip.net>
Date: Thu Mar 7 19:48:13 2013 +0100
dri/nouveau: fix crash in nouveau_flush
https://bugs.freedesktop.org/show_bug.cgi?id=61947
Note: this is a candidate for the stable branches
(cherry picked from commit 17f1cb1d99e66227d1e05925ef937643f5c1089a)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.c b/src/mesa/drivers/dri/nouveau/nouveau_driver.c
index ba818f0..4f885bb 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_driver.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_driver.c
@@ -67,7 +67,8 @@ nouveau_flush(struct gl_context *ctx)
__DRIdri2LoaderExtension *dri2 = screen->dri2.loader;
__DRIdrawable *drawable = nctx->dri_context->driDrawablePriv;
- dri2->flushFrontBuffer(drawable, drawable->loaderPrivate);
+ if (drawable && drawable->loaderPrivate)
+ dri2->flushFrontBuffer(drawable, drawable->loaderPrivate);
}
}
commit ed29a987fd9e76ee9b80a4f9cc0079ec22b1124b
Author: Frank Henigman <fjhenigman@google.com>
Date: Thu Feb 28 21:21:51 2013 -0500
i965: Link i965_dri.so with C++ linker.
Force C++ linking of i965_dri.so by adding a dummy C++ source file.
Reviewed-by: Matt Turner <mattst88@gmail.com>
diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/mesa/drivers/dri/i965/Makefile.am
index dc140df..77670ef 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -62,6 +62,7 @@ TEST_LIBS = \
../common/libdri_test_stubs.la
i965_dri_la_SOURCES =
+nodist_EXTRA_i965_dri_la_SOURCES = dummy2.cpp
i965_dri_la_LIBADD = $(COMMON_LIBS)
i965_dri_la_LDFLAGS = -module -avoid-version -shared
commit e3f1b34fbe360111f90d6b7f11b11c4f4b17485b
Author: Matt Turner <mattst88@gmail.com>
Date: Mon Mar 4 11:32:32 2013 -0800
mesa: Allow ETC2/EAC formats with ARB_ES3_compatibility.
Fixes piglit's oes_compressed_etc2_texture-miptree tests on Desktop GL.
Reported-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 8728540..c1e1658 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -917,7 +917,7 @@ _mesa_is_compressed_format(struct gl_context *ctx, GLenum format)
case GL_COMPRESSED_SIGNED_RG11_EAC:
case GL_COMPRESSED_RGB8_PUNCHTHROUGH_ALPHA1_ETC2:
case GL_COMPRESSED_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2:
- return _mesa_is_gles3(ctx);
+ return _mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility;
case GL_PALETTE4_RGB8_OES:
case GL_PALETTE4_RGBA8_OES:
case GL_PALETTE4_R5_G6_B5_OES:
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 6251173..1b9525b 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -520,7 +520,7 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint internalFormat )
}
}
- if (_mesa_is_gles3(ctx)) {
+ if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility) {
switch (internalFormat) {
case GL_COMPRESSED_RGB8_ETC2:
case GL_COMPRESSED_SRGB8_ETC2:
commit 09199c68627f738b51bb9fd385e4528b3f0fbc77
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed Feb 27 21:24:02 2013 +0100
r600g: pad the DMA CS to a multiple of 8 dwords
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit c77917d35fdf64d9f194fbecc4748213621eefc8)
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index a59578d..a7973a5 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -22,6 +22,7 @@
*/
#include "r600_pipe.h"
#include "r600_public.h"
+#include "r600d.h"
#include <errno.h>
#include "pipe/p_shader_tokens.h"
@@ -165,12 +166,23 @@ static void r600_flush_gfx_ring(void *ctx, unsigned flags)
static void r600_flush_dma_ring(void *ctx, unsigned flags)
{
struct r600_context *rctx = (struct r600_context *)ctx;
+ struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
+ unsigned padding_dw, i;
- if (!rctx->rings.dma.cs->cdw) {
+ if (!cs->cdw) {
return;
}
+
+ /* Pad the DMA CS to a multiple of 8 dwords. */
+ padding_dw = 8 - cs->cdw % 8;
+ if (padding_dw < 8) {
+ for (i = 0; i < padding_dw; i++) {
+ cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
+ }
+ }
+
rctx->rings.dma.flushing = true;
- rctx->ws->cs_flush(rctx->rings.dma.cs, flags);
+ rctx->ws->cs_flush(cs, flags);
rctx->rings.dma.flushing = false;
}
commit 1dc162d52fab6a7cd5e5e7fd60c9af603a1e541e
Author: Vincent Lejeune <vljn@ovi.com>
Date: Sun Mar 3 21:35:38 2013 +0100
r600g: Check comp_mask before merging export instructions
Fixes a llvm uncovered (rare) bug where consecutive exports were
merged even if they have incompatible mask.
(cherry picked from commit 83e7d111afd8d340ce8fe13ea139271400eb362e)
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 451b072..bda425c 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -322,6 +322,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
output->swizzle_y == bc->cf_last->output.swizzle_y &&
output->swizzle_z == bc->cf_last->output.swizzle_z &&
output->swizzle_w == bc->cf_last->output.swizzle_w &&
+ output->comp_mask == bc->cf_last->output.comp_mask &&
(output->burst_count + bc->cf_last->output.burst_count) <= 16) {
if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
commit 9a5f5137739acebfa3408aa8368a5a407ff9ef9c
Author: Vadim Girlin <vadimgirlin@gmail.com>
Date: Tue Feb 26 20:50:25 2013 +0400
r600g: fix check_and_set_bank_swizzle for cayman
Tested-by: Vincent Lejeune <vljn at ovi.com>
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
(cherry picked from commit 138b5b9a12b7e1537494aac556589ac9981b557b)
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index f25c6aa..451b072 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -873,12 +873,6 @@ static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
bank_swizzle[4] = SQ_ALU_SCL_210;
while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
- if (max_slots == 4) {
- for (i = 0; i < max_slots; i++) {
- if (bank_swizzle[i] == SQ_ALU_VEC_210)
- return -1;
- }
- }
init_bank_swizzle(&bs);
if (scalar_only == false) {
for (i = 0; i < 4; i++) {
@@ -910,8 +904,10 @@ static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
bank_swizzle[i]++;
if (bank_swizzle[i] <= SQ_ALU_VEC_210)
break;
- else
+ else if (i < max_slots - 1)
bank_swizzle[i] = SQ_ALU_VEC_012;
+ else
+ return -1;
}
}
}
commit 26e827b3099fe5c01dfb77bba48d0d6c5c334722
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri Mar 1 15:23:53 2013 -0800
i965: Fix Crystal Well PCI IDs.
The second digit was off by one, which meant we accidentally treated
GTn as GT(n-1). This also meant no support for GT1 at all.
NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit b88f74d63dca9db0f1b1cb9ce4d85f706c7a7fab)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 09dca5b..1e388f8 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -53,12 +53,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
-CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1)
-CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2)
-CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2)
-CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1)
-CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2)
-CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
-CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1)
-CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2)
-CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1)
+CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2)
+CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1)
+CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2)
+CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
+CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
+CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
+CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index 9c00ba8..885f6c2 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -114,15 +114,15 @@
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
+#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
+#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \
commit 44a5b5d161db496ec6a9c450a0f369b3356696f2
Author: Brian Paul <brianp@vmware.com>
Date: Fri Mar 1 16:53:22 2013 -0700
svga: always link with C++
Even when we don't have LLVM since there's other C++ code
in the resulting DRI driver object.
Note: This is a candidate for the stable branches.
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit a99eb5c83fd64d64fee2b6d7f2bb3fea3264ce47)
diff --git a/src/gallium/targets/dri-vmwgfx/Makefile.am b/src/gallium/targets/dri-vmwgfx/Makefile.am
index 06ebf88..ca7df65 100644
--- a/src/gallium/targets/dri-vmwgfx/Makefile.am
+++ b/src/gallium/targets/dri-vmwgfx/Makefile.am
@@ -58,17 +58,13 @@ vmwgfx_dri_la_LIBADD = \
$(top_builddir)/src/gallium/drivers/svga/libsvga.la \
$(GALLIUM_DRI_LIB_DEPS)
-if HAVE_MESA_LLVM
vmwgfx_dri_la_LINK = $(CXXLINK) $(vmwgfx_dri_la_LDFLAGS)
# Mention a dummy pure C++ file to trigger generation of the $(LINK) variable
nodist_EXTRA_vmwgfx_dri_la_SOURCES = dummy-cpp.cpp
+if HAVE_MESA_LLVM
vmwgfx_dri_la_LDFLAGS += $(LLVM_LDFLAGS)
vmwgfx_dri_la_LIBADD += $(LLVM_LIBS)
-else
-vmwgfx_dri_la_LINK = $(LINK) $(vmwgfx_dri_la_LDFLAGS)
-# Mention a dummy pure C file to trigger generation of the $(LINK) variable
-nodist_EXTRA_vmwgfx_dri_la_SOURCES = dummy-c.c
endif
# Provide compatibility with scripts for the old Mesa build system for
commit f6765c6d20519476d9a52033b65e3a6d109a5115
Author: Marek Olšák <maraeo@gmail.com>
Date: Wed Feb 27 23:50:15 2013 +0100
r600g: always map uninitialized buffer range as unsynchronized
Any driver can implement this simple and efficient optimization.
Team Fortress 2 hits it always. The DISCARD_RANGE codepath is not even used
with TF2 anymore, so we avoid a ton of useless buffer copies.
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit 89e2898e9ecfcf93c337b99542b06892a8e30cbe)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index bb47530..bb43353 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -283,4 +283,7 @@ void evergreen_dma_copy(struct r600_context *rctx,
src_offset += csize << shift;
size -= csize;
}
+
+ util_range_add(&rdst->valid_buffer_range, dst_offset,
+ dst_offset + size);
}
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 4407ac5..33f306c 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1322,6 +1322,10 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
* elements. */
surf->cb_color_dim = pipe_buffer->width0;
+ /* Set the buffer range the GPU will have access to: */
+ util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
+ 0, pipe_buffer->width0);
+
surf->cb_color_cmask = surf->cb_color_base;
surf->cb_color_cmask_slice = 0;
surf->cb_color_fmask = surf->cb_color_base;
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 6832bf7..0115293 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -28,6 +28,7 @@
#include "../../winsys/radeon/drm/radeon_winsys.h"
#include "util/u_double_list.h"
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