mesa: Changes to 'upstream-experimental'
Rebased ref, commits from common ancestor:
commit ff515c4e7cbd9f549e6b9054609ac380bec18468
Author: Matt Turner <mattst88@gmail.com>
Date: Tue Jan 29 11:22:06 2013 -0800
build: Add missing comma in AS_IF
Reported-by: Lauri Kasanen<curaga@operamail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47248#c15
diff --git a/configure.ac b/configure.ac
index 1e352db..564ca3c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -57,10 +57,10 @@ LT_PREREQ([2.2])
LT_INIT([disable-static])
AX_PROG_BISON([],
- AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-parse.c"]
+ AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-parse.c"],
[AC_MSG_ERROR([bison not found - unable to compile glcpp-parse.y])]))
AX_PROG_FLEX([],
- AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-lex.c"]
+ AS_IF([test ! -f "$srcdir/src/glsl/glcpp/glcpp-lex.c"],
[AC_MSG_ERROR([flex not found - unable to compile glcpp-lex.l])]))
AC_PATH_PROG([PERL], [perl])
commit d7ca04a7c3a7f9170469615affcb4f6eebd524e5
Author: Marek Olšák <maraeo@gmail.com>
Date: Tue Jan 29 17:32:14 2013 +0100
docs/relnotes-9.1: document new features in radeon drivers
(cherry picked from commit 845130951f9f62a1baba9ae9ea2b234e83ac5c94)
diff --git a/docs/relnotes-9.1.html b/docs/relnotes-9.1.html
index 036290e..350ae27 100644
--- a/docs/relnotes-9.1.html
+++ b/docs/relnotes-9.1.html
@@ -54,6 +54,8 @@ Note: some of the new features are only available with certain drivers.
<li>GL_ARB_texture_cube_map_array</li>
<li>GL_EXT_color_buffer_float</li>
<li>GL_OES_depth_texture_cube_map</li>
+<li>OpenGL 3.1 core profile support on Radeon HD2000 up to HD6000 series </li>
+<li>Multisample anti-aliasing support on Radeon X1000 series</li>
</ul>
commit 48af880f815b8f37d9c6e77e314d264250f742b0
Author: Matt Turner <mattst88@gmail.com>
Date: Fri Jan 25 15:06:16 2013 -0800
docs: List new extensions added in Mesa 9.1
I did not list the *_get_program_binary extensions since they're not
useful to anyone with their current implementation (that supports 0
binary formats).
diff --git a/docs/relnotes-9.1.html b/docs/relnotes-9.1.html
index ffca275..036290e 100644
--- a/docs/relnotes-9.1.html
+++ b/docs/relnotes-9.1.html
@@ -44,9 +44,16 @@ Note: some of the new features are only available with certain drivers.
</p>
<ul>
+<li>GL_ANGLE_texture_compression_dxt3</li>
+<li>GL_ANGLE_texture_compression_dxt5</li>
+<li>GL_ARB_ES3_compatibility</li>
+<li>GL_ARB_internalformat_query</li>
<li>GL_ARB_map_buffer_alignment</li>
-<li>GL_ARB_texture_cube_map_array</li>
+<li>GL_ARB_shading_language_packing</li>
<li>GL_ARB_texture_buffer_object_rgb32</li>
+<li>GL_ARB_texture_cube_map_array</li>
+<li>GL_EXT_color_buffer_float</li>
+<li>GL_OES_depth_texture_cube_map</li>
</ul>
commit af2d8f8072c53d4c63ed22b74f78213c1181c1eb
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Jan 28 19:07:10 2013 -0500
r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index ca4f4b3..bb47530 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -243,9 +243,9 @@ void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_en
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size)
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
unsigned i, ncopy, csize, sub_cmd, shift;
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index be1c427..0a3861f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3481,7 +3481,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
- unsigned long base, addr;
+ uint64_t base, addr;
/* make sure that the dma ring is only one active */
rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3625,7 +3625,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
}
if (src_mode == dst_mode) {
- unsigned long dst_offset, src_offset;
+ uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
* src_box.x/y == 0
* dst_x/y == 0
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index a383c90..08b77e4 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -174,9 +174,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size);
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
boolean r600_dma_blit(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
@@ -187,9 +187,9 @@ boolean r600_dma_blit(struct pipe_context *ctx,
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size);
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
boolean evergreen_dma_blit(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index ebafd97..23f488a 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1160,9 +1160,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size)
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
unsigned i, ncopy, csize, shift;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 6b4b2c3..c0bc2a5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2979,7 +2979,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
- unsigned long base, addr;
+ uint64_t base, addr;
/* make sure that the dma ring is only one active */
rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3109,7 +3109,7 @@ boolean r600_dma_blit(struct pipe_context *ctx,
}
if (src_mode == dst_mode) {
- unsigned long dst_offset, src_offset, size;
+ uint64_t dst_offset, src_offset, size;
/* simple dma blit would do NOTE code here assume :
* src_box.x/y == 0
commit d8d17441e2b5b777b12b3fdeea9d33aa7510f3f1
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Jan 28 17:14:09 2013 -0500
r600g: real fix for non 3.8 kernel
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 0f51eb2..3ff42d3 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -869,9 +869,11 @@ static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
* look serialized from driver pov
*/
if (!ring->flushing) {
- if (ring == &ctx->rings.gfx && ctx->rings.dma.cs) {
- /* flush dma ring */
- ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ if (ring == &ctx->rings.gfx) {
+ if (ctx->rings.dma.cs) {
+ /* flush dma ring */
+ ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
} else {
/* flush gfx ring */
ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
commit 72916698b056d0559263e84372bb45cd83a1c2c2
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Jan 28 14:48:46 2013 -0500
r600g: fix segfault with old kernel
Old kernel do not have dma support, patch pushed were missing some
of the check needed to not use dma.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index f4a7905..128464e 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -321,7 +321,9 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
ctx->cs_shader_state.shader->resources;
/* make sure that the gfx ring is only one active */
- ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ if (ctx->rings.dma.cs) {
+ ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
/* Initialize all the compute-related registers.
*
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 6767412..a59578d 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -151,7 +151,9 @@ static void r600_flush_from_st(struct pipe_context *ctx,
*rfence = r600_create_fence(rctx);
}
/* flush gfx & dma ring, order does not matter as only one can be live */
- rctx->rings.dma.flush(rctx, fflags);
+ if (rctx->rings.dma.cs) {
+ rctx->rings.dma.flush(rctx, fflags);
+ }
rctx->rings.gfx.flush(rctx, fflags);
}
@@ -179,8 +181,10 @@ boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
return TRUE;
}
- if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
- return TRUE;
+ if (ctx->rings.dma.cs) {
+ if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
+ return TRUE;
+ }
}
return FALSE;
}
@@ -211,10 +215,12 @@ void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
return NULL;
}
}
- if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
- ctx->rings.dma.flush(ctx, flags);
- if (usage & PIPE_TRANSFER_DONTBLOCK) {
- return NULL;
+ if (ctx->rings.dma.cs) {
+ if (ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, resource->cs_buf, rusage) && ctx->rings.dma.cs->cdw) {
+ ctx->rings.dma.flush(ctx, flags);
+ if (usage & PIPE_TRANSFER_DONTBLOCK) {
+ return NULL;
+ }
}
}
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 31dcd05..0f51eb2 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -869,7 +869,7 @@ static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
* look serialized from driver pov
*/
if (!ring->flushing) {
- if (ring == &ctx->rings.gfx) {
+ if (ring == &ctx->rings.gfx && ctx->rings.dma.cs) {
/* flush dma ring */
ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
} else {
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index b547d64..9386f61 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1274,7 +1274,9 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
}
/* make sure that the gfx ring is only one active */
- rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ if (rctx->rings.dma.cs) {
+ rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ }
if (!r600_update_derived_state(rctx)) {
/* useless to render because current rendering command
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 96c3729..1d04cc0 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -851,7 +851,9 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
if (usage & PIPE_TRANSFER_READ) {
r600_copy_to_staging_texture(ctx, trans);
/* flush gfx & dma ring, order does not matter as only one can be live */
- rctx->rings.dma.flush(rctx, 0);
+ if (rctx->rings.dma.cs) {
+ rctx->rings.dma.flush(rctx, 0);
+ }
rctx->rings.gfx.flush(rctx, 0);
}
} else {
commit dbb2d192de33064ae6cdb799d71c5ac89a6ea8ff
Author: Zack Rusin <zackr@vmware.com>
Date: Thu Jan 24 17:48:12 2013 -0800
glx: only advertise GLX_INTEL_swap_event if it's supported
Only drivers supporting DRI2 version >=4 support GLX_INTEL_swap_event.
So lets mark it as such otherwise applications which use this extension
(i.e. everything based on Clutter, e.g. gnome-shell) break horribly on
drivers supporting DRI2 versions only up to 3.
Note: This is a candidate for the 9.0 branch.
Reviewed-by: Brian Paul <brianp@vmware.com>
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 1b3cf2b..a51716f 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -1062,8 +1062,9 @@ dri2BindExtensions(struct dri2_screen *psc, const __DRIextension **extensions)
__glXEnableDirectExtension(&psc->base, "GLX_MESA_swap_control");
__glXEnableDirectExtension(&psc->base, "GLX_SGI_make_current_read");
- /* FIXME: if DRI2 version supports it... */
- __glXEnableDirectExtension(&psc->base, "GLX_INTEL_swap_event");
+ if (psc->dri2->base.version >= 4) {
+ __glXEnableDirectExtension(&psc->base, "GLX_INTEL_swap_event");
+ }
if (psc->dri2->base.version >= 3) {
const unsigned mask = psc->dri2->getAPIMask(psc->driScreen);
commit c9343047cfc44039915e0b09fc94bd992559a982
Author: Vadim Girlin <vadimgirlin@gmail.com>
Date: Wed Jan 23 21:30:02 2013 +0100
r600g: improve inputs/interpolation handling with llvm backend
Get rid of special handling for reserved regs.
Use one intrinsic for all kinds of interpolation.
v2[Vincent Lejeune]: Rebased against current master
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c
index 9f8a095..913dccc 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -83,48 +83,40 @@ static LLVMValueRef llvm_fetch_system_value(
static LLVMValueRef
llvm_load_input_helper(
struct radeon_llvm_context * ctx,
- const char *intrinsic, unsigned idx)
+ unsigned idx, int interp, int ij_index)
{
- LLVMValueRef reg = lp_build_const_int32(
- ctx->soa.bld_base.base.gallivm,
- idx);
- return build_intrinsic(
- ctx->soa.bld_base.base.gallivm->builder,
- intrinsic,
- ctx->soa.bld_base.base.elem_type, ®, 1,
- LLVMReadNoneAttribute);
+ const struct lp_build_context * bb = &ctx->soa.bld_base.base;
+ LLVMValueRef arg[2];
+ int arg_count;
+ const char * intrinsic;
+
+ arg[0] = lp_build_const_int32(bb->gallivm, idx);
+
+ if (interp) {
+ intrinsic = "llvm.R600.interp.input";
+ arg[1] = lp_build_const_int32(bb->gallivm, ij_index);
+ arg_count = 2;
+ } else {
+ intrinsic = "llvm.R600.load.input";
+ arg_count = 1;
+ }
+
+ return build_intrinsic(bb->gallivm->builder, intrinsic,
+ bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
}
static LLVMValueRef
llvm_face_select_helper(
struct radeon_llvm_context * ctx,
- const char *intrinsic, unsigned face_register,
- unsigned frontcolor_register, unsigned backcolor_regiser)
+ unsigned face_loc, LLVMValueRef front_color, LLVMValueRef back_color)
{
-
- LLVMValueRef backcolor = llvm_load_input_helper(
- ctx,
- intrinsic,
- backcolor_regiser);
- LLVMValueRef front_color = llvm_load_input_helper(
- ctx,
- intrinsic,
- frontcolor_register);
- LLVMValueRef face = llvm_load_input_helper(
- ctx,
- "llvm.R600.load.input",
- face_register);
- LLVMValueRef is_face_positive = LLVMBuildFCmp(
- ctx->soa.bld_base.base.gallivm->builder,
- LLVMRealUGT, face,
- lp_build_const_float(ctx->soa.bld_base.base.gallivm, 0.0f),
- "");
- return LLVMBuildSelect(
- ctx->soa.bld_base.base.gallivm->builder,
- is_face_positive,
- front_color,
- backcolor,
- "");
+ const struct lp_build_context * bb = &ctx->soa.bld_base.base;
+ LLVMValueRef face = llvm_load_input_helper(ctx, face_loc, 0, 0);
+ LLVMValueRef is_front = LLVMBuildFCmp(
+ bb->gallivm->builder, LLVMRealUGT, face,
+ lp_build_const_float(bb->gallivm, 0.0f), "");
+ return LLVMBuildSelect(bb->gallivm->builder, is_front,
+ front_color, back_color, "");
}
static void llvm_load_input(
@@ -132,110 +124,59 @@ static void llvm_load_input(
unsigned input_index,
const struct tgsi_full_declaration *decl)
{
+ const struct r600_shader_io * input = &ctx->r600_inputs[input_index];
unsigned chan;
-
- const char *intrinsics = "llvm.R600.load.input";
- unsigned offset = 4 * ctx->reserved_reg_count;
-
- if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->chip_class >= EVERGREEN) {
- switch (decl->Interp.Interpolate) {
- case TGSI_INTERPOLATE_COLOR:
- case TGSI_INTERPOLATE_PERSPECTIVE:
- offset = 0;
- intrinsics = "llvm.R600.load.input.perspective";
- break;
- case TGSI_INTERPOLATE_LINEAR:
- offset = 0;
- intrinsics = "llvm.R600.load.input.linear";
- break;
- case TGSI_INTERPOLATE_CONSTANT:
- offset = 0;
- intrinsics = "llvm.R600.load.input.constant";
- break;
- default:
- assert(0 && "Unknow Interpolate mode");
- }
+ unsigned interp = 0;
+ int ij_index;
+ int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR);
+ LLVMValueRef v;
+
+ if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT &&
+ input->spi_sid) {
+ interp = 1;
+ ij_index = (input->interpolate > 0) ? input->ij_index : -1;
}
for (chan = 0; chan < 4; chan++) {
- unsigned soa_index = radeon_llvm_reg_index_soa(input_index,
- chan);
-
- switch (decl->Semantic.Name) {
- case TGSI_SEMANTIC_FACE:
- ctx->inputs[soa_index] = llvm_load_input_helper(ctx,
- "llvm.R600.load.input",
- 4 * ctx->face_input);
- break;
- case TGSI_SEMANTIC_POSITION:
- if (ctx->type != TGSI_PROCESSOR_FRAGMENT || chan != 3) {
- ctx->inputs[soa_index] = llvm_load_input_helper(ctx,
- "llvm.R600.load.input",
- soa_index + (ctx->reserved_reg_count * 4));
- } else {
- LLVMValueRef w_coord = llvm_load_input_helper(ctx,
- "llvm.R600.load.input",
- soa_index + (ctx->reserved_reg_count * 4));
- ctx->inputs[soa_index] = LLVMBuildFDiv(ctx->gallivm.builder,
- lp_build_const_float(&(ctx->gallivm), 1.0f), w_coord, "");
- }
- break;
- case TGSI_SEMANTIC_COLOR:
- if (ctx->two_side) {
- unsigned front_location, back_location;
- unsigned back_reg = ctx->r600_inputs[input_index]
- .potential_back_facing_reg;
- if (ctx->chip_class >= EVERGREEN) {
- front_location = 4 * ctx->r600_inputs[input_index].lds_pos + chan;
- back_location = 4 * ctx->r600_inputs[back_reg].lds_pos + chan;
- } else {
- front_location = soa_index + 4 * ctx->reserved_reg_count;
- back_location = radeon_llvm_reg_index_soa(
- ctx->r600_inputs[back_reg].gpr,
- chan);
- }
- ctx->inputs[soa_index] = llvm_face_select_helper(ctx,
- intrinsics,
- 4 * ctx->face_input, front_location, back_location);
- break;
- }
- default:
- {
- unsigned location;
- if (ctx->chip_class >= EVERGREEN) {
- location = 4 * ctx->r600_inputs[input_index].lds_pos + chan;
- } else {
- location = soa_index + 4 * ctx->reserved_reg_count;
- }
- /* The * 4 is assuming that we are in soa mode. */
- ctx->inputs[soa_index] = llvm_load_input_helper(ctx,
- intrinsics, location);
-
- break;
- }
+ unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+ int loc;
+
+ if (interp) {
+ loc = 4 * input->lds_pos + chan;
+ } else {
+ if (input->name == TGSI_SEMANTIC_FACE)
+ loc = 4 * ctx->face_gpr;
+ else
+ loc = 4 * input->gpr + chan;
+ }
+
+ v = llvm_load_input_helper(ctx, loc, interp, ij_index);
+
+ if (two_side) {
+ struct r600_shader_io * back_input =
+ &ctx->r600_inputs[input->back_color_input];
+ int back_loc = interp ? back_input->lds_pos : back_input->gpr;
+ LLVMValueRef v2;
+
+ back_loc = 4 * back_loc + chan;
+ v2 = llvm_load_input_helper(ctx, back_loc, interp, ij_index);
+ v = llvm_face_select_helper(ctx, 4 * ctx->face_gpr, v, v2);
+ } else if (input->name == TGSI_SEMANTIC_POSITION &&
+ ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) {
+ /* RCP for fragcoord.w */
+ v = LLVMBuildFDiv(ctx->gallivm.builder,
+ lp_build_const_float(&(ctx->gallivm), 1.0f),
+ v, "");
}
+
+ ctx->inputs[soa_index] = v;
}
}
static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
{
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
- struct lp_build_context * base = &bld_base->base;
- unsigned i;
- /* Reserve special input registers */
- for (i = 0; i < ctx->reserved_reg_count; i++) {
- unsigned chan;
- for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
- LLVMValueRef reg_index = lp_build_const_int32(
- base->gallivm,
- radeon_llvm_reg_index_soa(i, chan));
- lp_build_intrinsic_unary(base->gallivm->builder,
- "llvm.AMDGPU.reserve.reg",
- LLVMVoidTypeInContext(base->gallivm->context),
- reg_index);
- }
- }
}
static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index c16e467..e8992ba 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -650,19 +650,15 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
return 0;
}
-static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
+static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
+ int input)
{
- int i, r;
- struct r600_bytecode_alu alu;
- int gpr = 0, base_chan = 0;
int ij_index = 0;
if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
- ij_index = 0;
if (ctx->shader->input[input].centroid)
ij_index++;
} else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
- ij_index = 0;
/* if we have perspective add one */
if (ctx->input_perspective) {
ij_index++;
@@ -674,6 +670,16 @@ static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
ij_index++;
}
+ ctx->shader->input[input].ij_index = ij_index;
+}
+
+static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
+{
+ int i, r;
+ struct r600_bytecode_alu alu;
+ int gpr = 0, base_chan = 0;
+ int ij_index = ctx->shader->input[input].ij_index;
+
/* work out gpr and base_chan from index */
gpr = ij_index / 2;
base_chan = (2 * (ij_index % 2)) + 1;
@@ -806,12 +812,13 @@ static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
if (ctx->shader->input[index].spi_sid) {
ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
- if (!ctx->use_llvm) {
- if (ctx->shader->input[index].interpolate > 0) {
+ if (ctx->shader->input[index].interpolate > 0) {
+ evergreen_interp_assign_ij_index(ctx, index);
+ if (!ctx->use_llvm)
r = evergreen_interp_alu(ctx, index);
- } else {
+ } else {
+ if (!ctx->use_llvm)
r = evergreen_interp_flat(ctx, index);
- }
}
}
return r;
@@ -857,11 +864,11 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
i = ctx->shader->ninput++;
ctx->shader->input[i].name = d->Semantic.Name;
ctx->shader->input[i].sid = d->Semantic.Index;
- ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
ctx->shader->input[i].interpolate = d->Interp.Interpolate;
ctx->shader->input[i].centroid = d->Interp.Centroid;
ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+ ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
switch (ctx->shader->input[i].name) {
case TGSI_SEMANTIC_FACE:
ctx->face_gpr = ctx->shader->input[i].gpr;
@@ -883,11 +890,11 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
i = ctx->shader->noutput++;
ctx->shader->output[i].name = d->Semantic.Name;
ctx->shader->output[i].sid = d->Semantic.Index;
- ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
ctx->shader->output[i].interpolate = d->Interp.Interpolate;
ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
if (ctx->type == TGSI_PROCESSOR_VERTEX) {
+ ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
switch (d->Semantic.Name) {
case TGSI_SEMANTIC_CLIPDIST:
ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
@@ -1193,17 +1200,9 @@ static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
for (i = 0; i < count; i++) {
if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
- unsigned back_facing_reg = ctx->shader->input[i].potential_back_facing_reg;
- if (ctx->bc->chip_class >= EVERGREEN) {
- if ((r = evergreen_interp_input(ctx, back_facing_reg)))
- return r;
- }
-
- if (!ctx->use_llvm) {
- r = select_twoside_color(ctx, i, back_facing_reg);
- if (r)
- return r;
- }
+ r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
+ if (r)
+ return r;
}
}
return 0;
@@ -1396,7 +1395,11 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
// TGSI to LLVM needs to know the lds position of inputs.
// Non LLVM path computes it later (in process_twoside_color)
ctx.shader->input[ni].lds_pos = next_lds_loc++;
- ctx.shader->input[i].potential_back_facing_reg = ni;
+ ctx.shader->input[i].back_color_input = ni;
+ if (ctx.bc->chip_class >= EVERGREEN) {
+ if ((r = evergreen_interp_input(&ctx, ni)))
+ return r;
+ }
}
}
}
@@ -1408,10 +1411,9 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
LLVMModuleRef mod;
unsigned dump = 0;
memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
- radeon_llvm_ctx.reserved_reg_count = ctx.file_offset[TGSI_FILE_INPUT];
radeon_llvm_ctx.type = ctx.type;
radeon_llvm_ctx.two_side = shader->two_side;
- radeon_llvm_ctx.face_input = ctx.face_gpr;
+ radeon_llvm_ctx.face_gpr = ctx.face_gpr;
radeon_llvm_ctx.r600_inputs = ctx.shader->input;
radeon_llvm_ctx.r600_outputs = ctx.shader->output;
radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
@@ -1442,9 +1444,24 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
shader->nr_ps_max_color_exports = 8;
- if (ctx.fragcoord_input >= 0 && !use_llvm) {
- if (ctx.bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
+ if (!use_llvm) {
+ if (ctx.fragcoord_input >= 0) {
+ if (ctx.bc->chip_class == CAYMAN) {
+ for (j = 0 ; j < 4; j++) {
+ struct r600_bytecode_alu alu;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
+ alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
+ alu.src[0].chan = 3;
+
+ alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
+ alu.dst.chan = j;
+ alu.dst.write = (j == 3);
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
+ return r;
+ }
+ } else {
struct r600_bytecode_alu alu;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
@@ -1452,65 +1469,49 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
alu.src[0].chan = 3;
alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
- alu.dst.chan = j;
- alu.dst.write = (j == 3);
+ alu.dst.chan = 3;
+ alu.dst.write = 1;
alu.last = 1;
if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
return r;
}
- } else {
- struct r600_bytecode_alu alu;
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
- alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
- alu.src[0].chan = 3;
+ }
- alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
- alu.dst.chan = 3;
- alu.dst.write = 1;
- alu.last = 1;
- if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
+ if (shader->two_side && ctx.colors_used) {
+ if ((r = process_twoside_color_inputs(&ctx)))
return r;
}
- }
-
- if (shader->two_side && ctx.colors_used) {
- if ((r = process_twoside_color_inputs(&ctx)))
- return r;
- }
- tgsi_parse_init(&ctx.parse, tokens);
- while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
- tgsi_parse_token(&ctx.parse);
- switch (ctx.parse.FullToken.Token.Type) {
- case TGSI_TOKEN_TYPE_INSTRUCTION:
- if (use_llvm) {
- continue;
+ tgsi_parse_init(&ctx.parse, tokens);
+ while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
+ tgsi_parse_token(&ctx.parse);
+ switch (ctx.parse.FullToken.Token.Type) {
+ case TGSI_TOKEN_TYPE_INSTRUCTION:
+ r = tgsi_is_supported(&ctx);
+ if (r)
+ goto out_err;
+ ctx.max_driver_temp_used = 0;
+ /* reserve first tmp for everyone */
+ r600_get_temp(&ctx);
+
+ opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
+ if ((r = tgsi_split_constant(&ctx)))
+ goto out_err;
+ if ((r = tgsi_split_literal_constant(&ctx)))
+ goto out_err;
+ if (ctx.bc->chip_class == CAYMAN)
+ ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
+ else if (ctx.bc->chip_class >= EVERGREEN)
+ ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
+ else
+ ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
+ r = ctx.inst_info->process(&ctx);
+ if (r)
+ goto out_err;
+ break;
+ default:
+ break;
}
- r = tgsi_is_supported(&ctx);
- if (r)
- goto out_err;
- ctx.max_driver_temp_used = 0;
- /* reserve first tmp for everyone */
- r600_get_temp(&ctx);
-
- opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
- if ((r = tgsi_split_constant(&ctx)))
- goto out_err;
- if ((r = tgsi_split_literal_constant(&ctx)))
- goto out_err;
- if (ctx.bc->chip_class == CAYMAN)
- ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
- else if (ctx.bc->chip_class >= EVERGREEN)
- ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
- else
- ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
- r = ctx.inst_info->process(&ctx);
- if (r)
- goto out_err;
- break;
- default:
- break;
}
}
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index d61efcb..f55e002 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -32,9 +32,10 @@ struct r600_shader_io {
int sid;
int spi_sid;
unsigned interpolate;
+ unsigned ij_index;
boolean centroid;
unsigned lds_pos; /* for evergreen */
- unsigned potential_back_facing_reg;
+ unsigned back_color_input;
unsigned write_mask;
};
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h b/src/gallium/drivers/radeon/radeon_llvm.h
index 1edcbd4..64d838a 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -56,7 +56,7 @@ struct radeon_llvm_context {
unsigned chip_class;
unsigned type;
- unsigned face_input;
+ unsigned face_gpr;
unsigned two_side;
unsigned clip_vertex;
struct r600_shader_io * r600_inputs;
@@ -108,7 +108,6 @@ struct radeon_llvm_context {
LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
- unsigned reserved_reg_count;
/*=== Private Members ===*/
struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH];
commit 33dc412b8901ec6b693644a40b1cd62a2cde2e99
Author: Tom Stellard <thomas.stellard@amd.com>
Date: Tue Jan 22 21:22:11 2013 +0100
r600g: Add ar_chan member to struct r600_bytecode
r600_bytecode::ar_chan stores the register channel for the value that
will be loaded into the AR register.
At the moment, this field is only used by the LLVM backend. The default
backend always sets ar_chan = 0.
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 123a9f8..1a501f6 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1421,6 +1421,7 @@ static int load_ar_r6xx(struct r600_bytecode *bc)
memset(&alu, 0, sizeof(alu));
alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
alu.src[0].sel = bc->ar_reg;
+ alu.src[0].chan = bc->ar_chan;
alu.last = 1;
alu.index_mode = INDEX_MODE_LOOP;
r = r600_bytecode_add_alu(bc, &alu);
@@ -1451,6 +1452,7 @@ static int load_ar(struct r600_bytecode *bc)
memset(&alu, 0, sizeof(alu));
alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
alu.src[0].sel = bc->ar_reg;
+ alu.src[0].chan = bc->ar_chan;
alu.last = 1;
r = r600_bytecode_add_alu(bc, &alu);
if (r)
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 182f403..0b33c38 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -213,6 +213,7 @@ struct r600_bytecode {
struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH];
unsigned ar_loaded;
unsigned ar_reg;
+ unsigned ar_chan;
unsigned ar_handling;
unsigned r6xx_nop_after_rel_dst;
};
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 727fac9..c16e467 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -377,6 +377,7 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT)) {
ctx->bc->ar_reg = alu.src[0].sel;
+ ctx->bc->ar_chan = alu.src[0].chan;
ctx->bc->ar_loaded = 0;
return bytes_read;
}
commit 0ba0926861f489261e45404cd57d8f92add9e1ee
Author: Tom Stellard <thomas.stellard@amd.com>
Date: Tue Jan 22 21:22:10 2013 +0100
r600g: More robust checks for MOVA_INT instructions
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 07fe1df..123a9f8 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -480,6 +480,23 @@ static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *
}
}
+static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+{
+ unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
+ unsigned src;
+
+ if (alu->dst.rel) {
+ return 1;
+ }
+
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