xserver-xorg-video-ati: Changes to 'debian-unstable'
configure.ac | 4 +-
debian/changelog | 22 +++++++++++
man/radeon.man | 2 +
src/ati_pciids_gen.h | 23 +++++++++++-
src/cayman_shader.c | 36 +------------------
src/drmmode_display.c | 67 ++++++++++++++++++++----------------
src/drmmode_display.h | 1
src/evergreen_shader.c | 36 +------------------
src/evergreen_textured_videofuncs.c | 51 ++++++---------------------
src/pcidb/ati_pciids.csv | 23 +++++++++++-
src/r600_shader.c | 34 +-----------------
src/r600_textured_videofuncs.c | 41 +++-------------------
src/radeon.h | 3 +
src/radeon_chipinfo_gen.h | 23 +++++++++++-
src/radeon_chipset_gen.h | 23 +++++++++++-
src/radeon_dri2.c | 1
src/radeon_kms.c | 11 ++++-
src/radeon_output.c | 58 +++++++++++++++++++++++++++++++
src/radeon_pci_chipset_gen.h | 23 +++++++++++-
src/radeon_pci_device_match_gen.h | 23 +++++++++++-
src/radeon_video.c | 31 ++++++++++++++++
21 files changed, 327 insertions(+), 209 deletions(-)
New commits:
commit 7236d2d52cf2d9332e4f8681b7c9d060e7208414
Author: Julien Cristau <jcristau@debian.org>
Date: Sat Jan 12 16:30:24 2013 +0100
Add changelog entry
diff --git a/debian/changelog b/debian/changelog
index 41a4aec..c39cd64 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,25 @@
+xserver-xorg-video-ati (1:6.14.4-6) unstable; urgency=low
+
+ * Update to 6.14.6, minus the Xserver 1.13 compat patches:
+ - r6xx-r9xx: force 1D tiling for buffer with height < 64
+ - Make radeon_setup_kernel_mem failures more graceful and verbose
+ - RADEONCopySwap: Fix RADEON_HOST_DATA_SWAP_16BIT case
+ - radeon: add MacModel entry for SAM440ep embedded board
+ - Fail more gracefully when drm surface manager can't be initialized
+ - radeon: avoid rounding errors in texture coords for textured xv on EG+
+ - radeon: use GB_GR and BG_RG formats for packed yuv video for r600+
+ - radeon: fix smooth startup with tiling enabled
+ - radeon: improve smooth startup fallbacks
+ - radeon: add new PCI ids
+ - Don't wait on a CRTC which has been disabled via DPMS
+ - Don't page-flip or wait on a CRTC while we're VT-switched away
+ - configure: bump libdrm_radeon requirement
+ - UMS: Fix CRTC DPMS state check
+ - Fix up displayWidth vs. virtualX confusion in radeon_setup_kernel_mem()
+ - radeon: require libdrm 2.4.36 for KMS support
+
+ -- Julien Cristau <jcristau@debian.org> Sat, 12 Jan 2013 16:30:01 +0100
+
xserver-xorg-video-ati (1:6.14.4-5) unstable; urgency=low
* Update radeon's long description to list the chips mentioned in the
commit 3656a238a1f18e733d02dea67aca0881fb2ea71e
Author: Dave Airlie <airlied@redhat.com>
Date: Fri Jun 29 14:46:17 2012 +0100
radeon: require libdrm 2.4.36 for KMS support.
This is due to some commits to the surface manager that fix bugs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 72fea2635a56c4f572c07fc50fc58f703a21eb4f)
diff --git a/configure.ac b/configure.ac
index 695a574..0fa2141 100644
--- a/configure.ac
+++ b/configure.ac
@@ -141,7 +141,7 @@ if test "$DRI" = yes; then
AC_CHECK_HEADER(xf86drmMode.h,[DRM_MODE=yes],[DRM_MODE=no],[#include <stdint.h>
#include <stdlib.h>])
if test "x$DRM_MODE" = xyes; then
- PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.35 libdrm_radeon],
+ PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.36 libdrm_radeon],
[LIBDRM_RADEON=yes], [LIBDRM_RADEON=no])
if test "x$LIBDRM_RADEON" = xyes; then
commit 470543df6ba8b8b8b8cca4adb1b9043765905eb5
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Jun 27 19:26:51 2012 +0200
Fix up displayWidth vs. virtualX confusion in radeon_setup_kernel_mem().
It was using the pitch (displayWidth) for the virtual width (virtualX). This
prevented using page flipping in some cases, as displayWidth was already
overaligned for virtualX, so the DRI2 front and back buffers ended up having
a different pitch.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
(cherry picked from commit 179b035835bfa99283d44ba2d5ee17e686196535)
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index ae4953e..73930b9 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1252,7 +1252,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
} else
tiling_flags |= RADEON_TILING_MACRO;
}
- pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
+ pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
if (info->ChipFamily >= CHIP_FAMILY_R600) {
@@ -1262,7 +1262,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
return FALSE;
}
memset(&surface, 0, sizeof(struct radeon_surface));
- surface.npix_x = pScrn->displayWidth;
+ surface.npix_x = pScrn->virtualX;
surface.npix_y = pScrn->virtualY;
surface.npix_z = 1;
surface.blk_w = 1;
@@ -1367,6 +1367,8 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
}
+ info->CurrentLayout.displayWidth = pScrn->displayWidth = pitch / cpp;
+
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024);
radeon_kms_update_vram_limit(pScrn, screen_size);
return TRUE;
commit 6fd0f198896cb8ef1f58b9c2ca425b5d9b22c8be
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Fri Jun 8 12:18:48 2012 +0200
UMS: Fix CRTC DPMS state check.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 248e912c487636d7352cfad43c03fc9f19fc2215)
diff --git a/src/radeon_video.c b/src/radeon_video.c
index dfdf2cf..5f640a9 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -143,6 +143,22 @@ radeon_box_area(BoxPtr box)
return (int) (box->x2 - box->x1) * (int) (box->y2 - box->y1);
}
+static Bool
+radeon_crtc_is_enabled(xf86CrtcPtr crtc)
+{
+ RADEONCrtcPrivatePtr radeon_crtc;
+
+#ifdef XF86DRM_MODE
+ if (RADEONPTR(crtc->scrn)->cs) {
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+ return drmmode_crtc->dpms_mode == DPMSModeOn;
+ }
+#endif
+
+ radeon_crtc = crtc->driver_private;
+ return radeon_crtc->enabled;
+}
+
xf86CrtcPtr
radeon_pick_best_crtc(ScrnInfoPtr pScrn,
int x1, int x2, int y1, int y2)
@@ -171,9 +187,8 @@ radeon_pick_best_crtc(ScrnInfoPtr pScrn,
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
- drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
- if (drmmode_crtc->dpms_mode == DPMSModeOff)
+ if (!radeon_crtc_is_enabled(crtc))
continue;
radeon_crtc_box(crtc, &crtc_box);
commit a5f7246e687c89ef557b54740f5d91e03efc7295
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Thu Jun 7 11:23:31 2012 -0400
configure: bump libdrm_radeon requirement
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
(cherry picked from commit f1693ee09e9b251eb75e3e5fe0ee7699fec6fb98)
diff --git a/configure.ac b/configure.ac
index 363e1d4..695a574 100644
--- a/configure.ac
+++ b/configure.ac
@@ -141,7 +141,7 @@ if test "$DRI" = yes; then
AC_CHECK_HEADER(xf86drmMode.h,[DRM_MODE=yes],[DRM_MODE=no],[#include <stdint.h>
#include <stdlib.h>])
if test "x$DRM_MODE" = xyes; then
- PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.33 libdrm_radeon],
+ PKG_CHECK_MODULES(LIBDRM_RADEON, [xorg-server >= 1.6.2 libdrm >= 2.4.35 libdrm_radeon],
[LIBDRM_RADEON=yes], [LIBDRM_RADEON=no])
if test "x$LIBDRM_RADEON" = xyes; then
commit 5754d021378f273d4f981617cc36b646c2d40be5
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Jun 6 12:29:37 2012 +0200
Don't page-flip or wait on a CRTC while we're VT-switched away.
We don't know what the CRTC state is.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 77a056c1725c9c44a328ed324687bdf35144e9e2)
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 8bd3f66..eef6c7a 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -744,6 +744,7 @@ can_flip(ScrnInfoPtr pScrn, DrawablePtr draw,
{
return draw->type == DRAWABLE_WINDOW &&
RADEONPTR(pScrn)->allowPageFlip &&
+ pScrn->vtSema &&
DRI2CanFlip(draw) &&
can_exchange(pScrn, draw, front, back);
}
diff --git a/src/radeon_video.c b/src/radeon_video.c
index a9daebd..dfdf2cf 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -153,6 +153,9 @@ radeon_pick_best_crtc(ScrnInfoPtr pScrn,
RROutputPtr primary_output = NULL;
xf86CrtcPtr best_crtc = NULL, primary_crtc = NULL;
+ if (!pScrn->vtSema)
+ return NULL;
+
box.x1 = x1;
box.x2 = x2;
box.y1 = y1;
commit 836031f438febea15718c211d7a374c513c33eb5
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Jun 6 12:16:08 2012 +0200
Don't wait on a CRTC which has been disabled via DPMS (bug #49761).
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=49761 .
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 1d9f1eb7e65c57c52759ccbfa51e8bdd5a10acac)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 81f60dc..93c7876 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -179,11 +179,12 @@ drmmode_ConvertToKMode(ScrnInfoPtr scrn,
static void
drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
-#if 0
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
-// drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
// drmmode_ptr drmmode = drmmode_crtc->drmmode;
+ drmmode_crtc->dpms_mode = mode;
+
+#if 0
/* bonghits in the randr 1.2 - uses dpms to disable crtc - bad buzz */
if (mode == DPMSModeOff) {
// drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id,
diff --git a/src/drmmode_display.h b/src/drmmode_display.h
index dff0392..14cf9d3 100644
--- a/src/drmmode_display.h
+++ b/src/drmmode_display.h
@@ -73,6 +73,7 @@ typedef struct {
struct radeon_bo *cursor_bo;
struct radeon_bo *rotate_bo;
unsigned rotate_fb_id;
+ int dpms_mode;
uint16_t lut_r[256], lut_g[256], lut_b[256];
} drmmode_crtc_private_rec, *drmmode_crtc_private_ptr;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 0e2c127..a9daebd 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -19,6 +19,14 @@
#include "atipciids.h"
#include "xf86fbman.h"
+/* DPMS */
+#ifdef HAVE_XEXTPROTO_71
+#include <X11/extensions/dpmsconst.h>
+#else
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+#endif
+
#include <X11/extensions/Xv.h>
#include "fourcc.h"
@@ -160,6 +168,11 @@ radeon_pick_best_crtc(ScrnInfoPtr pScrn,
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+ if (drmmode_crtc->dpms_mode == DPMSModeOff)
+ continue;
+
radeon_crtc_box(crtc, &crtc_box);
radeon_box_intersect(&cover_box, &crtc_box, &box);
coverage = radeon_box_area(&cover_box);
commit c043e61b767df11b3fa158fba7899db569b1942b
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Jun 5 09:48:59 2012 -0400
radeon: add new PCI ids
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
(cherry picked from commit 4603285aa8efaf2614f15a38254465cec2075f11)
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 77e41ac..b08ad88 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -460,6 +460,7 @@
#define PCI_CHIP_SUMO2_9645 0x9645
#define PCI_CHIP_SUMO_9647 0x9647
#define PCI_CHIP_SUMO_9648 0x9648
+#define PCI_CHIP_SUMO_9649 0x9649
#define PCI_CHIP_SUMO_964A 0x964A
#define PCI_CHIP_SUMO_964B 0x964B
#define PCI_CHIP_SUMO_964C 0x964C
@@ -479,6 +480,7 @@
#define PCI_CHIP_PALM_9807 0x9807
#define PCI_CHIP_PALM_9808 0x9808
#define PCI_CHIP_PALM_9809 0x9809
+#define PCI_CHIP_PALM_980A 0x980A
#define PCI_CHIP_CYPRESS_6880 0x6880
#define PCI_CHIP_CYPRESS_6888 0x6888
#define PCI_CHIP_CYPRESS_6889 0x6889
@@ -560,6 +562,7 @@
#define PCI_CHIP_TURKS_6747 0x6747
#define PCI_CHIP_TURKS_6748 0x6748
#define PCI_CHIP_TURKS_6749 0x6749
+#define PCI_CHIP_TURKS_674A 0x674A
#define PCI_CHIP_TURKS_6750 0x6750
#define PCI_CHIP_TURKS_6751 0x6751
#define PCI_CHIP_TURKS_6758 0x6758
@@ -585,6 +588,7 @@
#define PCI_CHIP_CAICOS_6767 0x6767
#define PCI_CHIP_CAICOS_6768 0x6768
#define PCI_CHIP_CAICOS_6770 0x6770
+#define PCI_CHIP_CAICOS_6771 0x6771
#define PCI_CHIP_CAICOS_6772 0x6772
#define PCI_CHIP_CAICOS_6778 0x6778
#define PCI_CHIP_CAICOS_6779 0x6779
@@ -593,6 +597,23 @@
#define PCI_CHIP_ARUBA_9901 0x9901
#define PCI_CHIP_ARUBA_9903 0x9903
#define PCI_CHIP_ARUBA_9904 0x9904
-#define PCI_CHIP_ARUBA_990f 0x990f
+#define PCI_CHIP_ARUBA_9905 0x9905
+#define PCI_CHIP_ARUBA_9906 0x9906
+#define PCI_CHIP_ARUBA_9907 0x9907
+#define PCI_CHIP_ARUBA_9908 0x9908
+#define PCI_CHIP_ARUBA_9909 0x9909
+#define PCI_CHIP_ARUBA_990A 0x990A
+#define PCI_CHIP_ARUBA_990F 0x990F
+#define PCI_CHIP_ARUBA_9910 0x9910
+#define PCI_CHIP_ARUBA_9913 0x9913
+#define PCI_CHIP_ARUBA_9917 0x9917
+#define PCI_CHIP_ARUBA_9918 0x9918
+#define PCI_CHIP_ARUBA_9919 0x9919
#define PCI_CHIP_ARUBA_9990 0x9990
#define PCI_CHIP_ARUBA_9991 0x9991
+#define PCI_CHIP_ARUBA_9992 0x9992
+#define PCI_CHIP_ARUBA_9993 0x9993
+#define PCI_CHIP_ARUBA_9994 0x9994
+#define PCI_CHIP_ARUBA_99A0 0x99A0
+#define PCI_CHIP_ARUBA_99A2 0x99A2
+#define PCI_CHIP_ARUBA_99A4 0x99A4
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 3376438..501a0f6 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -461,6 +461,7 @@
"0x9645","SUMO2_9645","SUMO2",1,1,,,1,"SUMO2"
"0x9647","SUMO_9647","SUMO",1,1,,,1,"SUMO"
"0x9648","SUMO_9648","SUMO",1,1,,,1,"SUMO"
+"0x9649","SUMO_9649","SUMO",1,1,,,1,"SUMO"
"0x964A","SUMO_964A","SUMO",,1,,,1,"SUMO"
"0x964B","SUMO_964B","SUMO",,1,,,1,"SUMO"
"0x964C","SUMO_964C","SUMO",,1,,,1,"SUMO"
@@ -480,6 +481,7 @@
"0x9807","PALM_9807","PALM",,1,,,1,"AMD Radeon HD 6200 Series Graphics"
"0x9808","PALM_9808","PALM",,1,,,1,"PALM"
"0x9809","PALM_9809","PALM",,1,,,1,"PALM"
+"0x980A","PALM_980A","PALM",,1,,,1,"PALM"
"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
@@ -561,6 +563,7 @@
"0x6747","TURKS_6747","TURKS",,,,,,"TURKS"
"0x6748","TURKS_6748","TURKS",,,,,,"TURKS"
"0x6749","TURKS_6749","TURKS",,,,,,"TURKS"
+"0x674A","TURKS_674A","TURKS",,,,,,"TURKS"
"0x6750","TURKS_6750","TURKS",,,,,,"TURKS"
"0x6751","TURKS_6751","TURKS",,,,,,"TURKS"
"0x6758","TURKS_6758","TURKS",,,,,,"TURKS"
@@ -586,6 +589,7 @@
"0x6767","CAICOS_6767","CAICOS",,,,,,"CAICOS"
"0x6768","CAICOS_6768","CAICOS",,,,,,"CAICOS"
"0x6770","CAICOS_6770","CAICOS",,,,,,"CAICOS"
+"0x6771","CAICOS_6771","CAICOS",,,,,,"CAICOS"
"0x6772","CAICOS_6772","CAICOS",,,,,,"CAICOS"
"0x6778","CAICOS_6778","CAICOS",,,,,,"CAICOS"
"0x6779","CAICOS_6779","CAICOS",,,,,,"CAICOS"
@@ -594,6 +598,23 @@
"0x9901","ARUBA_9901","ARUBA",,,,,,"ARUBA"
"0x9903","ARUBA_9903","ARUBA",1,,,,,"ARUBA"
"0x9904","ARUBA_9904","ARUBA",,,,,,"ARUBA"
-"0x990f","ARUBA_990f","ARUBA",,,,,,"ARUBA"
+"0x9905","ARUBA_9905","ARUBA",,,,,,"ARUBA"
+"0x9906","ARUBA_9906","ARUBA",,,,,,"ARUBA"
+"0x9907","ARUBA_9907","ARUBA",1,,,,,"ARUBA"
+"0x9908","ARUBA_9908","ARUBA",1,,,,,"ARUBA"
+"0x9909","ARUBA_9909","ARUBA",1,,,,,"ARUBA"
+"0x990A","ARUBA_990A","ARUBA",1,,,,,"ARUBA"
+"0x990F","ARUBA_990F","ARUBA",,,,,,"ARUBA"
+"0x9910","ARUBA_9910","ARUBA",1,,,,,"ARUBA"
+"0x9913","ARUBA_9913","ARUBA",1,,,,,"ARUBA"
+"0x9917","ARUBA_9917","ARUBA",,,,,,"ARUBA"
+"0x9918","ARUBA_9918","ARUBA",,,,,,"ARUBA"
+"0x9919","ARUBA_9919","ARUBA",,,,,,"ARUBA"
"0x9990","ARUBA_9990","ARUBA",1,,,,,"ARUBA"
"0x9991","ARUBA_9991","ARUBA",,,,,,"ARUBA"
+"0x9992","ARUBA_9992","ARUBA",1,,,,,"ARUBA"
+"0x9993","ARUBA_9993","ARUBA",,,,,,"ARUBA"
+"0x9994","ARUBA_9994","ARUBA",1,,,,,"ARUBA"
+"0x99A0","ARUBA_99A0","ARUBA",1,,,,,"ARUBA"
+"0x99A2","ARUBA_99A2","ARUBA",1,,,,,"ARUBA"
+"0x99A4","ARUBA_99A4","ARUBA",,,,,,"ARUBA"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index a578825..c64c921 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -380,6 +380,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9645, CHIP_FAMILY_SUMO2, 1, 1, 0, 0, 1 },
{ 0x9647, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x9648, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
+ { 0x9649, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x964A, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
{ 0x964B, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
{ 0x964C, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
@@ -399,6 +400,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9807, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x9808, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x9809, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x980A, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
{ 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
{ 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
@@ -480,6 +482,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x6747, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6748, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6749, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x674A, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6750, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6751, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6758, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
@@ -505,6 +508,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x6767, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6768, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6770, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6771, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6772, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6778, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6779, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
@@ -513,7 +517,24 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9901, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
{ 0x9903, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
{ 0x9904, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
- { 0x990f, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9905, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9906, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9907, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9908, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9909, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x990A, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x990F, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9910, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9913, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9917, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9918, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9919, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
{ 0x9990, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
{ 0x9991, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9992, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9993, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9994, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x99A0, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x99A2, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x99A4, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index e7f7379..d2f61a0 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -380,6 +380,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_SUMO2_9645, "SUMO2" },
{ PCI_CHIP_SUMO_9647, "SUMO" },
{ PCI_CHIP_SUMO_9648, "SUMO" },
+ { PCI_CHIP_SUMO_9649, "SUMO" },
{ PCI_CHIP_SUMO_964A, "SUMO" },
{ PCI_CHIP_SUMO_964B, "SUMO" },
{ PCI_CHIP_SUMO_964C, "SUMO" },
@@ -399,6 +400,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_PALM_9807, "AMD Radeon HD 6200 Series Graphics" },
{ PCI_CHIP_PALM_9808, "PALM" },
{ PCI_CHIP_PALM_9809, "PALM" },
+ { PCI_CHIP_PALM_980A, "PALM" },
{ PCI_CHIP_CYPRESS_6880, "CYPRESS" },
{ PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
{ PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
@@ -480,6 +482,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_TURKS_6747, "TURKS" },
{ PCI_CHIP_TURKS_6748, "TURKS" },
{ PCI_CHIP_TURKS_6749, "TURKS" },
+ { PCI_CHIP_TURKS_674A, "TURKS" },
{ PCI_CHIP_TURKS_6750, "TURKS" },
{ PCI_CHIP_TURKS_6751, "TURKS" },
{ PCI_CHIP_TURKS_6758, "TURKS" },
@@ -505,6 +508,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_CAICOS_6767, "CAICOS" },
{ PCI_CHIP_CAICOS_6768, "CAICOS" },
{ PCI_CHIP_CAICOS_6770, "CAICOS" },
+ { PCI_CHIP_CAICOS_6771, "CAICOS" },
{ PCI_CHIP_CAICOS_6772, "CAICOS" },
{ PCI_CHIP_CAICOS_6778, "CAICOS" },
{ PCI_CHIP_CAICOS_6779, "CAICOS" },
@@ -513,8 +517,25 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_ARUBA_9901, "ARUBA" },
{ PCI_CHIP_ARUBA_9903, "ARUBA" },
{ PCI_CHIP_ARUBA_9904, "ARUBA" },
- { PCI_CHIP_ARUBA_990f, "ARUBA" },
+ { PCI_CHIP_ARUBA_9905, "ARUBA" },
+ { PCI_CHIP_ARUBA_9906, "ARUBA" },
+ { PCI_CHIP_ARUBA_9907, "ARUBA" },
+ { PCI_CHIP_ARUBA_9908, "ARUBA" },
+ { PCI_CHIP_ARUBA_9909, "ARUBA" },
+ { PCI_CHIP_ARUBA_990A, "ARUBA" },
+ { PCI_CHIP_ARUBA_990F, "ARUBA" },
+ { PCI_CHIP_ARUBA_9910, "ARUBA" },
+ { PCI_CHIP_ARUBA_9913, "ARUBA" },
+ { PCI_CHIP_ARUBA_9917, "ARUBA" },
+ { PCI_CHIP_ARUBA_9918, "ARUBA" },
+ { PCI_CHIP_ARUBA_9919, "ARUBA" },
{ PCI_CHIP_ARUBA_9990, "ARUBA" },
{ PCI_CHIP_ARUBA_9991, "ARUBA" },
+ { PCI_CHIP_ARUBA_9992, "ARUBA" },
+ { PCI_CHIP_ARUBA_9993, "ARUBA" },
+ { PCI_CHIP_ARUBA_9994, "ARUBA" },
+ { PCI_CHIP_ARUBA_99A0, "ARUBA" },
+ { PCI_CHIP_ARUBA_99A2, "ARUBA" },
+ { PCI_CHIP_ARUBA_99A4, "ARUBA" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index aef8d89..dbf0728 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -380,6 +380,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_SUMO2_9645, PCI_CHIP_SUMO2_9645, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_9647, PCI_CHIP_SUMO_9647, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_9648, PCI_CHIP_SUMO_9648, RES_SHARED_VGA },
+ { PCI_CHIP_SUMO_9649, PCI_CHIP_SUMO_9649, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964A, PCI_CHIP_SUMO_964A, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964B, PCI_CHIP_SUMO_964B, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964C, PCI_CHIP_SUMO_964C, RES_SHARED_VGA },
@@ -399,6 +400,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_PALM_9807, PCI_CHIP_PALM_9807, RES_SHARED_VGA },
{ PCI_CHIP_PALM_9808, PCI_CHIP_PALM_9808, RES_SHARED_VGA },
{ PCI_CHIP_PALM_9809, PCI_CHIP_PALM_9809, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_980A, PCI_CHIP_PALM_980A, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
@@ -480,6 +482,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_TURKS_6747, PCI_CHIP_TURKS_6747, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6748, PCI_CHIP_TURKS_6748, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6749, PCI_CHIP_TURKS_6749, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_674A, PCI_CHIP_TURKS_674A, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6750, PCI_CHIP_TURKS_6750, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6751, PCI_CHIP_TURKS_6751, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6758, PCI_CHIP_TURKS_6758, RES_SHARED_VGA },
@@ -505,6 +508,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_CAICOS_6767, PCI_CHIP_CAICOS_6767, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6768, PCI_CHIP_CAICOS_6768, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6770, PCI_CHIP_CAICOS_6770, RES_SHARED_VGA },
+ { PCI_CHIP_CAICOS_6771, PCI_CHIP_CAICOS_6771, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6772, PCI_CHIP_CAICOS_6772, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6778, PCI_CHIP_CAICOS_6778, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6779, PCI_CHIP_CAICOS_6779, RES_SHARED_VGA },
@@ -513,8 +517,25 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_ARUBA_9901, PCI_CHIP_ARUBA_9901, RES_SHARED_VGA },
{ PCI_CHIP_ARUBA_9903, PCI_CHIP_ARUBA_9903, RES_SHARED_VGA },
{ PCI_CHIP_ARUBA_9904, PCI_CHIP_ARUBA_9904, RES_SHARED_VGA },
- { PCI_CHIP_ARUBA_990f, PCI_CHIP_ARUBA_990f, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9905, PCI_CHIP_ARUBA_9905, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9906, PCI_CHIP_ARUBA_9906, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9907, PCI_CHIP_ARUBA_9907, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9908, PCI_CHIP_ARUBA_9908, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9909, PCI_CHIP_ARUBA_9909, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_990A, PCI_CHIP_ARUBA_990A, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_990F, PCI_CHIP_ARUBA_990F, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9910, PCI_CHIP_ARUBA_9910, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9913, PCI_CHIP_ARUBA_9913, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9917, PCI_CHIP_ARUBA_9917, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9918, PCI_CHIP_ARUBA_9918, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9919, PCI_CHIP_ARUBA_9919, RES_SHARED_VGA },
{ PCI_CHIP_ARUBA_9990, PCI_CHIP_ARUBA_9990, RES_SHARED_VGA },
{ PCI_CHIP_ARUBA_9991, PCI_CHIP_ARUBA_9991, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9992, PCI_CHIP_ARUBA_9992, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9993, PCI_CHIP_ARUBA_9993, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9994, PCI_CHIP_ARUBA_9994, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_99A0, PCI_CHIP_ARUBA_99A0, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_99A2, PCI_CHIP_ARUBA_99A2, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_99A4, PCI_CHIP_ARUBA_99A4, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 681a6b8..a6663e0 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -380,6 +380,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_SUMO2_9645, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9647, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9648, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9649, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964C, 0 ),
@@ -399,6 +400,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9807, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9808, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9809, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_980A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
@@ -480,6 +482,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6747, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6748, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6749, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_674A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6750, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6751, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6758, 0 ),
@@ -505,6 +508,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6767, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6768, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6770, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6771, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6772, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6778, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6779, 0 ),
@@ -513,8 +517,25 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9901, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9903, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9904, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990f, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9905, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9906, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9907, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9908, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9909, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990F, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9910, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9913, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9917, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9918, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9919, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9990, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9991, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9992, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9993, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9994, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A2, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_99A4, 0 ),
{ 0, 0, 0 }
};
commit 1bacbf62a18b225b42229dcdd8f26b950c052b2f
Author: Dave Airlie <airlied@redhat.com>
Date: Sat Jun 2 17:16:34 2012 +0100
radeon: improve smooth startup fallbacks.
If we can't handover the framebuffer, memset it to black.
mostly ported from nouveau.
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 9307609420b4b209767d2057b4803bcb16cc1455)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 2e61260..81f60dc 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -194,42 +194,41 @@ drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode)
static PixmapPtr
create_pixmap_for_fbcon(drmmode_ptr drmmode,
- ScrnInfoPtr pScrn, int crtc_id)
+ ScrnInfoPtr pScrn, int fbcon_id)
{
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- drmmode_crtc_private_ptr drmmode_crtc;
- PixmapPtr pixmap;
+ PixmapPtr pixmap = NULL;
struct radeon_bo *bo;
drmModeFBPtr fbcon;
struct drm_gem_flink flink;
- drmmode_crtc = xf86_config->crtc[crtc_id]->driver_private;
-
- fbcon = drmModeGetFB(drmmode->fd, drmmode_crtc->mode_crtc->buffer_id);
+ fbcon = drmModeGetFB(drmmode->fd, fbcon_id);
if (fbcon == NULL)
return NULL;
+ if (fbcon->depth != pScrn->depth ||
+ fbcon->width != pScrn->virtualX ||
+ fbcon->height != pScrn->virtualY)
+ goto out_free_fb;
+
flink.handle = fbcon->handle;
if (ioctl(drmmode->fd, DRM_IOCTL_GEM_FLINK, &flink) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Couldn't flink fbcon handle\n");
- return NULL;
+ goto out_free_fb;
}
bo = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
if (bo == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Couldn't allocate bo for fbcon handle\n");
- return NULL;
+ goto out_free_fb;
}
pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height,
fbcon->depth, fbcon->bpp,
fbcon->pitch, 0, bo, NULL);
- if (!pixmap)
- return NULL;
-
radeon_bo_unref(bo);
+out_free_fb:
drmModeFreeFB(fbcon);
return pixmap;
}
@@ -240,27 +239,28 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr src, dst;
ScreenPtr pScreen = pScrn->pScreen;
- int crtc_id = 0;
+ int fbcon_id = 0;
int i;
int pitch;
uint32_t tiling_flags = 0;
Bool ret;
if (info->accelOn == FALSE)
- return;
+ goto fallback;
for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
- drmmode_crtc_private_ptr drmmode_crtc;
+ drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[i]->driver_private;
- drmmode_crtc = crtc->driver_private;
if (drmmode_crtc->mode_crtc->buffer_id)
- crtc_id = i;
+ fbcon_id = drmmode_crtc->mode_crtc->buffer_id;
}
- src = create_pixmap_for_fbcon(drmmode, pScrn, crtc_id);
+ if (!fbcon_id)
+ goto fallback;
+
+ src = create_pixmap_for_fbcon(drmmode, pScrn, fbcon_id);
if (!src)
- return;
+ goto fallback;
if (info->allowColorTiling) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
@@ -299,7 +299,15 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
drmmode_destroy_bo_pixmap(dst);
out_free_src:
drmmode_destroy_bo_pixmap(src);
+ return;
+
+fallback:
+ /* map and memset the bo */
+ if (radeon_bo_map(info->front_bo, 1))
+ return;
+ memset(info->front_bo->ptr, 0x00, info->front_bo->size);
+ radeon_bo_unmap(info->front_bo);
}
static Bool
commit d0d0b5a9f458cdff96c6dc80f38b82da8574f6ca
Author: Dave Airlie <airlied@redhat.com>
Date: Sat Jun 2 17:14:14 2012 +0100
radeon: fix smooth startup with tiling enabled.
We need to use the surface we worked out when we allocated the front bo,
not work out a new surface from scratch.
This fixes smooth handover from plymouth to gdm on F17.
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 89a4c79a43a2b6963e41d7812e8fe5beedb556af)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 38f9940..2e61260 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -53,7 +53,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
int width, int height,
int depth, int bpp,
int pitch, int tiling,
- struct radeon_bo *bo)
+ struct radeon_bo *bo, struct radeon_surface *psurf)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
ScreenPtr pScreen = pScrn->pScreen;
@@ -73,7 +73,9 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
radeon_set_pixmap_bo(pixmap, bo);
if (info->ChipFamily >= CHIP_FAMILY_R600) {
surface = radeon_get_pixmap_surface(pixmap);
- if (surface) {
+ if (surface && psurf)
+ *surface = *psurf;
+ else if (surface) {
memset(surface, 0, sizeof(struct radeon_surface));
surface->npix_x = width;
surface->npix_y = height;
@@ -223,7 +225,7 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height,
fbcon->depth, fbcon->bpp,
- fbcon->pitch, 0, bo);
+ fbcon->pitch, 0, bo, NULL);
if (!pixmap)
return NULL;
@@ -278,7 +280,7 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
dst = drmmode_create_bo_pixmap(pScrn, pScrn->virtualX,
pScrn->virtualY, pScrn->depth,
pScrn->bitsPerPixel, pitch,
- tiling_flags, info->front_bo);
+ tiling_flags, info->front_bo, &info->front_surface);
if (!dst)
goto out_free_src;
@@ -551,7 +553,7 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
pScrn->depth,
pScrn->bitsPerPixel,
rotate_pitch,
- 0, drmmode_crtc->rotate_bo);
+ 0, drmmode_crtc->rotate_bo, NULL);
if (rotate_pixmap == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Couldn't allocate shadow pixmap for rotated CRTC\n");
commit 3fb694b308ebadd1b849836059b6b56bb19385f7
Author: Thierry Vignaud <thierry.vignaud@gmail.com>
Date: Wed May 16 14:43:53 2012 +0200
UMS/EXA: Add reminder for potential solid picture performance issue.
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
index 45222b5..7af8a52 100644
--- a/src/radeon_exa_shared.c
+++ b/src/radeon_exa_shared.c
@@ -157,6 +157,7 @@ PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid)
return NULL;
}
+ /* XXX: Big hammer... */
info->accel_state->exa->WaitMarker(pScreen, info->accel_state->exaSyncMarker);
memcpy(info->FB + exaGetPixmapOffset(pPix), &solid, 4);
commit 4b9bad959438725e4434e2aa4f142542d8dcc260
Author: Roland Scheidegger <rscheidegger_lists@hispeed.ch>
Date: Fri May 11 05:25:32 2012 +0200
radeon: use GB_GR and BG_RG formats for packed yuv video for r600+
Those formats were invented for exactly that purpose so use them.
This saves some code and also some hw resources (only need one
sampler instead of two for packed yuv).
Only tested on EG.
diff --git a/src/cayman_shader.c b/src/cayman_shader.c
index 01b612a..18e9f50 100644
--- a/src/cayman_shader.c
+++ b/src/cayman_shader.c
@@ -1338,7 +1338,7 @@ int cayman_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
- I_COUNT(2),
+ I_COUNT(1),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_TC),
BARRIER(1));
@@ -1365,8 +1365,8 @@ int cayman_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
shader[i++] = TEX_DWORD1(DST_GPR(1),
DST_REL(ABSOLUTE),
DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_MASK),
- DST_SEL_Z(SQ_SEL_MASK),
+ DST_SEL_Y(SQ_SEL_Y),
+ DST_SEL_Z(SQ_SEL_Z),
DST_SEL_W(SQ_SEL_1),
LOD_BIAS(0),
COORD_TYPE_X(TEX_NORMALIZED),
@@ -1382,36 +1382,6 @@ int cayman_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
SRC_SEL_Z(SQ_SEL_0),
SRC_SEL_W(SQ_SEL_1));
shader[i++] = TEX_DWORD_PAD;
- /* 34/35 */
- shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
- INST_MOD(0),
- FETCH_WHOLE_QUAD(0),
- RESOURCE_ID(1),
- SRC_GPR(0),
- SRC_REL(ABSOLUTE),
- ALT_CONST(0),
- RESOURCE_INDEX_MODE(SQ_CF_INDEX_NONE),
- SAMPLER_INDEX_MODE(SQ_CF_INDEX_NONE));
- shader[i++] = TEX_DWORD1(DST_GPR(1),
- DST_REL(ABSOLUTE),
- DST_SEL_X(SQ_SEL_MASK),
- DST_SEL_Y(SQ_SEL_X),
- DST_SEL_Z(SQ_SEL_Y),
- DST_SEL_W(SQ_SEL_MASK),
- LOD_BIAS(0),
- COORD_TYPE_X(TEX_NORMALIZED),
- COORD_TYPE_Y(TEX_NORMALIZED),
- COORD_TYPE_Z(TEX_NORMALIZED),
- COORD_TYPE_W(TEX_NORMALIZED));
- shader[i++] = TEX_DWORD2(OFFSET_X(0),
- OFFSET_Y(0),
- OFFSET_Z(0),
- SAMPLER_ID(1),
- SRC_SEL_X(SQ_SEL_X),
- SRC_SEL_Y(SQ_SEL_Y),
- SRC_SEL_Z(SQ_SEL_0),
- SRC_SEL_W(SQ_SEL_1));
- shader[i++] = TEX_DWORD_PAD;
return i;
}
diff --git a/src/evergreen_shader.c b/src/evergreen_shader.c
index bbdd7a7..a6faba0 100644
--- a/src/evergreen_shader.c
+++ b/src/evergreen_shader.c
@@ -1306,7 +1306,7 @@ int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
- I_COUNT(2),
+ I_COUNT(1),
VALID_PIXEL_MODE(0),
END_OF_PROGRAM(0),
CF_INST(SQ_CF_INST_TC),
@@ -1337,8 +1337,8 @@ int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
shader[i++] = TEX_DWORD1(DST_GPR(1),
DST_REL(ABSOLUTE),
DST_SEL_X(SQ_SEL_X),
- DST_SEL_Y(SQ_SEL_MASK),
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