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libdrm: Changes to 'ubuntu'



 ChangeLog                                                    |  557 +++
 configure.ac                                                 |   22 
 debian/changelog                                             |   25 
 debian/libdrm-intel1.symbols                                 |    4 
 debian/libdrm-radeon1.symbols                                |    4 
 debian/libdrm2.symbols                                       |    1 
 debian/patches/100-revert-intel-fix-build-of-intel-drm.patch |   28 
 debian/patches/101-revert-dont-build-intel-drm.patch         |   30 
 debian/patches/series                                        |    4 
 debian/rules                                                 |    6 
 include/drm/drm_fourcc.h                                     |    6 
 include/drm/i915_drm.h                                       |   37 
 include/drm/radeon_drm.h                                     |   24 
 intel/Makefile.am                                            |    3 
 intel/intel_aub.h                                            |  123 
 intel/intel_bufmgr.h                                         |   19 
 intel/intel_bufmgr_gem.c                                     |  532 +++
 intel/intel_decode.c                                         | 1708 ++++++-----
 intel/tests/gen7-2d-copy.batch                               |binary
 intel/tests/gen7-2d-copy.batch-ref.txt                       |   14 
 intel/tests/gen7-2d-copy.batch.sh                            |    1 
 intel/tests/gen7-3d.batch                                    |binary
 intel/tests/gen7-3d.batch-ref.txt                            | 1504 +--------
 radeon/Makefile.am                                           |    5 
 radeon/r600_pci_ids.h                                        |  271 +
 radeon/radeon_cs_space.c                                     |   15 
 radeon/radeon_surface.c                                      | 1007 ++++++
 radeon/radeon_surface.h                                      |  114 
 xf86drmMode.c                                                |   21 
 xf86drmMode.h                                                |    6 
 30 files changed, 3949 insertions(+), 2142 deletions(-)

New commits:
commit 05fa7aab66a25009b754b6a93def5aff582e6d18
Author: Robert Hooker <sarvatt@ubuntu.com>
Date:   Thu Mar 22 13:18:48 2012 -0400

    Add patch series allowing libdrm-intel1 to build on powerpc/armel until plymouth is updated.

diff --git a/debian/changelog b/debian/changelog
index b84d11c..f8127bd 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,14 @@
-libdrm (2.4.32-1ubuntu1) precise; urgency=low
+libdrm (2.4.32-1ubuntu1) UNRELEASED; urgency=low
 
   * Merge from Debian unstable, remaining changes:
     - debian/rules
     - debian/control:
       + Build libdrm-intel1 everywhere rather than just {i386,amd64}
         for Plymouth
+    - 100-revert-intel-fix-build-of-intel-drm.patch
+      101-revert-dont-build-intel-drm.patch
+      + Add patch series to reenable building libdrm-intel1 on !i386/amd64,
+        (drop when plymouth is updated to 0.8.4.)
 
  -- Robert Hooker <sarvatt@ubuntu.com>  Thu, 22 Mar 2012 13:10:48 -0400
 
diff --git a/debian/patches/100-revert-intel-fix-build-of-intel-drm.patch b/debian/patches/100-revert-intel-fix-build-of-intel-drm.patch
new file mode 100644
index 0000000..fb99a1f
--- /dev/null
+++ b/debian/patches/100-revert-intel-fix-build-of-intel-drm.patch
@@ -0,0 +1,28 @@
+From eeaba3a4430f711e3dfddb9210ade1038854f13d Mon Sep 17 00:00:00 2001
+From: Robert Hooker <sarvatt@ubuntu.com>
+Date: Thu, 22 Mar 2012 13:09:59 -0400
+Subject: [PATCH 1/2] Revert "intel: Fix build of Intel DRM on x86 systems"
+
+This reverts commit 82c6938d232327233caac743a07639ac91bceb7e.
+---
+ configure.ac |    4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/configure.ac b/configure.ac
+index ff2c840..38aae0d 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -246,8 +246,8 @@ if test "x$INTEL" != "xno" -o "x$RADEON" != "xno"; then
+ 
+     else
+            if test "x$INTEL" != "xno"; then
+-                   case $host_cpu in
+-                           i?86|x86_64) INTEL=yes ;;
++                   case $host_os in
++                           i?86-*|x86_64-*) INTEL=yes ;;
+                            *) INTEL=no ;;
+                    esac
+            fi
+-- 
+1.7.9.1
+
diff --git a/debian/patches/101-revert-dont-build-intel-drm.patch b/debian/patches/101-revert-dont-build-intel-drm.patch
new file mode 100644
index 0000000..d413194
--- /dev/null
+++ b/debian/patches/101-revert-dont-build-intel-drm.patch
@@ -0,0 +1,30 @@
+From 1e13e415ca07b27d0ab064ff1ed8b4dd022d2065 Mon Sep 17 00:00:00 2001
+From: Robert Hooker <sarvatt@ubuntu.com>
+Date: Thu, 22 Mar 2012 13:10:03 -0400
+Subject: [PATCH 2/2] Revert "Don't build Intel DRM if $CHOST is not i?86-* or
+ x86_64-*"
+
+This reverts commit efd6e81e2ba112105457887ae18a58dfa4bbc8ef.
+---
+ configure.ac |    5 +----
+ 1 files changed, 1 insertions(+), 4 deletions(-)
+
+diff --git a/configure.ac b/configure.ac
+index 38aae0d..f7f33c6 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -246,10 +246,7 @@ if test "x$INTEL" != "xno" -o "x$RADEON" != "xno"; then
+ 
+     else
+            if test "x$INTEL" != "xno"; then
+-                   case $host_os in
+-                           i?86-*|x86_64-*) INTEL=yes ;;
+-                           *) INTEL=no ;;
+-                   esac
++                   INTEL=yes
+            fi
+            if test "x$RADEON" != "xno"; then
+                    RADEON=yes
+-- 
+1.7.9.1
+
diff --git a/debian/patches/series b/debian/patches/series
index b1a73f8..e50ae1f 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1,3 +1,7 @@
 01_default_perms.diff
 02_build_libkms_against_in_tree_drm.diff
 03_build_against_librt.diff
+
+# Ubuntu specific, drop when plymouth doesn't require libdrm-intel on powerpc/arm
+100-revert-intel-fix-build-of-intel-drm.patch
+101-revert-dont-build-intel-drm.patch

commit c876b7a3b309704f8d526950c836ff6c2ea0ff12
Author: Robert Hooker <sarvatt@ubuntu.com>
Date:   Thu Mar 22 13:11:46 2012 -0400

    Bump changelog.

diff --git a/debian/changelog b/debian/changelog
index 7df2b00..b84d11c 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,13 @@
+libdrm (2.4.32-1ubuntu1) precise; urgency=low
+
+  * Merge from Debian unstable, remaining changes:
+    - debian/rules
+    - debian/control:
+      + Build libdrm-intel1 everywhere rather than just {i386,amd64}
+        for Plymouth
+
+ -- Robert Hooker <sarvatt@ubuntu.com>  Thu, 22 Mar 2012 13:10:48 -0400
+
 libdrm (2.4.32-1) unstable; urgency=low
 
   [ Robert Hooker ]

commit 7921097578a7d1688fc4d92cb2338b1463824c57
Author: Cyril Brulebois <kibi@debian.org>
Date:   Mon Mar 19 19:56:24 2012 +0000

    Upload to unstable.

diff --git a/debian/changelog b/debian/changelog
index 2371913..45ad062 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.32-1) UNRELEASED; urgency=low
+libdrm (2.4.32-1) unstable; urgency=low
 
   [ Robert Hooker ]
   * New upstream release (2.4.31).
@@ -9,7 +9,7 @@ libdrm (2.4.32-1) UNRELEASED; urgency=low
   * New upstream release (2.4.32).
   * Bump libdrm-intel1's symbols and shlibs accordingly.
 
- -- Cyril Brulebois <kibi@debian.org>  Mon, 19 Mar 2012 19:33:21 +0000
+ -- Cyril Brulebois <kibi@debian.org>  Mon, 19 Mar 2012 19:56:12 +0000
 
 libdrm (2.4.30-1) unstable; urgency=low
 

commit 7d6eca41f92c247e0be2b1562c833e6ef410977f
Author: Cyril Brulebois <kibi@debian.org>
Date:   Mon Mar 19 19:56:08 2012 +0000

    Bump libdrm-intel1's symbols and shlibs accordingly.

diff --git a/debian/changelog b/debian/changelog
index 7b7ed8d..2371913 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -7,6 +7,7 @@ libdrm (2.4.32-1) UNRELEASED; urgency=low
 
   [ Cyril Brulebois ]
   * New upstream release (2.4.32).
+  * Bump libdrm-intel1's symbols and shlibs accordingly.
 
  -- Cyril Brulebois <kibi@debian.org>  Mon, 19 Mar 2012 19:33:21 +0000
 
diff --git a/debian/libdrm-intel1.symbols b/debian/libdrm-intel1.symbols
index c4af4d2..a381740 100644
--- a/debian/libdrm-intel1.symbols
+++ b/debian/libdrm-intel1.symbols
@@ -36,7 +36,9 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
  drm_intel_bufmgr_fake_set_last_dispatch@Base 2.4.1
  drm_intel_bufmgr_gem_enable_fenced_relocs@Base 2.4.20
  drm_intel_bufmgr_gem_enable_reuse@Base 2.4.1
+ drm_intel_bufmgr_gem_get_devid@Base 2.4.32
  drm_intel_bufmgr_gem_init@Base 2.4.1
+ drm_intel_bufmgr_gem_set_aub_dump@Base 2.4.32
  drm_intel_bufmgr_gem_set_vma_cache_size@Base 2.4.29
  drm_intel_bufmgr_set_debug@Base 2.4.1
  drm_intel_decode@Base 2.4.30
@@ -46,9 +48,11 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
  drm_intel_decode_set_dump_past_end@Base 2.4.30
  drm_intel_decode_set_head_tail@Base 2.4.30
  drm_intel_decode_set_output_file@Base 2.4.30
+ drm_intel_gem_bo_aub_dump_bmp@Base 2.4.32
  drm_intel_gem_bo_clear_relocs@Base 2.4.27
  drm_intel_gem_bo_get_reloc_count@Base 2.4.27
  drm_intel_gem_bo_map_gtt@Base 2.4.3
+ drm_intel_gem_bo_map_unsynchronized@Base 2.4.32
  drm_intel_gem_bo_start_gtt_access@Base 2.4.3
  drm_intel_gem_bo_unmap_gtt@Base 2.4.9
  drm_intel_get_aperture_sizes@Base 2.4.26
diff --git a/debian/rules b/debian/rules
index 7857963..4c296ea 100755
--- a/debian/rules
+++ b/debian/rules
@@ -77,7 +77,7 @@ endif
 override_dh_makeshlibs:
 	dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.31)' -- -c4
 ifeq ($(INTEL), yes)
-	dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.30)' -- -c4
+	dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.32)' -- -c4
 endif
 ifeq ($(NOUVEAU), yes)
 	dh_makeshlibs -plibdrm-nouveau1a -V'libdrm-nouveau1a (>= 2.4.23)' -- -c4

commit 12ae11b0ca3895ec6dadd684cf57ce600f796786
Author: Cyril Brulebois <kibi@debian.org>
Date:   Mon Mar 19 19:33:53 2012 +0000

    Bump changelogs.

diff --git a/ChangeLog b/ChangeLog
index 4d5e8df..60b0b2d 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,251 @@
+commit 51c3e7d7335ecdf572968db7d3eed661e8a61810
+Author: Eric Anholt <eric@anholt.net>
+Date:   Fri Mar 16 16:11:10 2012 -0700
+
+    configure: Bump version for 2.4.32.
+
+commit 5de5b7484a3a41554e16c02a544a45db5516b031
+Author: Eric Anholt <eric@anholt.net>
+Date:   Tue Mar 13 16:49:53 2012 -0700
+
+    intel: Quiet two more valgrind complaints with recent changes.
+    
+    These are more cases where valgrind doesn't understand what gets read
+    or written by our ioctls.
+
+commit 9d18ad254afc2afc41a919b86cd51ea40cfd8f0b
+Author: Eric Anholt <eric@anholt.net>
+Date:   Fri Mar 2 10:27:55 2012 -0800
+
+    intel: Add per-dword decode of gen7 3DPRIMITIVE.
+
+commit 9b87fd9a3df8c59461bc90b4620526d10f9b5771
+Author: Eric Anholt <eric@anholt.net>
+Date:   Fri Mar 2 10:18:51 2012 -0800
+
+    intel: Move the gen4-6 3DPRIMITIVE handling out of the switch statement.
+
+commit 99c73378a1b440bcf594742445dfe14ab1e89128
+Author: Eric Anholt <eric@anholt.net>
+Date:   Fri Feb 10 04:12:15 2012 -0800
+
+    intel: Add support for (possibly) unsynchronized maps.
+    
+    This improves the performance of Mesa's GL_MAP_UNSYNCHRONIZED_BIT path
+    in GL_ARB_map_buffer_range.  Improves Unigine Tropics performance at
+    1024x768 by 2.30482% +/- 0.0492146% (n=61)
+    
+    v2: Fix comment grammar.
+    
+    Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 3a8884851b72af012a8cb2beea320f094a58e5eb
+Author: Eric Anholt <eric@anholt.net>
+Date:   Mon Feb 27 17:26:05 2012 -0800
+
+    intel: Fix error check for I915_PARAM_HAS_LLC.
+    
+    drmIoctl returns -1 on error with errno set to the error value.  Other
+    users of it in this file just check for != 0, and only use errno when
+    they need to send an error value on to the caller of the API.
+
+commit c9ce2edfc8d33e760667529250e86e93ff656c3d
+Author: Eric Anholt <eric@anholt.net>
+Date:   Fri Mar 9 16:08:23 2012 -0800
+
+    intel: Bump the copyright dates on the bufmgr files.
+    
+    We've been hacking these constantly.
+
+commit 4db16a9480af2c4f36eb8023193cd54545efbe54
+Author: Eric Anholt <eric@anholt.net>
+Date:   Tue Oct 11 15:59:03 2011 -0700
+
+    intel: Add .aub file output support.
+    
+    This will allow the driver to capture all of its execution state to a
+    file for later debugging.  intel_gpu_dump is limited in that it only
+    captures batchbuffers, and Mesa's captures, while more complete, still
+    capture only a portion of the state involved in execution.
+    
+    This is a squash commit of a long series of hacking as we tried to get
+    the resulting traces to work in the internal simulator.  It contains
+    contributions by Yuanhan Liu and Kenneth Graunke.
+    
+    v2: Drop the MI_FLUSH_ENABLE setup.
+    
+    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+    Signed-off-by: Eric Anholt <eric@anholt.net>
+    Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
+    Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
+
+commit 6e642db7f4a5628ed63ca3c479f06bd6f2ca3893
+Author: Kenneth Graunke <kenneth@whitecape.org>
+Date:   Tue Oct 11 14:38:34 2011 -0700
+
+    intel: Add support for overriding the PCI ID via an environment variable
+    
+    For example:
+    
+        export INTEL_DEVID_OVERRIDE=0x162
+    
+    If this variable is set, don't actually submit the batchbuffer to the
+    GPU, it probably contains commands for the wrong generation of hardware.
+    
+    v2: Introduce a getter for the overridden devid, and avoid getenv per exec.
+    
+    Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
+    Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
+    Signed-off-by: Eric Anholt <eric@anholt.net>
+
+commit fd39e61d0edfd30052d5f0b59b9215574e37942f
+Author: David Herrman <dh.herrmann@googlemail.com>
+Date:   Fri Mar 9 13:40:14 2012 -0500
+
+    xf86drmMode.h: Add header protection
+    
+    xf86drmMode.h is missing a header protection. xf86drm.h has one so just
+    copy it and adjust the name.
+    
+    Reviewed-by: Adam Jackson <ajax@redhat.com>
+    Signed-off-by: David Herrmann <dh.herrmann@googlemail.com>
+
+commit f82c77870354ba736774b6c45ccf8a326732243a
+Author: Alan Coopersmith <alan.coopersmith@oracle.com>
+Date:   Thu Feb 2 17:51:24 2012 -0800
+
+    Make drm/drm_fourcc.h portable to non-linux platforms
+    
+    Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
+
+commit be30d350b64c1a83473a9ffbedf8e2c680a65fcd
+Author: Matt Turner <mattst88@gmail.com>
+Date:   Thu Mar 1 12:19:59 2012 -0500
+
+    Don't require pciaccess if Intel is disabled
+    
+    Reviewed-by: Eric Anholt <eric@anholt.net>
+    Signed-off-by: Matt Turner <mattst88@gmail.com>
+
+commit 783db34f6d8aded019b005a957fed1b91fd67c7c
+Author: Eric Anholt <eric@anholt.net>
+Date:   Mon Jan 30 15:21:29 2012 -0800
+
+    intel: Import a new batchbuffer for the gen7 test.
+    
+    This one doesn't have the 3DSTATE_HIER_DEPTH_BUFFER bug that the
+    previous one did.
+    
+    Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit b395af0d2d617c29054f1b97973982bbffa33190
+Author: Eric Anholt <eric@anholt.net>
+Date:   Mon Jan 30 15:13:32 2012 -0800
+
+    intel: Add decode for gen7 HIER_DEPTH_BUFFER.
+    
+    Note that the regression test complains here: The batch that was
+    captured included a bug in its packet output, which was later fixed in
+    Mesa.
+    
+    Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit e6beaf8ee49dbf165ef2e005931fdf0ce323fcf6
+Author: Eric Anholt <eric@anholt.net>
+Date:   Mon Jan 30 15:04:10 2012 -0800
+
+    intel: Add decode for gen7 3DSTATE_WM.
+    
+    This requires pulling the gen6 3DSTATE_WM out to a function so it
+    doesn't override gen7's handler.
+    
+    v2: Fix pasteo in interpreting ZW interpolation (thanks danvet!).
+    
+    Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 259e7b61381551b65ad3b574817dbde2210ff188
+Author: Eric Anholt <eric@anholt.net>
+Date:   Fri Jan 27 13:27:56 2012 -0800
+
+    intel: Fix a typo in decode error message.
+    
+    Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 23eeb7e1e45417a5a84f826286dd982dba440cd3
+Author: Chris Wilson <chris@chris-wilson.co.uk>
+Date:   Thu Feb 9 10:29:22 2012 +0000
+
+    intel: Detect cache domain inconsistency with valgrind
+    
+    Every access to either the GTT or CPU pointer is supposed to be
+    proceeded by a set_domain ioctl so that GEM is able to manage the cache
+    domains correctly and for the following access to be coherent. Of
+    course, some people explicitly want incoherent, non-blocking access
+    which is going to trigger warnings by this patch but are probably better
+    served by explicit suppression.
+    
+    v2: Also mark the pointers as inaccessible following the explicit unmap
+    and implicit unmap upon return to the cache.
+    
+    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+    Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 9b3ad51ae5fd9654df8ef75de845a519015150bb
+Author: Jerome Glisse <jglisse@redhat.com>
+Date:   Mon Feb 13 20:45:53 2012 -0500
+
+    radeon: fix pitch alignment for scanout buffer
+    
+    Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit ced219ebbd3b266ac8326223bad62f994907ae6b
+Author: Chris Wilson <chris@chris-wilson.co.uk>
+Date:   Mon Feb 13 00:19:17 2012 +0000
+
+    configure: Fix pkg-config test in absence of valgrind
+    
+    The empty string used for the not case is replaced by the default
+    if-else clause and so causes the configure to fail in the absence of
+    valgrind. Which is not quite what was intended.
+    
+    Instead use the common idiom of setting a variable depending on whether
+    the true or false branch is taken and emit the conditional code as a
+    second step.
+    
+    Reported-by: Tobias Jakobi <liquid.acid@gmx.net>
+    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit 90b23cc24c19fbe131d84237c55311cafeb4ca21
+Author: Chris Wilson <chris@chris-wilson.co.uk>
+Date:   Thu Feb 9 10:23:10 2012 +0000
+
+    intel: Mark up with valgrind intrinsics to reduce false positives
+    
+    In particular, declare the hidden CPU mmaps to valgrind so that it knows
+    about those memory regions.
+    
+    v2: Add an additional VG_CLEAR for the getparam
+    
+    References: https://bugs.freedesktop.org/show_bug.cgi?id=35071
+    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+    Acked-by: Ben Widawsky <ben@bwidawsk.net>
+    [anholt: Ideally valgrind should just learn about the ioctls, and
+             removing the clear for the non-valgrindified code feels risky.]
+    Reviewed-by: Eric Anholt <eric@anholt.net>
+
+commit 2cfac57d364d0166ed9472b086c16aea376f495a
+Author: Michel Dänzer <michel.daenzer@amd.com>
+Date:   Wed Feb 8 10:49:08 2012 +0100
+
+    radeon_cs_setup_bo: Fix accounting if caller specified write and read domains.
+    
+    Only account for the write domain in that case.
+    
+    Fixes https://bugs.freedesktop.org/show_bug.cgi?id=43893 .
+    
+    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
 commit 230ec7d7bbf1e8a7e263d471b21afb08c28eba0c
 Author: Jerome Glisse <jglisse@redhat.com>
 Date:   Mon Feb 6 15:22:58 2012 -0500
diff --git a/debian/changelog b/debian/changelog
index 94e2d44..7b7ed8d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,14 @@
-libdrm (2.4.31-1) UNRELEASED; urgency=low
+libdrm (2.4.32-1) UNRELEASED; urgency=low
 
-  * New upstream release.
+  [ Robert Hooker ]
+  * New upstream release (2.4.31).
   * Bump libdrm2 and libdrm-radeon1 symbols and shlibs to account for
     recent changes.
 
- -- Robert Hooker <sarvatt@ubuntu.com>  Tue, 07 Feb 2012 11:06:32 -0500
+  [ Cyril Brulebois ]
+  * New upstream release (2.4.32).
+
+ -- Cyril Brulebois <kibi@debian.org>  Mon, 19 Mar 2012 19:33:21 +0000
 
 libdrm (2.4.30-1) unstable; urgency=low
 

commit 51c3e7d7335ecdf572968db7d3eed661e8a61810
Author: Eric Anholt <eric@anholt.net>
Date:   Fri Mar 16 16:11:10 2012 -0700

    configure: Bump version for 2.4.32.

diff --git a/configure.ac b/configure.ac
index 71a596c..ff2c840 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
 
 AC_PREREQ([2.63])
 AC_INIT([libdrm],
-        [2.4.31],
+        [2.4.32],
         [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
         [libdrm])
 

commit 5de5b7484a3a41554e16c02a544a45db5516b031
Author: Eric Anholt <eric@anholt.net>
Date:   Tue Mar 13 16:49:53 2012 -0700

    intel: Quiet two more valgrind complaints with recent changes.
    
    These are more cases where valgrind doesn't understand what gets read
    or written by our ioctls.

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 51b963f..3c91090 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2647,6 +2647,7 @@ get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
 		}
 	}
 
+	VG_CLEAR(devid);
 	VG_CLEAR(gp);
 	gp.param = I915_PARAM_CHIPSET_ID;
 	gp.value = &devid;
@@ -2790,6 +2791,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 		bufmgr_gem->gtt_size -= 256*1024*1024;
 	}
 
+	VG_CLEAR(gp);
 	gp.value = &tmp;
 
 	gp.param = I915_PARAM_HAS_EXECBUF2;

commit 9d18ad254afc2afc41a919b86cd51ea40cfd8f0b
Author: Eric Anholt <eric@anholt.net>
Date:   Fri Mar 2 10:27:55 2012 -0800

    intel: Add per-dword decode of gen7 3DPRIMITIVE.

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index af621d4..df9b704 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -2577,10 +2577,8 @@ static const char *get_965_element_component(uint32_t data, int component)
 	}
 }
 
-static const char *get_965_prim_type(uint32_t data)
+static const char *get_965_prim_type(uint32_t primtype)
 {
-	uint32_t primtype = (data >> 10) & 0x1f;
-
 	switch (primtype) {
 	case 0x01:
 		return "point list";
@@ -3009,7 +3007,7 @@ gen4_3DPRIMITIVE(struct drm_intel_decode *ctx)
 {
 	instr_out(ctx, 0,
 		  "3DPRIMITIVE: %s %s\n",
-		  get_965_prim_type(ctx->data[0]),
+		  get_965_prim_type((ctx->data[0] >> 10) & 0x1f),
 		  (ctx->data[0] & (1 << 15)) ? "random" : "sequential");
 	instr_out(ctx, 1, "vertex count\n");
 	instr_out(ctx, 2, "start vertex\n");
@@ -3021,6 +3019,27 @@ gen4_3DPRIMITIVE(struct drm_intel_decode *ctx)
 }
 
 static int
+gen7_3DPRIMITIVE(struct drm_intel_decode *ctx)
+{
+	bool indirect = !!(ctx->data[0] & (1 << 10));
+
+	instr_out(ctx, 0,
+		  "3DPRIMITIVE: %s%s\n",
+		  indirect ? " indirect" : "",
+		  (ctx->data[0] & (1 << 8)) ? " predicated" : "");
+	instr_out(ctx, 1, "%s %s\n",
+		  get_965_prim_type(ctx->data[1] & 0x3f),
+		  (ctx->data[1] & (1 << 8)) ? "random" : "sequential");
+	instr_out(ctx, 2, indirect ? "ignored" : "vertex count\n");
+	instr_out(ctx, 3, indirect ? "ignored" : "start vertex\n");
+	instr_out(ctx, 4, indirect ? "ignored" : "instance count\n");
+	instr_out(ctx, 5, indirect ? "ignored" : "start instance\n");
+	instr_out(ctx, 6, indirect ? "ignored" : "index bias\n");
+
+	return 7;
+}
+
+static int
 decode_3d_965(struct drm_intel_decode *ctx)
 {
 	uint32_t opcode;
@@ -3120,7 +3139,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 		{ 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" },
 		{ 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" },
 		{ 0x7a00, 0x00ff, 4, 6, "PIPE_CONTROL" },
-		{ 0x7b00, 0x00ff, 7, 7, "3DPRIMITIVE", 7 },
+		{ 0x7b00, 0x00ff, 7, 7, NULL, 7, gen7_3DPRIMITIVE },
 		{ 0x7b00, 0x00ff, 6, 6, NULL, 0, gen4_3DPRIMITIVE },
 	}, *opcode_3d = NULL;
 
diff --git a/intel/tests/gen7-3d.batch-ref.txt b/intel/tests/gen7-3d.batch-ref.txt
index 1488ca5..be3c85e 100644
--- a/intel/tests/gen7-3d.batch-ref.txt
+++ b/intel/tests/gen7-3d.batch-ref.txt
@@ -202,11 +202,11 @@
 0x12300324:      0x11230000:    (X, Y, 0.0, 1.0), dst offset 0x00 bytes
 0x12300328:      0x02400008:    buffer 0: invalid, type 0x0040, src offset 0x0008 bytes
 0x1230032c:      0x11130000:    (X, Y, Z, 1.0), dst offset 0x00 bytes
-0x12300330:      0x7b000005: 3DPRIMITIVE
-0x12300334:      0x00000007:    dword 1
-0x12300338:      0x00000004:    dword 2
-0x1230033c:      0x00000000:    dword 3
-0x12300340:      0x00000001:    dword 4
-0x12300344:      0x00000000:    dword 5
-0x12300348:      0x00000000:    dword 6
+0x12300330:      0x7b000005: 3DPRIMITIVE: 
+0x12300334:      0x00000007:    quad list sequential
+0x12300338:      0x00000004:    vertex count
+0x1230033c:      0x00000000:    start vertex
+0x12300340:      0x00000001:    instance count
+0x12300344:      0x00000000:    start instance
+0x12300348:      0x00000000:    index bias
 0x1230034c:      0x05000000: MI_BATCH_BUFFER_END

commit 9b87fd9a3df8c59461bc90b4620526d10f9b5771
Author: Eric Anholt <eric@anholt.net>
Date:   Fri Mar 2 10:18:51 2012 -0800

    intel: Move the gen4-6 3DPRIMITIVE handling out of the switch statement.

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2ea8f67..af621d4 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3005,6 +3005,22 @@ gen7_3DSTATE_WM(struct drm_intel_decode *ctx)
 }
 
 static int
+gen4_3DPRIMITIVE(struct drm_intel_decode *ctx)
+{
+	instr_out(ctx, 0,
+		  "3DPRIMITIVE: %s %s\n",
+		  get_965_prim_type(ctx->data[0]),
+		  (ctx->data[0] & (1 << 15)) ? "random" : "sequential");
+	instr_out(ctx, 1, "vertex count\n");
+	instr_out(ctx, 2, "start vertex\n");
+	instr_out(ctx, 3, "instance count\n");
+	instr_out(ctx, 4, "start instance\n");
+	instr_out(ctx, 5, "index bias\n");
+
+	return 6;
+}
+
+static int
 decode_3d_965(struct drm_intel_decode *ctx)
 {
 	uint32_t opcode;
@@ -3105,7 +3121,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
 		{ 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" },
 		{ 0x7a00, 0x00ff, 4, 6, "PIPE_CONTROL" },
 		{ 0x7b00, 0x00ff, 7, 7, "3DPRIMITIVE", 7 },
-		{ 0x7b00, 0x00ff, 6, 6, "3DPRIMITIVE" },
+		{ 0x7b00, 0x00ff, 6, 6, NULL, 0, gen4_3DPRIMITIVE },
 	}, *opcode_3d = NULL;
 
 	opcode = (data[0] & 0xffff0000) >> 16;
@@ -3593,20 +3609,6 @@ decode_3d_965(struct drm_intel_decode *ctx)
 			instr_out(ctx, 3, "immediate dword high\n");
 			return len;
 		}
-	case 0x7b00:
-		if (ctx->gen == 7)
-			break;
-
-		instr_out(ctx, 0,
-			  "3DPRIMITIVE: %s %s\n",
-			  get_965_prim_type(data[0]),
-			  (data[0] & (1 << 15)) ? "random" : "sequential");
-		instr_out(ctx, 1, "vertex count\n");
-		instr_out(ctx, 2, "start vertex\n");
-		instr_out(ctx, 3, "instance count\n");
-		instr_out(ctx, 4, "start instance\n");
-		instr_out(ctx, 5, "index bias\n");
-		return len;
 	}
 
 	if (opcode_3d) {

commit 99c73378a1b440bcf594742445dfe14ab1e89128
Author: Eric Anholt <eric@anholt.net>
Date:   Fri Feb 10 04:12:15 2012 -0800

    intel: Add support for (possibly) unsynchronized maps.
    
    This improves the performance of Mesa's GL_MAP_UNSYNCHRONIZED_BIT path
    in GL_ARB_map_buffer_range.  Improves Unigine Tropics performance at
    1024x768 by 2.30482% +/- 0.0492146% (n=61)
    
    v2: Fix comment grammar.
    
    Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index a8062c5..45389e1 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -156,8 +156,10 @@ void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
 void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
 void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
 					     int limit);
+int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
+
 int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
 void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 0eb57c4..51b963f 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1189,15 +1189,13 @@ static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
 	return 0;
 }
 
-int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
+static int
+map_gtt(drm_intel_bo *bo)
 {
 	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
 	drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
-	struct drm_i915_gem_set_domain set_domain;
 	int ret;
 
-	pthread_mutex_lock(&bufmgr_gem->lock);
-
 	if (bo_gem->map_count++ == 0)
 		drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
 
@@ -1223,7 +1221,6 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
 			    strerror(errno));
 			if (--bo_gem->map_count == 0)
 				drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
-			pthread_mutex_unlock(&bufmgr_gem->lock);
 			return ret;
 		}
 
@@ -1240,7 +1237,6 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
 			    strerror(errno));
 			if (--bo_gem->map_count == 0)
 				drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
-			pthread_mutex_unlock(&bufmgr_gem->lock);
 			return ret;
 		}
 	}
@@ -1250,7 +1246,33 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
 	DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
 	    bo_gem->gtt_virtual);
 
-	/* Now move it to the GTT domain so that the CPU caches are flushed */
+	return 0;
+}
+
+int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
+{
+	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
+	drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+	struct drm_i915_gem_set_domain set_domain;
+	int ret;
+
+	pthread_mutex_lock(&bufmgr_gem->lock);
+
+	ret = map_gtt(bo);
+	if (ret) {
+		pthread_mutex_unlock(&bufmgr_gem->lock);
+		return ret;
+	}
+
+	/* Now move it to the GTT domain so that the GPU and CPU
+	 * caches are flushed and the GPU isn't actively using the
+	 * buffer.
+	 *
+	 * The pagefault handler does this domain change for us when
+	 * it has unbound the BO from the GTT, but it's up to us to
+	 * tell it when we're about to use things if we had done
+	 * rendering and it still happens to be bound to the GTT.
+	 */
 	VG_CLEAR(set_domain);
 	set_domain.handle = bo_gem->gem_handle;
 	set_domain.read_domains = I915_GEM_DOMAIN_GTT;
@@ -1271,6 +1293,42 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
 	return 0;
 }
 
+/**
+ * Performs a mapping of the buffer object like the normal GTT
+ * mapping, but avoids waiting for the GPU to be done reading from or
+ * rendering to the buffer.
+ *
+ * This is used in the implementation of GL_ARB_map_buffer_range: The
+ * user asks to create a buffer, then does a mapping, fills some
+ * space, runs a drawing command, then asks to map it again without
+ * synchronizing because it guarantees that it won't write over the
+ * data that the GPU is busy using (or, more specifically, that if it
+ * does write over the data, it acknowledges that rendering is
+ * undefined).
+ */
+
+int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
+{
+	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
+	int ret;
+
+	/* If the CPU cache isn't coherent with the GTT, then use a
+	 * regular synchronized mapping.  The problem is that we don't
+	 * track where the buffer was last used on the CPU side in
+	 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
+	 * we would potentially corrupt the buffer even when the user
+	 * does reasonable things.
+	 */
+	if (!bufmgr_gem->has_llc)
+		return drm_intel_gem_bo_map_gtt(bo);
+
+	pthread_mutex_lock(&bufmgr_gem->lock);
+	ret = map_gtt(bo);
+	pthread_mutex_unlock(&bufmgr_gem->lock);
+
+	return ret;
+}
+
 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
 {
 	drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;

commit 3a8884851b72af012a8cb2beea320f094a58e5eb
Author: Eric Anholt <eric@anholt.net>
Date:   Mon Feb 27 17:26:05 2012 -0800

    intel: Fix error check for I915_PARAM_HAS_LLC.
    
    drmIoctl returns -1 on error with errno set to the error value.  Other
    users of it in this file just check for != 0, and only use errno when
    they need to send an error value on to the caller of the API.

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index e87690d..0eb57c4 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2753,7 +2753,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 
 	gp.param = I915_PARAM_HAS_LLC;
 	ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
-	if (ret == -EINVAL) {
+	if (ret != 0) {
 		/* Kernel does not supports HAS_LLC query, fallback to GPU
 		 * generation detection and assume that we have LLC on GEN6/7
 		 */

commit c9ce2edfc8d33e760667529250e86e93ff656c3d
Author: Eric Anholt <eric@anholt.net>
Date:   Fri Mar 9 16:08:23 2012 -0800

    intel: Bump the copyright dates on the bufmgr files.
    
    We've been hacking these constantly.

diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index fa6f2b8..a8062c5 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright © 2008 Intel Corporation
+ * Copyright © 2008-2012 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index d56593a..e87690d 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1,7 +1,7 @@
 /**************************************************************************
  *
  * Copyright � 2007 Red Hat Inc.
- * Copyright � 2007 Intel Corporation
+ * Copyright � 2007-2012 Intel Corporation
  * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
  * All Rights Reserved.
  *

commit 4db16a9480af2c4f36eb8023193cd54545efbe54
Author: Eric Anholt <eric@anholt.net>
Date:   Tue Oct 11 15:59:03 2011 -0700

    intel: Add .aub file output support.
    
    This will allow the driver to capture all of its execution state to a
    file for later debugging.  intel_gpu_dump is limited in that it only
    captures batchbuffers, and Mesa's captures, while more complete, still
    capture only a portion of the state involved in execution.
    
    This is a squash commit of a long series of hacking as we tried to get
    the resulting traces to work in the internal simulator.  It contains
    contributions by Yuanhan Liu and Kenneth Graunke.
    
    v2: Drop the MI_FLUSH_ENABLE setup.
    
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
    Signed-off-by: Eric Anholt <eric@anholt.net>
    Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
    Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/intel/Makefile.am b/intel/Makefile.am
index 06362b6..dc01a96 100644
--- a/intel/Makefile.am
+++ b/intel/Makefile.am
@@ -53,6 +53,7 @@ intel_bufmgr_gem_o_CFLAGS = $(AM_CFLAGS) -c99
 
 libdrm_intelincludedir = ${includedir}/libdrm
 libdrm_intelinclude_HEADERS = intel_bufmgr.h \
+			      intel_aub.h \
 			      intel_debug.h
 
 # This may be interesting even outside of "make check", due to the -dump option.
diff --git a/intel/intel_aub.h b/intel/intel_aub.h
new file mode 100644
index 0000000..a36fd53
--- /dev/null
+++ b/intel/intel_aub.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR


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