mesa: Changes to 'ubuntu'
Makefile | 2
configure.ac | 2
debian/changelog | 42
debian/control | 11
debian/libegl1-mesa-dev.install.in | 5
debian/libegl1-mesa-dev.install.linux.in | 10
debian/libegl1-mesa-drivers.install.in | 1
debian/libegl1-mesa-drivers.install.linux.in | 6
debian/libegl1-mesa.symbols | 2
debian/libgl1-mesa-dri.install.kfreebsd.in | 6
debian/rules | 23
docs/contents.html | 1
docs/news.html | 10
docs/relnotes-8.0.1.html | 151 +++
docs/relnotes-8.0.html | 6
docs/systems.html | 68 +
docs/vmware-guest.html | 3
src/gallium/auxiliary/postprocess/postprocess.h | 3
src/gallium/auxiliary/postprocess/pp_init.c | 6
src/gallium/auxiliary/postprocess/pp_run.c | 13
src/gallium/drivers/r600/evergreen_state.c | 16
src/gallium/drivers/r600/evergreend.h | 3
src/gallium/drivers/r600/r600_pipe.c | 25
src/gallium/drivers/r600/r600_pipe.h | 1
src/gallium/drivers/softpipe/sp_screen.c | 2
src/gallium/drivers/softpipe/sp_state_derived.c | 3
src/gallium/state_trackers/dri/common/dri_context.c | 3
src/gallium/state_trackers/dri/common/dri_drawable.c | 30
src/gallium/state_trackers/dri/drm/dri2.c | 3
src/gallium/state_trackers/vega/path.c | 2
src/gallium/state_trackers/xorg/xvmc/subpicture.c | 3
src/glsl/ast_to_hir.cpp | 545 ++++++------
src/glsl/glcpp/glcpp-lex.l | 10
src/glsl/glcpp/glcpp-parse.y | 3
src/glsl/glsl_parser.yy | 6
src/glsl/glsl_parser_extras.cpp | 5
src/glsl/glsl_parser_extras.h | 21
src/mapi/glapi/glapi_nop.c | 8
src/mapi/glapi/glapi_priv.h | 10
src/mesa/drivers/common/meta.c | 17
src/mesa/drivers/dri/common/drirc | 10
src/mesa/drivers/dri/common/xmlpool/options.h | 10
src/mesa/drivers/dri/i915/i830_vtbl.c | 5
src/mesa/drivers/dri/i915/i915_vtbl.c | 5
src/mesa/drivers/dri/i915/intel_tris.c | 2
src/mesa/drivers/dri/i965/Makefile.sources | 1
src/mesa/drivers/dri/i965/brw_context.c | 57 -
src/mesa/drivers/dri/i965/brw_context.h | 40
src/mesa/drivers/dri/i965/brw_defines.h | 1
src/mesa/drivers/dri/i965/brw_draw.c | 47 -
src/mesa/drivers/dri/i965/brw_eu_emit.c | 2
src/mesa/drivers/dri/i965/brw_fs.cpp | 3
src/mesa/drivers/dri/i965/brw_fs.h | 14
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 8
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6
src/mesa/drivers/dri/i965/brw_misc_state.c | 2
src/mesa/drivers/dri/i965/brw_state_upload.c | 1
src/mesa/drivers/dri/i965/brw_structs.h | 11
src/mesa/drivers/dri/i965/brw_vec4.h | 1
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 6
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 14
src/mesa/drivers/dri/i965/brw_vtbl.c | 14
src/mesa/drivers/dri/i965/brw_wm.h | 3
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22
src/mesa/drivers/dri/i965/gen6_clip_state.c | 20
src/mesa/drivers/dri/i965/gen6_depthstencil.c | 9
src/mesa/drivers/dri/i965/gen6_hiz.c | 829 ++++++++++++-------
src/mesa/drivers/dri/i965/gen6_hiz.h | 38
src/mesa/drivers/dri/i965/gen6_sf_state.c | 29
src/mesa/drivers/dri/i965/gen6_vs_state.c | 9
src/mesa/drivers/dri/i965/gen6_wm_state.c | 20
src/mesa/drivers/dri/i965/gen7_clip_state.c | 20
src/mesa/drivers/dri/i965/gen7_hiz.c | 464 ++++++++++
src/mesa/drivers/dri/i965/gen7_hiz.h | 43
src/mesa/drivers/dri/i965/gen7_sf_state.c | 37
src/mesa/drivers/dri/i965/gen7_urb.c | 2
src/mesa/drivers/dri/i965/gen7_vs_state.c | 2
src/mesa/drivers/dri/i965/gen7_wm_state.c | 18
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 33
src/mesa/drivers/dri/intel/intel_batchbuffer.h | 1
src/mesa/drivers/dri/intel/intel_blit.c | 2
src/mesa/drivers/dri/intel/intel_context.h | 2
src/mesa/drivers/dri/intel/intel_fbo.c | 112 --
src/mesa/drivers/dri/intel/intel_screen.c | 3
src/mesa/drivers/osmesa/osmesa.c | 3
src/mesa/main/arrayobj.c | 6
src/mesa/main/attrib.c | 13
src/mesa/main/bufferobj.c | 138 +--
src/mesa/main/context.c | 28
src/mesa/main/dlist.c | 21
src/mesa/main/format_unpack.c | 353 ++++++++
src/mesa/main/mipmap.c | 6
src/mesa/main/mtypes.h | 11
src/mesa/main/pack.c | 58 -
src/mesa/main/shared.c | 48 -
src/mesa/main/shared.h | 11
src/mesa/main/texgetimage.c | 9
src/mesa/main/teximage.c | 22
src/mesa/main/texstate.c | 19
src/mesa/main/texstore.c | 45 -
src/mesa/main/version.h | 4
src/mesa/state_tracker/st_cb_blit.c | 3
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2
src/mesa/swrast/s_aaline.c | 2
src/mesa/swrast/s_aalinetemp.h | 2
src/mesa/swrast/s_aatriangle.c | 2
src/mesa/swrast/s_context.c | 25
src/mesa/swrast/s_context.h | 3
src/mesa/swrast/s_fragprog.c | 13
src/mesa/swrast/s_fragprog.h | 2
src/mesa/swrast/s_lines.c | 2
src/mesa/swrast/s_renderbuffer.c | 28
src/mesa/swrast/s_span.c | 57 -
src/mesa/swrast/s_triangle.c | 4
src/mesa/vbo/vbo_exec_array.c | 2
116 files changed, 2765 insertions(+), 1244 deletions(-)
New commits:
commit 759b3aaf6bb77fff296bf560091f2481b26f3374
Author: Timo Aaltonen <tjaalton@ubuntu.com>
Date: Thu Feb 23 11:04:14 2012 +0200
update the changelog
diff --git a/debian/changelog b/debian/changelog
index d594d5c..7c83b4d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (8.0.1-1) UNRELEASED; urgency=low
+
+ * New upstream bugfix release. (LP: #926379)
+
+ -- Timo Aaltonen <tjaalton@ubuntu.com> Thu, 23 Feb 2012 10:58:33 +0200
+
mesa (8.0-2) experimental; urgency=low
[ Julien Cristau ]
commit fe77fd3983ba3da16ec53c58a790c381b07387ce
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Thu Feb 16 18:55:18 2012 -0800
docs: Add 8.0.1 release notes
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/docs/relnotes-8.0.1.html b/docs/relnotes-8.0.1.html
new file mode 100644
index 0000000..8c8cd3f
--- /dev/null
+++ b/docs/relnotes-8.0.1.html
@@ -0,0 +1,151 @@
+<HTML>
+
+<head>
+<TITLE>Mesa Release Notes</TITLE>
+<link rel="stylesheet" type="text/css" href="mesa.css">
+<meta http-equiv="content-type" content="text/html; charset=utf-8" />
+</head>
+
+<BODY>
+
+<body bgcolor="#eeeeee">
+
+<H1>Mesa 8.0.1 Release Notes / February 16, 2012</H1>
+
+<p>
+Mesa 8.0.1 is a bug fix release which fixes bugs found since the 8.0 release.
+</p>
+<p>
+Mesa 8.0 implements the OpenGL 3.0 API, but the version reported by
+glGetString(GL_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.0.
+</p>
+<p>
+See the <a href="install.html">Compiling/Installing page</a> for prerequisites
+for DRI hardware acceleration.
+</p>
+
+
+<h2>MD5 checksums</h2>
+<pre>
+tdb
+</pre>
+
+<h2>New features</h2>
+<p>None.</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=28924";>Bug 28924</a> - [ILK] piglit tex-border-1 fail</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=40864";>Bug 40864</a> - [bisected pineview] oglc pxconv-gettex(basic.allCases) fails on pineview</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=43327";>Bug 43327</a> - [bisected SNB] HiZ make many oglc cases regressed</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44333";>Bug 44333</a> - [bisected] Color distortion with xbmc mediaplayer</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=44927";>Bug 44927</a> - [SNB IVB regression] gl-117 abort when click</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45221";>Bug 45221</a> - [bisected IVB] glean/fbo regression in stencil-only case</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45877";>Bug 45877</a> - main/image.c:1597: _mesa_convert_colors: Assertion `dstType == 0x1406' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45578";>Bug 45578</a> - main/image.c:1659: _mesa_convert_colors: Assertion `dstType == 0x1403' failed.</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45872";>Bug 45872</a> - [bisected PNV] oglc mustpass(basic.stipple) regressed on pineview</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45876";>Bug 45876</a> - [PNV]oglc texenv(basic.allCases) regressed on pineview</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45917";>Bug 45917</a> - [PNV] Regression in Piglit test general/two-sided-lighting-separate-specular</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=45943";>Bug 45943</a> - [r300g] r300_emit.c:365:r300_emit_aa_state: Assertion `(aa-d>dest)->cs_buf' failed.</li>
+
+<!-- <li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=";>Bug </a> - </li> -->
+
+</ul>
+
+
+<h2>Changes</h2>
+<p>The full set of changes can be viewed by using the following GIT command:</p>
+
+<pre>
+ git log mesa-8.0..mesa-8.0.1
+</pre>
+
+<p>Alex Deucher (2):
+<ul>
+ <li>r600g: fix tex tile_type offset for cayman</li>
+ <li>r600g: 128 bit formats require tile_type = 1 on cayman</li>
+</ul></p>
+
+<p>Anuj Phogat (2):
+<ul>
+ <li>meta: Add pixel store/pack operations in decompress_texture_image</li>
+ <li>meta: Avoid FBO resizing/reallocating in decompress_texture_image</li>
+</ul></p>
+
+<p>Brian Paul (6):
+<ul>
+ <li>docs: add news item for 8.0 release</li>
+ <li>docs: update info about supported systems, GPUs, APIs</li>
+ <li>docs: add VMware link</li>
+ <li>docs: remove link to the GLSL compiler page</li>
+ <li>mesa: fix proxy texture target initialization</li>
+ <li>swrast: fix span color type selection</li>
+</ul></p>
+
+<p>Chad Versace (2):
+<ul>
+ <li>i965: Rewrite the HiZ op</li>
+ <li>i965: Remove file i965/junk, accidentally added in 7b36c68</li>
+</ul></p>
+
+<p>Dave Airlie (1):
+<ul>
+ <li>st/mesa: only resolve if number of samples is > 1</li>
+</ul></p>
+
+<p>Eric Anholt (3):
+<ul>
+ <li>i965: Fix HiZ change compiler warning.</li>
+ <li>i965: Report the failure message when failing to compile the fragment shader.</li>
+ <li>i965/fs: Enable register spilling on gen7 too.</li>
+</ul></p>
+
+<p>Ian Romanick (4):
+<ul>
+ <li>docs: Add 8.0 MD5 checksums</li>
+ <li>glapi: Include GLES2 headers for ES2 extension functions</li>
+ <li>swrast: Only avoid empty _TexEnvPrograms</li>
+ <li>mesa: Bump version number to 8.0.1</li>
+</ul></p>
+
+<p>Kenneth Graunke (4):
+<ul>
+ <li>i965: Fix border color on Ironlake.</li>
+ <li>i965/fs: Add a new fs_inst::regs_written function.</li>
+ <li>i965/fs: Take # of components into account in try_rewrite_rhs_to_dst.</li>
+ <li>i965: Emit Ivybridge VS workaround flushes.</li>
+</ul></p>
+
+<p>Mathias Fröhlich (1):
+<ul>
+ <li>state_stracker: Fix access to uninitialized memory.</li>
+</ul></p>
+
+<p>Paul Berry (1):
+<ul>
+ <li>i915: Fix type of "specoffset" variable.</li>
+</ul></p>
+
+<p>Simon Farnsworth (1):
+<ul>
+ <li>r600g: Use a fake reloc to sleep for fences</li>
+</ul></p>
+
+</body>
+</html>
commit b6950789377b2b31d93beca9d61d1f38c9ba5d4b
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Thu Feb 16 18:54:28 2012 -0800
mesa: Bump version number to 8.0.1
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
diff --git a/Makefile b/Makefile
index e0dd6ef..81ae944 100644
--- a/Makefile
+++ b/Makefile
@@ -184,7 +184,7 @@ ultrix-gcc:
# Rules for making release tarballs
-PACKAGE_VERSION=8.0
+PACKAGE_VERSION=8.0.1
PACKAGE_DIR = Mesa-$(PACKAGE_VERSION)
PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 11fe922..50f6adb 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -34,8 +34,8 @@ struct gl_context;
/* Mesa version */
#define MESA_MAJOR 8
#define MESA_MINOR 0
-#define MESA_PATCH 0
-#define MESA_VERSION_STRING "8.0"
+#define MESA_PATCH 1
+#define MESA_VERSION_STRING "8.0.1"
/* To make version comparison easy */
#define MESA_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
commit 106ea10d1b246aba1a0f4e171fd7d21268f3960f
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Tue Feb 14 12:06:20 2012 +0000
r600g: Use a fake reloc to sleep for fences
r300g is able to sleep until a fence completes rather than busywait because
it creates a special buffer object and relocation that stays busy until the
CS containing the fence is finished.
Copy the idea into r600g, and use it to sleep if the user asked for an
infinite wait, falling back to busywaiting if the user provided a timeout.
Signed-off-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4)
Conflicts:
src/gallium/drivers/r600/r600_pipe.c
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 43d6fea..008a0b9 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -47,6 +47,7 @@
#include "r600_resource.h"
#include "r600_shader.h"
#include "r600_pipe.h"
+#include "r600_hw_context_priv.h"
/*
* pipe_context
@@ -116,6 +117,14 @@ static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
rscreen->fences.data[fence->index] = 0;
r600_context_emit_fence(&ctx->ctx, rscreen->fences.bo, fence->index, 1);
+
+ /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
+ fence->sleep_bo = (struct r600_resource*)
+ pipe_buffer_create(&ctx->ctx.screen->screen, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_STAGING, 1);
+ /* Add the fence as a dummy relocation. */
+ r600_context_bo_reloc(&ctx->ctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
+
out:
pipe_mutex_unlock(rscreen->fences.mutex);
return fence;
@@ -568,6 +577,7 @@ static void r600_fence_reference(struct pipe_screen *pscreen,
if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
pipe_mutex_lock(rscreen->fences.mutex);
+ pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
pipe_mutex_unlock(rscreen->fences.mutex);
}
@@ -601,6 +611,17 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen,
}
while (rscreen->fences.data[rfence->index] == 0) {
+ /* Special-case infinite timeout - wait for the dummy BO to become idle */
+ if (timeout == PIPE_TIMEOUT_INFINITE) {
+ rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
+ break;
+ }
+
+ /* The dummy BO will be busy until the CS including the fence has completed, or
+ * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
+ if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
+ break;
+
if (++spins % 256)
continue;
#ifdef PIPE_OS_UNIX
@@ -610,11 +631,11 @@ static boolean r600_fence_finish(struct pipe_screen *pscreen,
#endif
if (timeout != PIPE_TIMEOUT_INFINITE &&
os_time_get() - start_time >= timeout) {
- return FALSE;
+ break;
}
}
- return TRUE;
+ return rscreen->fences.data[rfence->index] != 0;
}
static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 015d5e0..5e62210 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -172,6 +172,7 @@ struct r600_textures_info {
struct r600_fence {
struct pipe_reference reference;
unsigned index; /* in the shared bo */
+ struct r600_resource *sleep_bo;
struct list_head head;
};
commit fca1a33c96f2063bbaa4a6898fef1e41a197073d
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Feb 10 11:02:03 2012 -0500
r600g: 128 bit formats require tile_type = 1 on cayman
Noticed by taiu on IRC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 5e1495b2d9311fa2b320766a1d299053904bd9c3)
Conflicts:
src/gallium/drivers/r600/evergreen_state.c
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 9fd5855..83699e3 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1093,6 +1093,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
util_format_get_blockwidth(state->format), 8);
array_mode = tmp->array_mode[0];
tile_type = tmp->tile_type;
+ /* 128 bit formats require tile type = 1 */
+ if (rctx->chip_class == CAYMAN) {
+ if (util_format_get_blocksize(state->format) >= 16)
+ tile_type = 1;
+ }
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
@@ -1461,6 +1466,11 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
tile_type = rtex->tile_type;
} else /* workaround for linear buffers */
tile_type = 1;
+ /* 128 bit formats require tile type = 1 */
+ if (rctx->chip_class == CAYMAN) {
+ if (util_format_get_blocksize(surf->base.format) >= 16)
+ tile_type = 1;
+ }
/* FIXME handle enabling of CB beyond BASE8 which has different offset */
r600_pipe_state_add_reg(rstate,
commit 036d9992659bdd03c44800835f48b99f26ca24d7
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Fri Feb 10 10:49:13 2012 -0500
r600g: fix tex tile_type offset for cayman
Noticed by taiu on IRC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit acca690c259824636ef1ff684a10bd1caca4751f)
Conflicts:
src/gallium/drivers/r600/evergreen_state.c
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 60b1909..9fd5855 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1046,6 +1046,7 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
struct pipe_resource *texture,
const struct pipe_sampler_view *state)
{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
struct r600_pipe_resource_state *rstate;
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
@@ -1107,8 +1108,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
S_030000_PITCH((pitch / 8) - 1) |
- S_030000_NON_DISP_TILING_ORDER(tile_type) |
S_030000_TEX_WIDTH(texture->width0 - 1));
+ if (rctx->chip_class == CAYMAN)
+ rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
+ else
+ rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index fa3fece..310eb10 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -970,6 +970,9 @@
#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
+#define CM_S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x3) << 4)
+#define CM_G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x3)
+#define CM_C_030000_NON_DISP_TILING_ORDER 0xFFFFFFCF
#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
#define C_030000_PITCH 0xFFFC003F
commit e3943cf1ccf5a08c8f1b98ebdd30980a7efc6f02
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu Jan 19 09:55:34 2012 -0800
i965: Emit Ivybridge VS workaround flushes.
I recently discovered this text in the BSpec. It seems wise to comply,
though I haven't observed it to fix anything yet.
Fixes a regression in glean/fbo since 28cfa1fa213fe.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 709f50928e1d4df755ffb90ec9f33ba6c9605a32)
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index e6cf1eb..920c9fc 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -99,6 +99,8 @@ gen7_upload_urb(struct brw_context *brw)
/* GS requirement */
assert(!brw->gs.prog_active);
+ gen7_emit_vs_workaround_flush(intel);
+
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
OUT_BATCH(brw->urb.nr_vs_entries |
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 0746e6c..a3d652c 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -35,6 +35,8 @@ upload_vs_state(struct brw_context *brw)
struct intel_context *intel = &brw->intel;
uint32_t floating_point_mode = 0;
+ gen7_emit_vs_workaround_flush(intel);
+
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
OUT_BATCH(brw->bind.bo_offset);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index ab4cb7e..d8b1eca 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -57,13 +57,13 @@ intel_batchbuffer_init(struct intel_context *intel)
{
intel_batchbuffer_reset(intel);
- if (intel->gen == 6) {
+ if (intel->gen >= 6) {
/* We can't just use brw_state_batch to get a chunk of space for
* the gen6 workaround because it involves actually writing to
* the buffer, and the kernel doesn't let us write to the batch.
*/
intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr,
- "gen6 workaround",
+ "pipe_control workaround",
4096, 4096);
}
}
@@ -364,6 +364,28 @@ intel_emit_depth_stall_flushes(struct intel_context *intel)
}
/**
+ * From the BSpec, volume 2a.03: VS Stage Input / State:
+ * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
+ * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
+ * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
+ * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
+ * to be sent before any combination of VS associated 3DSTATE."
+ */
+void
+gen7_emit_vs_workaround_flush(struct intel_context *intel)
+{
+ assert(intel->gen == 7);
+
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE);
+ OUT_RELOC(intel->batch.workaround_bo,
+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
+ OUT_BATCH(0); /* write data */
+ ADVANCE_BATCH();
+}
+
+/**
* Emits a PIPE_CONTROL with a non-zero post-sync operation, for
* implementing two workarounds on gen6. From section 1.4.7.1
* "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index e5e5bd4..751ec99 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -43,6 +43,7 @@ bool intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
void intel_batchbuffer_emit_mi_flush(struct intel_context *intel);
void intel_emit_post_sync_nonzero_flush(struct intel_context *intel);
void intel_emit_depth_stall_flushes(struct intel_context *intel);
+void gen7_emit_vs_workaround_flush(struct intel_context *intel);
static INLINE uint32_t float_as_int(float f)
{
commit 0aadb240e191538b07c45733dc2597235a52d274
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Feb 14 12:43:22 2012 -0800
i965/fs: Take # of components into account in try_rewrite_rhs_to_dst.
Commit dc7f449d1ac53a66e6efb56ccf2a5953418a26ca introduced a new method
for avoiding MOVs: try to rewrite the destination of the instruction
that produced the RHS so it writes into the LHS.
Unfortunately, this is not safe for swizzled texturing operations, as
they return a set of four contiguous registers. Consider the following:
(assign (x)
(var_ref vec_ctor_x)
(swiz x (tex vec4 (var_ref m_sampY) (var_ref m_cordY) 0 1 ())))
In this case, the source and destination registers are equal, since
reg_offset is 0 for both. Yet, this is only a partial move: the texture
operation generates four registers, and the LHS only covers one.
Fixes color distortion in XBMC when using GLSL shaders.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44333
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 4b274068204c7f0bacaa4639f24feb433353b861)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 44c9ee8..0632052 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -564,6 +564,12 @@ fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
!src.equals(&last_rhs_inst->dst))
return false;
+ /* If last_rhs_inst wrote a different number of components than our LHS,
+ * we can't safely rewrite it.
+ */
+ if (ir->lhs->type->vector_elements != last_rhs_inst->regs_written())
+ return false;
+
/* Success! Rewrite the instruction. */
last_rhs_inst->dst = dst;
commit 740123fff754fac9da3e9807e2fcd05d66690866
Author: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue Feb 14 12:43:21 2012 -0800
i965/fs: Add a new fs_inst::regs_written function.
Certain instructions write more than one register. Texturing, for
example, returns 4 registers. (We set rlen to 4 even for TXS and float
shadow sampling.) Some math functions return 2. Most return 1.
The next commit introduces a use of this function.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 8ab02b511882857a09fceed0e93bf4a0b25c17b2)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 5fdc055..9a2cc08 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -286,6 +286,18 @@ public:
offset == inst->offset);
}
+ int regs_written()
+ {
+ if (is_tex())
+ return 4;
+
+ /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
+ * but we don't currently use them...nor do we have an opcode for them.
+ */
+
+ return 1;
+ }
+
bool is_tex()
{
return (opcode == SHADER_OPCODE_TEX ||
commit ff1d9450321d5fe164611f819ee299706d9cbe02
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Fri Feb 10 16:00:27 2012 -0800
swrast: Only avoid empty _TexEnvPrograms
If the generated shader for _TexEnvProgram is empty, force the use of
the fixed-function code. Otherwise, go ahead and use the shader.
This works around a mysterious issue on i915 where fixed-function
software fallbacks are not working correctly.
This isn't really the fix we want, but it works around the issue.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45872
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45876
(cherry picked from commit 3e22d4e5fc32dafcb9669a9d6376323aa88e300c)
diff --git a/src/mesa/swrast/s_fragprog.c b/src/mesa/swrast/s_fragprog.c
index cd20d8e..8d59371 100644
--- a/src/mesa/swrast/s_fragprog.c
+++ b/src/mesa/swrast/s_fragprog.c
@@ -40,7 +40,8 @@ GLboolean
_swrast_use_fragment_program(struct gl_context *ctx)
{
struct gl_fragment_program *fp = ctx->FragmentProgram._Current;
- return fp && fp != ctx->FragmentProgram._TexEnvProgram;
+ return fp && !(fp == ctx->FragmentProgram._TexEnvProgram
+ && fp->Base.NumInstructions == 0);
}
/**
commit efca49fd513dd7504a07368c61e7198cfebe24a9
Author: Ian Romanick <ian.d.romanick@intel.com>
Date: Wed Feb 8 13:04:38 2012 -0800
glapi: Include GLES2 headers for ES2 extension functions
This fixes build errors like
In file included from glapi_dispatch.c:91:
../../../src/mapi/glapi/glapitemp.h:4641: error: no previous prototype for
'glDrawBuffersNV'
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Lucas Stach <dev@lynxeye.de>
(cherry picked from commit 8f3be339850ead96f9c6200db4e0db1f74e39d13)
diff --git a/src/mapi/glapi/glapi_priv.h b/src/mapi/glapi/glapi_priv.h
index 3ab553a..b6600c5 100644
--- a/src/mapi/glapi/glapi_priv.h
+++ b/src/mapi/glapi/glapi_priv.h
@@ -38,6 +38,16 @@
#include "GL/gl.h"
#include "GL/glext.h"
+/* The define of GL_COVERAGE_SAMPLES_NV in gl2ext.h is guarded by a different
+ * extension (GL_NV_coverage_sample) than in glext.h
+ * (GL_NV_multisample_coverage). Just undefine it to avoid spurious compiler
+ * warnings.
+ */
+#undef GL_COVERAGE_SAMPLES_NV
+
+#include "GLES2/gl2platform.h"
+#include "GLES2/gl2ext.h"
+
#ifndef GL_OES_fixed_point
typedef int GLfixed;
typedef int GLclampx;
commit d45a5fde45e30c4475a92217b582c73d8ef5f52b
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Mon Feb 13 10:48:45 2012 -0800
meta: Avoid FBO resizing/reallocating in decompress_texture_image
Reallocate/resize decompress FBO only if texture image width/height is
greater than existing decompress FBO width/height.
This is a candidate for stable branches.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 66bf25f1a2cc8343640cdfc4242d882bc00b9e3b)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 2b994de..4dd9b29 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -3291,7 +3291,7 @@ decompress_texture_image(struct gl_context *ctx,
}
/* alloc dest surface */
- if (width != decompress->Width || height != decompress->Height) {
+ if (width > decompress->Width || height > decompress->Height) {
_mesa_RenderbufferStorageEXT(GL_RENDERBUFFER_EXT, GL_RGBA,
width, height);
decompress->Width = width;
commit e55f2d97f61420f6004c60be4238799f7a35b440
Author: Paul Berry <stereotype441@gmail.com>
Date: Fri Feb 10 19:51:55 2012 -0800
i915: Fix type of "specoffset" variable.
Commit 2e5a1a2 (intel: Convert from GLboolean to 'bool' from
stdbool.h.) converted the "specoffset" local variable (in
intel_tris.c) from a GLboolean to a bool. However, GLboolean was the
wrong type for specoffset--it should have been a GLuint (to match the
declaration of specoffset in struct intel_context).
This patch changes specoffset to the proper type.
Fixes piglit test general/two-sided-lighting-separate-specular.
This is a candidate for stable branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45917
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 6b0a07f9ce844a8a96e2583bd37ed8453bf151c6)
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 23de6ea..a36011a 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -663,7 +663,7 @@ do { \
struct intel_context *intel = intel_context(ctx); \
GLuint color[n] = { 0, }, spec[n] = { 0, }; \
GLuint coloroffset = intel->coloroffset; \
- bool specoffset = intel->specoffset; \
+ GLuint specoffset = intel->specoffset; \
(void) color; (void) spec; (void) coloroffset; (void) specoffset;
commit 6e09d3cff2e850b8fef44c4f7bd7397c78376f1d
Author: Mathias Fröhlich <Mathias.Froehlich@gmx.net>
Date: Sat Jan 28 18:55:08 2012 +0100
state_stracker: Fix access to uninitialized memory.
Fix an access to uninitialized memory pointed out by valgrind in
glsl_to_tgsi_visitor::simplify_cmp(void).
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
(cherry picked from commit 1d01429c6a1ae679d0cc0cb61db1948fca5ced4c)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 26047cf..ec8b1d1 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2978,7 +2978,7 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
if (!tempWrites) {
return;
}
- memset(tempWrites, 0, sizeof(tempWrites));
+ memset(tempWrites, 0, sizeof(unsigned) * MAX_TEMPS);
memset(outputWrites, 0, sizeof(outputWrites));
foreach_iter(exec_list_iterator, iter, this->instructions) {
commit 99f9c9789a2d316d97ca6791343fb697f220929e
Author: Eric Anholt <eric@anholt.net>
Date: Thu Feb 9 16:35:49 2012 -0800
i965/fs: Enable register spilling on gen7 too.
It turns out the same messages work on gen7, we were just being paranoid.
Fixes the penumbra shadows mode of Lightsmark since the register
allocation fix.
NOTE: This is a candidate for release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 93831a54c7d4e74f353e0029164b1b3262e98806)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 0d1712e..7da1418 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -236,8 +236,6 @@ fs_visitor::assign_regs()
if (reg == -1) {
fail("no register to spill\n");
- } else if (intel->gen >= 7) {
- fail("no spilling support on gen7 yet\n");
} else if (c->dispatch_width == 16) {
fail("no spilling support on 16-wide yet\n");
} else {
commit a63d79dd4075fdc4dba4b9b6c9801fca93a8a725
Author: Eric Anholt <eric@anholt.net>
Date: Thu Feb 9 10:23:45 2012 -0800
i965: Report the failure message when failing to compile the fragment shader.
We just abort later, but at least this should result in more
informative bug reports.
NOTE: This is a candidate for release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit a7f46eadea4555ed377928d4e3f89db4a445312e)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 40327ac..0de1eef 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1844,6 +1844,9 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
prog->LinkStatus = false;
ralloc_strcat(&prog->InfoLog, v.fail_msg);
+ _mesa_problem(NULL, "Failed to compile fragment shader: %s\n",
+ v.fail_msg);
+
return false;
}
commit ff7ccb1cf147b4c55492bc6ec6319dcbd6f31048
Author: Anuj Phogat <anuj.phogat@gmail.com>
Date: Fri Feb 10 16:27:19 2012 -0800
meta: Add pixel store/pack operations in decompress_texture_image
This patch adds the pixel store operations in decompress_texture_image().
decompress_texture_image() is used in glGetTexImage() for compressed
textures with unsigned, normalized values.
It also fixes the failures in intel oglconform pxstore-gettex due to
following sub test cases:
- Test all mipmaps with byte swapping enabled
- Test all small mipmaps with all allowable alignment values
- Test subimage packing for all mipmap levels
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40864
Note: This is a candidate for stable branches
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 40427025916e003cfd380c2e30df78ad2bc8fe10)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index aa5fef8..2b994de 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -3243,7 +3243,7 @@ decompress_texture_image(struct gl_context *ctx,
struct gl_texture_image *texImage,
GLuint slice,
GLenum destFormat, GLenum destType,
- GLvoid *dest, GLint destRowLength)
+ GLvoid *dest)
{
struct decompress_state *decompress = &ctx->Meta->Decompress;
struct gl_texture_object *texObj = texImage->TexObject;
@@ -3273,7 +3273,7 @@ decompress_texture_image(struct gl_context *ctx,
fboDrawSave = ctx->DrawBuffer->Name;
fboReadSave = ctx->ReadBuffer->Name;
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