intel-gpu-tools: Changes to 'upstream-unstable'
.gitignore | 154 -
COPYING | 108 +
Makefile.am | 20
autogen.sh | 14
benchmarks/.gitignore | 5
benchmarks/Makefile.am | 29
configure.ac | 130 -
debugger/.gitignore | 2
debugger/Makefile.am | 27
debugger/system_routine/.gitignore | 10
debugger/system_routine/GNUmakefile.in | 3
debugger/system_routine/Makefile | 84
debugger/system_routine/Makefile.am | 42
demos/.gitignore | 1
demos/Makefile.am | 7
demos/sprite_on.c | 1222 +++++++++++++
lib/Makefile.am | 51
lib/drmtest.c | 306 +++
lib/drmtest.h | 31
lib/gen6_render.h | 1553 +++++++++++++++++
lib/intel_batchbuffer.h | 1
lib/intel_drm.c | 99 +
lib/intel_gpu_tools.h | 1
lib/intel_mmio.c | 32
lib/intel_pci.c | 14
lib/intel_reg.h | 17
lib/intel_reg_map.c | 5
lib/rendercopy.h | 72
lib/rendercopy_gen6.c | 599 ++++++
lib/rendercopy_i830.c | 344 +++
lib/rendercopy_i915.c | 180 ++
m4/.gitignore | 5
man/Makefile.am | 44
man/intel_audio_dump.1 | 11
man/intel_audio_dump.man | 11
man/intel_bios_dumper.1 | 14
man/intel_bios_dumper.man | 14
man/intel_bios_reader.1 | 15
man/intel_bios_reader.man | 15
man/intel_error_decode.1 | 20
man/intel_error_decode.man | 20
man/intel_gpu_top.1 | 41
man/intel_gpu_top.man | 41
man/intel_gtt.1 | 14
man/intel_gtt.man | 14
man/intel_lid.1 | 12
man/intel_lid.man | 12
man/intel_reg_dumper.1 | 24
man/intel_reg_dumper.man | 24
man/intel_reg_read.1 | 15
man/intel_reg_read.man | 15
man/intel_reg_snapshot.1 | 15
man/intel_reg_snapshot.man | 15
man/intel_reg_write.1 | 16
man/intel_reg_write.man | 16
man/intel_stepping.1 | 15
man/intel_stepping.man | 15
man/intel_upload_blit_large.1 | 18
man/intel_upload_blit_large.man | 18
man/intel_upload_blit_large_gtt.1 | 18
man/intel_upload_blit_large_gtt.man | 18
man/intel_upload_blit_large_map.1 | 18
man/intel_upload_blit_large_map.man | 18
man/intel_upload_blit_small.1 | 18
man/intel_upload_blit_small.man | 18
scripts/Makefile.am | 7
tests/.gitignore | 57
tests/Makefile.am | 34
tests/ZZ_check_dmesg | 11
tests/ZZ_hangman | 62
tests/drm_vma_limiter.c | 110 +
tests/drm_vma_limiter_cached.c | 138 +
tests/drm_vma_limiter_cpu.c | 100 +
tests/drm_vma_limiter_gtt.c | 101 +
tests/gem_bad_length.c | 32
tests/gem_basic.c | 10
tests/gem_cs_prefetch.c | 169 +
tests/gem_exec_bad_domains.c | 10
tests/gem_exec_blt.c | 43
tests/gem_exec_faulting_reloc.c | 59
tests/gem_exec_nop.c | 63
tests/gem_fence_thrash.c | 12
tests/gem_fenced_exec_thrash.c | 44
tests/gem_flink.c | 14
tests/gem_gtt_speed.c | 104 -
tests/gem_largeobject.c | 23
tests/gem_linear_blits.c | 66
tests/gem_mmap.c | 39
tests/gem_mmap_gtt.c | 76
tests/gem_partial_pwrite_pread.c | 53
tests/gem_pwrite.c | 32
tests/gem_reloc_vs_gpu.c | 1
tests/gem_ring_sync_loop.c | 4
tests/gem_stress.c | 181 --
tests/gem_stress.h | 100 -
tests/gem_stress_gen6.c | 595 ------
tests/gem_stress_i830.c | 354 ---
tests/gem_stress_i915.c | 190 --
tests/gem_tiled_blits.c | 10
tests/gem_tiled_fence_blits.c | 42
tests/gem_tiled_pread.c | 61
tests/gem_tiled_pread_pwrite.c | 76
tests/gem_tiled_swapping.c | 145 +
tests/gem_vmap_blits.c | 62
tests/gen3_mixed_blits.c | 88
tests/gen3_render_linear_blits.c | 66
tests/gen3_render_mixed_blits.c | 86
tests/gen3_render_tiledx_blits.c | 86
tests/gen3_render_tiledy_blits.c | 86
tests/gen6_render.h | 1553 -----------------
tests/testdisplay.c | 291 +--
tests/testdisplay.h | 35
tests/testdisplay_hotplug.c | 136 +
tools/.gitignore | 20
tools/Makefile.am | 83
tools/intel_audio_dump.c | 381 +++-
tools/intel_bios_dumper.c | 20
tools/intel_bios_reader.c | 103 -
tools/intel_decode.c | 2931 ---------------------------------
tools/intel_decode.h | 35
tools/intel_dump_decode.c | 32
tools/intel_error_decode.c | 52
tools/intel_gpu_top.c | 16
tools/intel_gtt.c | 1
tools/intel_reg_dumper.c | 248 +-
tools/intel_reg_read.c | 4
tools/intel_reg_write.c | 3
tools/intel_stepping.c | 24
128 files changed, 7127 insertions(+), 8323 deletions(-)
New commits:
commit 2065ca15fb5a5a5c4079f6c0cb6361a4052e4fdb
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu Feb 9 22:39:50 2012 +0100
Release 1.2
diff --git a/configure.ac b/configure.ac
index 18cf310..94d54a6 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ([2.60])
AC_INIT([intel-gpu-tools],
- [1.1],
+ [1.2],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[intel-gpu-tools])
commit 06bfa3d3870521a595beb280f5f91c07422f189e
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu Feb 9 22:32:54 2012 +0100
lib/rendercopy: fixup make distcheck
And complete the gem_stress->rendercopy rename that I've forgotten
about.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 4e8d9e9..f9d6167 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -21,11 +21,11 @@ libintel_tools_la_SOURCES = \
intel_mmio.c \
intel_pci.c \
intel_reg.h \
- gem_stress_i915.c \
- gem_stress_i830.c \
+ rendercopy_i915.c \
+ rendercopy_i830.c \
gen6_render.h \
- gem_stress_gen6.c \
+ rendercopy_gen6.c \
+ rendercopy.h \
intel_reg_map.c \
- gem_stress.h \
$(NULL)
diff --git a/lib/gem_stress_gen6.c b/lib/gem_stress_gen6.c
deleted file mode 100644
index dafee88..0000000
--- a/lib/gem_stress_gen6.c
+++ /dev/null
@@ -1,599 +0,0 @@
-#include "rendercopy.h"
-#include "gen6_render.h"
-
-#include <assert.h>
-
-#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
-#define VERTEX_SIZE (3*4)
-
-static const uint32_t ps_kernel_nomask_affine[][4] = {
- { 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 },
- { 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 },
- { 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 },
- { 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 },
- { 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
- { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 },
- { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 },
- { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 },
- { 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 },
- { 0x00600001, 0x208003be, 0x008d0200, 0x00000000 },
- { 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 },
- { 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 },
- { 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 },
- { 0x00600001, 0x210003be, 0x008d0280, 0x00000000 },
- { 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 },
- { 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
- { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
-};
-
-static uint32_t
-batch_used(struct intel_batchbuffer *batch)
-{
- return batch->ptr - batch->buffer;
-}
-
-static uint32_t
-batch_align(struct intel_batchbuffer *batch, uint32_t align)
-{
- uint32_t offset = batch_used(batch);
- offset = ALIGN(offset, align);
- batch->ptr = batch->buffer + offset;
- return offset;
-}
-
-static uint32_t
-batch_round_upto(struct intel_batchbuffer *batch, uint32_t divisor)
-{
- uint32_t offset = batch_used(batch);
- offset = (offset + divisor-1) / divisor * divisor;
- batch->ptr = batch->buffer + offset;
- return offset;
-}
-
-static void *
-batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
-{
- uint32_t offset = batch_align(batch, align);
- batch->ptr += size;
- return memset(batch->buffer + offset, 0, size);
-}
-
-static uint32_t
-batch_offset(struct intel_batchbuffer *batch, void *ptr)
-{
- return (uint8_t *)ptr - batch->buffer;
-}
-
-static uint32_t
-batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
-{
- return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
-}
-
-static void
-gen6_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
-{
- int ret;
-
- ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
- if (ret == 0)
- ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
- NULL, 0, 0, 0);
- assert(ret == 0);
-}
-
-static uint32_t
-gen6_bind_buf(struct intel_batchbuffer *batch, struct scratch_buf *buf,
- uint32_t format, int is_dst)
-{
- struct gen6_surface_state *ss;
- uint32_t write_domain, read_domain;
- int ret;
-
- if (is_dst) {
- write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
- } else {
- write_domain = 0;
- read_domain = I915_GEM_DOMAIN_SAMPLER;
- }
-
- ss = batch_alloc(batch, sizeof(*ss), 32);
- ss->ss0.surface_type = GEN6_SURFACE_2D;
- ss->ss0.surface_format = format;
-
- ss->ss0.data_return_format = GEN6_SURFACERETURNFORMAT_FLOAT32;
- ss->ss0.color_blend = 1;
- ss->ss1.base_addr = buf->bo->offset;
-
- ret = drm_intel_bo_emit_reloc(batch->bo,
- batch_offset(batch, ss) + 4,
- buf->bo, 0,
- read_domain, write_domain);
- assert(ret == 0);
-
- ss->ss2.height = buf_height(buf) - 1;
- ss->ss2.width = buf_width(buf) - 1;
- ss->ss3.pitch = buf->stride - 1;
- ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE;
- ss->ss3.tile_walk = buf->tiling == I915_TILING_Y;
-
- return batch_offset(batch, ss);
-}
-
-static uint32_t
-gen6_bind_surfaces(struct intel_batchbuffer *batch,
- struct scratch_buf *src,
- struct scratch_buf *dst)
-{
- uint32_t *binding_table;
-
- binding_table = batch_alloc(batch, 32, 32);
-
- binding_table[0] =
- gen6_bind_buf(batch, dst, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
- binding_table[1] =
- gen6_bind_buf(batch, src, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
-
- return batch_offset(batch, binding_table);
-}
-
-static void
-gen6_emit_sip(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_STATE_SIP | 0);
- OUT_BATCH(0);
-}
-
-static void
-gen6_emit_urb(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
- OUT_BATCH((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT |
- 24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT); /* at least 24 on GEN6 */
- OUT_BATCH(0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT |
- 0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT); /* no GS thread */
-}
-
-static void
-gen6_emit_state_base_address(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
- OUT_BATCH(0); /* general */
- OUT_RELOC(batch->bo, /* surface */
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- BASE_ADDRESS_MODIFY);
- OUT_RELOC(batch->bo, /* instruction */
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- BASE_ADDRESS_MODIFY);
- OUT_BATCH(0); /* indirect */
- OUT_RELOC(batch->bo, /* dynamic */
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- BASE_ADDRESS_MODIFY);
-
- /* upper bounds, disable */
- OUT_BATCH(0);
- OUT_BATCH(BASE_ADDRESS_MODIFY);
- OUT_BATCH(0);
- OUT_BATCH(BASE_ADDRESS_MODIFY);
-}
-
-static void
-gen6_emit_viewports(struct intel_batchbuffer *batch, uint32_t cc_vp)
-{
- OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
- GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
- (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(cc_vp);
-}
-
-static void
-gen6_emit_vs(struct intel_batchbuffer *batch)
-{
- /* disable VS constant buffer */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
- OUT_BATCH(0); /* no VS kernel */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
-}
-
-static void
-gen6_emit_gs(struct intel_batchbuffer *batch)
-{
- /* disable GS constant buffer */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
- OUT_BATCH(0); /* no GS kernel */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
-}
-
-static void
-gen6_emit_clip(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0); /* pass-through */
- OUT_BATCH(0);
-}
-
-static void
-gen6_emit_wm_constants(struct intel_batchbuffer *batch)
-{
- /* disable WM constant buffer */
- OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-}
-
-static void
-gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH(GEN6_SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2));
- OUT_BATCH(0);
-}
-
-static void
-gen6_emit_invariant(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
-
- OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
- OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
- GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
- OUT_BATCH(0);
-
- OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
- OUT_BATCH(1);
-}
-
-static void
-gen6_emit_cc(struct intel_batchbuffer *batch, uint32_t blend)
-{
- OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
- OUT_BATCH(blend | 1);
- OUT_BATCH(1024 | 1);
- OUT_BATCH(1024 | 1);
-}
-
-static void
-gen6_emit_sampler(struct intel_batchbuffer *batch, uint32_t state)
-{
- OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
- GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
- (4 - 2));
- OUT_BATCH(0); /* VS */
- OUT_BATCH(0); /* GS */
- OUT_BATCH(state);
-}
-
-static void
-gen6_emit_sf(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
- OUT_BATCH(1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT |
- 1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT |
- 1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT);
- OUT_BATCH(0);
- OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
- OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW9 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW14 */
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0); /* DW19 */
-}
-
-static void
-gen6_emit_wm(struct intel_batchbuffer *batch, int kernel)
-{
- OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2));
- OUT_BATCH(kernel);
- OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT |
- 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
- OUT_BATCH(0);
- OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); /* DW4 */
- OUT_BATCH((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT |
- GEN6_3DSTATE_WM_DISPATCH_ENABLE |
- GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
- OUT_BATCH(1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT |
- GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
- OUT_BATCH(0);
- OUT_BATCH(0);
-}
-
-static void
-gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
-{
- OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS |
- GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
- (4 - 2));
- OUT_BATCH(0); /* vs */
- OUT_BATCH(0); /* gs */
- OUT_BATCH(wm_table);
-}
-
-static void
-gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct scratch_buf *dst)
-{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH((buf_height(dst) - 1) << 16 | (buf_width(dst) - 1));
- OUT_BATCH(0);
-}
-
-static void
-gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
-{
- /* The VUE layout
- * dword 0-3: pad (0.0, 0.0, 0.0. 0.0)
- * dword 4-7: position (x, y, 1.0, 1.0),
- * dword 8-11: texture coordinate 0 (u0, v0, 0, 0)
- *
- * dword 4-11 are fetched from vertex buffer
- */
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
-
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
- GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
- 0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
-
- /* x,y */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
- GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
- 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
-
- /* u0, v0 */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
- GEN6_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
- 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
-}
-
-static uint32_t
-gen6_create_cc_viewport(struct intel_batchbuffer *batch)
-{
- struct gen6_cc_viewport *vp;
-
- vp = batch_alloc(batch, sizeof(*vp), 32);
-
- vp->min_depth = -1.e35;
- vp->max_depth = 1.e35;
-
- return batch_offset(batch, vp);
-}
-
-static uint32_t
-gen6_create_cc_blend(struct intel_batchbuffer *batch)
-{
- struct gen6_blend_state *blend;
-
- blend = batch_alloc(batch, sizeof(*blend), 64);
-
- blend->blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
- blend->blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
- blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
- blend->blend0.blend_enable = 1;
-
- blend->blend1.post_blend_clamp_enable = 1;
- blend->blend1.pre_blend_clamp_enable = 1;
-
- return batch_offset(batch, blend);
-}
-
-static uint32_t
-gen6_create_kernel(struct intel_batchbuffer *batch)
-{
- return batch_copy(batch, ps_kernel_nomask_affine,
- sizeof(ps_kernel_nomask_affine),
- 64);
-}
-
-static uint32_t
-gen6_create_sampler(struct intel_batchbuffer *batch,
- sampler_filter_t filter,
- sampler_extend_t extend)
-{
- struct gen6_sampler_state *ss;
-
- ss = batch_alloc(batch, sizeof(*ss), 32);
- ss->ss0.lod_preclamp = 1; /* GL mode */
-
- /* We use the legacy mode to get the semantics specified by
- * the Render extension. */
- ss->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
-
- switch (filter) {
- default:
- case SAMPLER_FILTER_NEAREST:
- ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
- break;
- case SAMPLER_FILTER_BILINEAR:
- ss->ss0.min_filter = GEN6_MAPFILTER_LINEAR;
- ss->ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
- break;
- }
-
- switch (extend) {
- default:
- case SAMPLER_EXTEND_NONE:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- break;
- case SAMPLER_EXTEND_REPEAT:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- break;
- case SAMPLER_EXTEND_PAD:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- break;
- case SAMPLER_EXTEND_REFLECT:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- break;
- }
-
- return batch_offset(batch, ss);
-}
-
-static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch)
-{
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3);
- OUT_BATCH(VB0_VERTEXDATA |
- 0 << VB0_BUFFER_INDEX_SHIFT |
- VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
- OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
- OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, batch->bo->size-1);
- OUT_BATCH(0);
-}
-
-static uint32_t gen6_emit_primitive(struct intel_batchbuffer *batch)
-{
- uint32_t offset;
-
- OUT_BATCH(GEN6_3DPRIMITIVE |
- GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL |
- _3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT |
- 0 << 9 |
- 4);
- OUT_BATCH(3); /* vertex count */
- offset = batch_used(batch);
- OUT_BATCH(0); /* vertex_index */
- OUT_BATCH(1); /* single instance */
- OUT_BATCH(0); /* start instance location */
- OUT_BATCH(0); /* index buffer offset, ignored */
-
- return offset;
-}
-
-void gen6_render_copyfunc(struct intel_batchbuffer *batch,
- struct scratch_buf *src, unsigned src_x, unsigned src_y,
- unsigned width, unsigned height,
- struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
-{
- uint32_t wm_state, wm_kernel, wm_table;
- uint32_t cc_vp, cc_blend, offset;
- uint32_t batch_end;
-
- intel_batchbuffer_flush(batch);
-
- batch->ptr = batch->buffer + 1024;
- batch_alloc(batch, 64, 64);
- wm_table = gen6_bind_surfaces(batch, src, dst);
- wm_kernel = gen6_create_kernel(batch);
- wm_state = gen6_create_sampler(batch,
- SAMPLER_FILTER_NEAREST,
- SAMPLER_EXTEND_NONE);
-
- cc_vp = gen6_create_cc_viewport(batch);
- cc_blend = gen6_create_cc_blend(batch);
-
- batch->ptr = batch->buffer;
-
- gen6_emit_invariant(batch);
- gen6_emit_state_base_address(batch);
-
- gen6_emit_sip(batch);
- gen6_emit_urb(batch);
-
- gen6_emit_viewports(batch, cc_vp);
- gen6_emit_vs(batch);
- gen6_emit_gs(batch);
- gen6_emit_clip(batch);
- gen6_emit_wm_constants(batch);
- gen6_emit_null_depth_buffer(batch);
-
- gen6_emit_drawing_rectangle(batch, dst);
- gen6_emit_cc(batch, cc_blend);
- gen6_emit_sampler(batch, wm_state);
- gen6_emit_sf(batch);
- gen6_emit_wm(batch, wm_kernel);
- gen6_emit_vertex_elements(batch);
- gen6_emit_binding_table(batch, wm_table);
-
- gen6_emit_vertex_buffer(batch);
- offset = gen6_emit_primitive(batch);
-
- OUT_BATCH(MI_BATCH_BUFFER_END);
- batch_end = batch_align(batch, 8);
-
- *(uint32_t*)(batch->buffer + offset) =
- batch_round_upto(batch, VERTEX_SIZE)/VERTEX_SIZE;
-
- emit_vertex_2s(batch, dst_x + width, dst_y + height);
- emit_vertex_normalized(batch, src_x + width, buf_width(src));
- emit_vertex_normalized(batch, src_y + height, buf_height(src));
-
- emit_vertex_2s(batch, dst_x, dst_y + height);
- emit_vertex_normalized(batch, src_x, buf_width(src));
- emit_vertex_normalized(batch, src_y + height, buf_height(src));
-
- emit_vertex_2s(batch, dst_x, dst_y);
- emit_vertex_normalized(batch, src_x, buf_width(src));
- emit_vertex_normalized(batch, src_y, buf_height(src));
-
- gen6_render_flush(batch, batch_end);
- intel_batchbuffer_reset(batch);
-}
diff --git a/lib/gem_stress_i830.c b/lib/gem_stress_i830.c
deleted file mode 100644
index 54bb41e..0000000
--- a/lib/gem_stress_i830.c
+++ /dev/null
@@ -1,344 +0,0 @@
-#include "i830_reg.h"
-#include "rendercopy.h"
-
-#define TB0C_LAST_STAGE (1 << 31)
-#define TB0C_RESULT_SCALE_1X (0 << 29)
-#define TB0C_RESULT_SCALE_2X (1 << 29)
-#define TB0C_RESULT_SCALE_4X (2 << 29)
-#define TB0C_OP_MODULE (3 << 25)
-#define TB0C_OUTPUT_WRITE_CURRENT (0 << 24)
-#define TB0C_OUTPUT_WRITE_ACCUM (1 << 24)
-#define TB0C_ARG3_REPLICATE_ALPHA (1<<23)
-#define TB0C_ARG3_INVERT (1<<22)
-#define TB0C_ARG3_SEL_XXX
-#define TB0C_ARG2_REPLICATE_ALPHA (1<<17)
-#define TB0C_ARG2_INVERT (1<<16)
-#define TB0C_ARG2_SEL_ONE (0 << 12)
-#define TB0C_ARG2_SEL_FACTOR (1 << 12)
-#define TB0C_ARG2_SEL_TEXEL0 (6 << 12)
-#define TB0C_ARG2_SEL_TEXEL1 (7 << 12)
-#define TB0C_ARG2_SEL_TEXEL2 (8 << 12)
-#define TB0C_ARG2_SEL_TEXEL3 (9 << 12)
-#define TB0C_ARG1_REPLICATE_ALPHA (1<<11)
-#define TB0C_ARG1_INVERT (1<<10)
-#define TB0C_ARG1_SEL_ONE (0 << 6)
-#define TB0C_ARG1_SEL_TEXEL0 (6 << 6)
-#define TB0C_ARG1_SEL_TEXEL1 (7 << 6)
-#define TB0C_ARG1_SEL_TEXEL2 (8 << 6)
-#define TB0C_ARG1_SEL_TEXEL3 (9 << 6)
-#define TB0C_ARG0_REPLICATE_ALPHA (1<<5)
-#define TB0C_ARG0_SEL_XXX
-
-#define TB0A_CTR_STAGE_ENABLE (1<<31)
-#define TB0A_RESULT_SCALE_1X (0 << 29)
-#define TB0A_RESULT_SCALE_2X (1 << 29)
-#define TB0A_RESULT_SCALE_4X (2 << 29)
-#define TB0A_OP_MODULE (3 << 25)
-#define TB0A_OUTPUT_WRITE_CURRENT (0<<24)
-#define TB0A_OUTPUT_WRITE_ACCUM (1<<24)
-#define TB0A_CTR_STAGE_SEL_BITS_XXX
-#define TB0A_ARG3_SEL_XXX
-#define TB0A_ARG3_INVERT (1<<17)
-#define TB0A_ARG2_INVERT (1<<16)
-#define TB0A_ARG2_SEL_ONE (0 << 12)
-#define TB0A_ARG2_SEL_TEXEL0 (6 << 12)
-#define TB0A_ARG2_SEL_TEXEL1 (7 << 12)
-#define TB0A_ARG2_SEL_TEXEL2 (8 << 12)
-#define TB0A_ARG2_SEL_TEXEL3 (9 << 12)
-#define TB0A_ARG1_INVERT (1<<10)
-#define TB0A_ARG1_SEL_ONE (0 << 6)
-#define TB0A_ARG1_SEL_TEXEL0 (6 << 6)
-#define TB0A_ARG1_SEL_TEXEL1 (7 << 6)
-#define TB0A_ARG1_SEL_TEXEL2 (8 << 6)
-#define TB0A_ARG1_SEL_TEXEL3 (9 << 6)
-
-void gen2_render_copyfunc(struct intel_batchbuffer *batch,
- struct scratch_buf *src, unsigned src_x, unsigned src_y,
- unsigned width, unsigned height,
- struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
-{
- /* invariant state */
- {
- OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
- OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
- OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
- OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
-
- OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
- OUT_BATCH(FOGFUNC_ENABLE |
- FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
- MAP_UNIT(0) |
- DISABLE_TEX_STREAM_BUMP |
- ENABLE_TEX_STREAM_COORD_SET |
- TEX_STREAM_COORD_SET(0) |
- ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
- OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
- MAP_UNIT(1) |
- DISABLE_TEX_STREAM_BUMP |
- ENABLE_TEX_STREAM_COORD_SET |
- TEX_STREAM_COORD_SET(1) |
- ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
- OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
- MAP_UNIT(2) |
- DISABLE_TEX_STREAM_BUMP |
- ENABLE_TEX_STREAM_COORD_SET |
- TEX_STREAM_COORD_SET(2) |
- ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
- OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
- MAP_UNIT(3) |
- DISABLE_TEX_STREAM_BUMP |
- ENABLE_TEX_STREAM_COORD_SET |
- TEX_STREAM_COORD_SET(3) |
- ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
-
- OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
- OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
- OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
- OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
- OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
-
- OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
- ENABLE_POINT_RASTER_RULE |
- OGL_POINT_RASTER_RULE |
- ENABLE_LINE_STRIP_PROVOKE_VRTX |
- ENABLE_TRI_FAN_PROVOKE_VRTX |
- ENABLE_TRI_STRIP_PROVOKE_VRTX |
- LINE_STRIP_PROVOKE_VRTX(1) |
- TRI_FAN_PROVOKE_VRTX(2) | TRI_STRIP_PROVOKE_VRTX(2));
-
- OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
-
- OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
- OUT_BATCH(0);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
- OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
-
- OUT_BATCH(_3DSTATE_W_STATE_CMD);
- OUT_BATCH(MAGIC_W_STATE_DWORD1);
- OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
-
- OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
- OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
-
- OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
- OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
- TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
- TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
- TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
-
- /* copy from mesa */
- OUT_BATCH(_3DSTATE_FOG_COLOR_CMD |
- FOG_COLOR_RED(0) | FOG_COLOR_GREEN(0) | FOG_COLOR_BLUE(0));
-
- OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_MODES_1_CMD |
- ENABLE_COLR_BLND_FUNC |
- BLENDFUNC_ADD |
- ENABLE_SRC_BLND_FACTOR |
- SRC_BLND_FACT(BLENDFACTOR_ONE) |
- ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
- OUT_BATCH(_3DSTATE_MODES_2_CMD | ENABLE_GLOBAL_DEPTH_BIAS | GLOBAL_DEPTH_BIAS(0) | ENABLE_ALPHA_TEST_FUNC | ALPHA_TEST_FUNC(0) | /* always */
- ALPHA_REF_VALUE(0));
- OUT_BATCH(_3DSTATE_MODES_3_CMD |
- ENABLE_DEPTH_TEST_FUNC |
- DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */
- ENABLE_ALPHA_SHADE_MODE |
- ALPHA_SHADE_MODE(SHADE_MODE_LINEAR) |
- ENABLE_FOG_SHADE_MODE |
- FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
- ENABLE_SPEC_SHADE_MODE |
- SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
- ENABLE_COLOR_SHADE_MODE |
- COLOR_SHADE_MODE(SHADE_MODE_LINEAR) |
- ENABLE_CULL_MODE | CULLMODE_NONE);
-
- OUT_BATCH(_3DSTATE_MODES_4_CMD |
- ENABLE_LOGIC_OP_FUNC |
- LOGIC_OP_FUNC(LOGICOP_COPY) |
- ENABLE_STENCIL_TEST_MASK |
- STENCIL_TEST_MASK(0xff) |
- ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff));
-
- OUT_BATCH(_3DSTATE_STENCIL_TEST_CMD |
- ENABLE_STENCIL_PARMS |
- STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */
- STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */
- STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */
- ENABLE_STENCIL_TEST_FUNC |
- STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */
- ENABLE_STENCIL_REF_VALUE |
- STENCIL_REF_VALUE(0));
-
- OUT_BATCH(_3DSTATE_MODES_5_CMD |
- FLUSH_TEXTURE_CACHE |
- ENABLE_SPRITE_POINT_TEX | SPRITE_POINT_TEX_OFF |
- ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(0x2) | /* 1.0 */
- ENABLE_FIXED_POINT_WIDTH | FIXED_POINT_WIDTH(1));
-
- OUT_BATCH(_3DSTATE_STIPPLE);
-
- /* Set default blend state */
- OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
- TEXPIPE_COLOR |
- ENABLE_TEXOUTPUT_WRT_SEL |
- TEXOP_OUTPUT_CURRENT |
- DISABLE_TEX_CNTRL_STAGE |
- TEXOP_SCALE_1X |
- TEXOP_MODIFY_PARMS | TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
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